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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Multiplexer - Demultiplexer
The MC74VHC1G53 is an advanced high speed CMOS multiplexer - demultiplexer analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining CMOS low power dissipation. This multiplexer - demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The MC74VHC1G53 is compatible in function to a single gate of the High Speed CMOS MC74VHC4053 and the metal-gate CMOS MC14053. The device has been designed so that the ON resistances (RON) are much lower and more linear over input voltage than RON of the metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pull-up resistors, it is compatible with LSTTL outputs. * * * * High Speed: tPD = 4 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Diode Protection Provided on Inputs and Outputs Improved Linearity and Lower ON Resistance over Input Voltage than the MC14053B or the HC4053 * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300 mA * ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V
OUT/IN X 1 ENABLE 2 N/C 3 GND 4 8 VCC 7 IN/OUT X0 6 IN/OUT X1 5 CHANNEL SELECT
MC74VHC1G53
PLANNED PACKAGE 8-LEAD MICRO 8 PACKAGE Tamb = -55C to 125C
FUNCTION TABLE
Enable L L H Select L L X ON Channel X0 X1 NONE
VT ddd
PIN ASSIGNMENT
ENABLE CHANNEL SELECT OUT/IN X U 2X0 2X1
IN/OUT X0 IN/OUT X1
MARKING DIAGRAM d = date code
LOGIC SYMBOL
DEVICE ORDERING INFORMATION
Device Nomenclature Motorola Circuit Indicator MC Temp Range Identifier 74 Device Function 53 Package Suffix DM Tape and Reel Suffix R2 Package Pk Type Micro 8 Tape and R l T d Reel Size 13-Inch/4000 Unit
Device Order Number D i Od N b MC74VHC1G53DMT1
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/98
(c) Motorola, Inc. 1998
1
U U
Technology VHC1G
REV 0
MC74VHC1G53
ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. Exposureto these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.
Characteristics DC Supply Voltage Digital Input Voltage Analog Input Voltage Digital Input Diode Current DC Supply Current, VCC and GND Power dissipation in still air, Micro-8 Lead temperature, 1 mm from case for 10 s Symbol VCC VIN VIS IIK ICC PD TL Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC + 0.5 -20 25 300 260 -65 to +150 Unit V V V mA mA mW C C
Storage temperature Tstg Power Dissipation Derating: Micro-8 Package: - 4.4 mW/_C from 65_C to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics DC Supply Voltage Digital Input Voltage Analog Input Voltage Static or Dynamic Voltage Across Switch Operating Temperature Range Input Rise and Fall Time, SELECT & ENABLE Symbol VCC VIN VIS VIO* TA tr, tf Min 2.0 GND GND -- -55 Max 5.5 VCC VCC 100 +125 Unit V V V mV C ns/V
VCC = 3.3 V 0.3 V 0 100 VCC = 5.0 V 0.5 V 0 20 * For voltage drops across the switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G53
DC ELECTRICAL CHARACTERISTICS
VCC Symbol VIH Parameter Minimum High-Level Input Voltage ON/OFF Control Input Maximum Low-Level Input Voltage ON/OFF Control Input Maximum Input Leakage Current ON/OFF Control Input Maximum Quiescent Supply Current Maximum "ON" Resistance Test Conditions RON = Per Spec (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0 to 5.5 5.5 2.0 3.0 4.5 2.0 3.0 4.5 5.5 25 12 5 25 12 5 Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 0.1 TA = 25C Typ Max TA 85C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max TA 125C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max Unit V
VIL
RON = Per Spec
V
IIN
VIN = VCC or GND
A
ICC RON
VIN = VCC or GND VIO = 0 V VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1) Endpoints VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1)
2.0 50 20 10 50 20 10 0.1
20 70 30 15 65 26 13 0.5
40 100 45 25 90 40 22 1.0
A
W W
A
IOFF
Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel
VIN = VIL VIO = VCC to GND Switch Off (Figure 2) VIN = VIL VIO = VCC to GND Switch Off (Figure 3) VIN = VIH VIS = VCC to GND (Figure 4)
5.5
0.1
1.0
2.0
A
ION
Maximum On-Channel Leakage Current
5.5
0.1
0.5
1.0
A
II I I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0 ns)
Symbol S bl Parameter P Test C di i T Conditions VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0.0 5.0 TA = 25C Typ 1 0 0 0 TA 85C TA 125C Min Max 5 2 1 1 Min Max 6 3 1 1 Min Max 7 4 2 1 Unit Ui ns tPLH, tPHL Maximum Propagation Delay, Input X to X0 or X1 Maximum Propagation Delay, SELECT to Analog Output Maximum Propagation Delay, ENABLE to Analog Output Maximum Input Capacitance Figure 5 tPLH, tPHL Figure 6 15 8 6 4 15 8 6 4 3 4 4 35 15 10 7 35 15 10 7 10 10 10 46 20 13 9 46 20 13 9 10 10 10 57 25 17 11 57 25 17 11 10 10 10 ns tPZL, tPZH tPLZ, tPHZ CIN RL = 1000 W Figure 7 ns ON/OFF Control Input pF Analog I/O (Control Input = GND) Feedthrough Typical @ 25C, VCC = 5.0 V CPD Power Dissipation C P Di i i Capacitance ( i (per S i h) (N Switch) (Note 1) Fi Figure 8 pF F 18 (1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA
MC74VHC1G53
II II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Test Conditions VCC 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Limit { 25C 150 175 200 -50 -50 -50 -40 -40 -40 Unit BW Maximum On-Channel Bandwidth or Minimum Frequency Response Figure 9 fin = 1 MHz Sine Wave Adjust fin voltage to obtain 0 dBm at VOS Increase fin = frequency until dB meter reads -3 dB RL = 50 W, CL = 10 pF fin = Sine Wave Adjust fin voltage to obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF MHz ISOoff Off-Channel Feedthrough Isolation Figure 10 dB NOISEfeed Feedthrough Noise Channel Select to Switch Figure 11 Vin 1 MHz Square Wave (tr = tf = 2 ns) Adjust RL at setup so that Is = 0 A RL = 600 W, CL = 50 pF RL = 50 W, CL = 10 pF 45 60 100 25 30 60 mVPP THD Total Harmonic Distortion Figure 12 fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 3.0 VPP sine wave VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave % 3.3 4.5 5.5 0.20 0.10 0.06 Guaranteed limits not tested. Determined by design and verified by qualification. MOTOROLA 4 VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G53
PLOTTER VCC DC PARAMETER ANALYZER COMPUTER VCC 1 2 3 4 8 3 7 4 6 5 VIH 5 6 POWER SUPPLY + - VIH 1 2 8 7 A VCC
Figure 1. On Resistance Test Set-Up
VCC 1 2 3 4 8 7 6 5
Figure 2. Maximum Off-Channel Leakage Current Test Set-Up, Any One Channel
VCC VCC N/C 1 2 3 4 8 7 6 5 A VCC
VCC 1 2 1 VCC 2
A VIH
Figure 3. Maximum Off-Channel Leakage Current Test Set-Up, Common Channel
Figure 4. Maximum On-Channel Leakage Current Test Set-Up
TEST POINT 1 CL 2 3 4 8 7 6
VCC VCC
TEST POINT 1 CL 2 3 VCC 4 8 7 6 5
VCC
5
Figure 5. Propagation Delay Test Set-Up, Analog I/O to Analog I/O
Figure 6. Propagation Delay Test Set-Up, Channel Select to Analog I/O
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
MOTOROLA
MC74VHC1G53
Switch SW1 to Position 1 when testing tPLZ and tPZL Switch SW1 to Position 2 when testing tPHZ and tPZH Testing should be repeated with Switch SW2 in Position 2 to test both channels VCC VCC VCC 1 2 3 4 8 7 SW1 6 5 1 2 1 2 VCC 4 5 N/C 3 6 1 2 N/C 1 2 8 7 A
RL TEST POINT CL*
SW2 *Includes all probe and jig capacitance.
Figure 7. Propagation Delay Output Enable/ Disable to Analog Output Test Set-Up
Figure 8. Power Dissipation Capacitance Test Set-Up
fin VOS 1 dB Meter CL* 2 3 4 8 7 6 5 VCC VCC 0.1 mF dB Meter CL* fin VOS 1 2 3 4 8 7 6 5 VCC VCC 0.1 mF
VIS
RL
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 9. Maximum On-Channel Bandwidth Test Set-Up
Figure 10. Off-Channel Feedthrough Isolation Test Set-Up
TEST POINT
VOS 1 8 7 6 5
VCC RL RL V tr
TO DISTORTION VOS METER 1 RL CL* 2 3 4 8 7 6 5
fin VCC 0.1 mF
VIS
RL
CL*
2 3 4
IN
v 1 MHz + tf + 2 ns
VCC GND
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
VCC
Figure 11. Feedthrough Noise, Channel Select to Analog Out, Test Set-Up
Figure 12. Total Harmonic Distortion Test Set-Up
MOTOROLA
6
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G53
OUTLINE DIMENSIONS
PLANNED PACKAGE 8-Lead Micro 8 Tamb = -55C to 125C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --- 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --- 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028
-A-
K
-B-
PIN 1 ID
G D 8 PL 0.08 (0.003)
M
TB
S
A
S
-T-
SEATING PLANE
0.038 (0.0015) H
C J L
DIM A B C D G H J K L
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
7
MOTOROLA
MC74VHC1G53 INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process.
0.041 1.04
0.208 5.28
0.126 3.20
0.015 0.38
0.0256 0.65
inches mm
Micro8 POWER DISSIPATION
The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = TJ(max) - TA RJA the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 300 mW. 100C - 25C 250C/W
PD =
= 300 mW
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into
The 250C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 300 mW using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.
* The soldering temperature and time shall not exceed * When shifting from preheating to soldering, the maximum * After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. temperature gradient shall be 5C or less. 260C for more than 10 seconds.
MOTOROLA
8
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G53
2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A 1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)
12.30 11.70 (.484) (.461)
5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)
A
FEED DIRECTION
5.40 (.212) 5.20 (.205)
8.10 (.318) 7.90 (.312)
1.60 (.063) 1.50 (.059) TYP.
1.50 (.059) 1.30 (.052)
SECTION A-A
SECTION B-B
NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER.
*TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE BENDING RADIUS
EMBOSSED CARRIER
EMBOSSMENT
10
MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE
100 mm (3.937")
1 mm MAX
TAPE 1 mm (0.039") MAX 250 mm (9.843")
TYPICAL COMPONENT CENTER LINE
CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 13. Carrier Tape Specifications
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
9
MOTOROLA
MC74VHC1G53
t MAX
1.5 mm MIN (0.06") A 20.2 mm MIN (0.795")
13.0 mm 0.2 mm (0.512" 0.008")
50 mm MIN (1.969")
FULL RADIUS
G
Figure 14. Reel Dimensions
REEL DIMIENSIONS
Tape Size 12 mm A Max 330 mm (12.992") G 12.4 mm, +2.0 mm, -0.0 (0.49", +0.079", -0.00) t Max 18.4 mm (0.72")
DIRECTION OF FEED
BARCODE LABEL POCKET HOLE
Figure 15. Reel Winding Direction
MOTOROLA
10
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC1G53
CAVITY TAPE
TOP TAPE
TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN
COMPONENTS
TAPE LEADER NO COMPONENTS 400 mm MIN
DIRECTION OF FEED
Figure 16. Tape Ends for Finished Goods
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
11
MOTOROLA
MC74VHC1G53
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MOTOROLA 12
MC74VHC1G53/D VHC Data - Advanced CMOS Logic DL203 -- Rev 1

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