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" for more information + ! " FBGA users guide version 4.2 publication number 22247 revision j amendment 0 issue date november 1, 2002
november 1, 2002 version 4.2
? 2002 advanced micro devices, inc. advanced micro devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. this publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness for a particular application. amd ? assumes no responsibility for the use of any circuitry other than the circuitry in an amd product. the information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice. amd assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the information included herein. additionally, amd assumes no responsibility for the functioning of undescribed features or parameters. trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
FBGA user?s guide version 4.2, november 1, 2002 3 chapter 1: introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7 table 1.1: package highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 2: amd fine-pitch ball grid array (FBGA) - - - - - - - - - - - - - - 9 package construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2-1. FBGA construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 the impact of die size changes on FBGA package size . . . . . . . . . . . . . . . . . . . . . . . . . 9 the impact of die size changes on FBGA package size . . . . . . . . . . . . . . . . . . . . . . . . 10 FBGA package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2-2. 48-ball ball (4 mb to 32mb, x8/x16, low voltage) . . . . . . . . . . . . 11 figure 2-3. 48-ball (16 mb, x8, low voltage) . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2-4. 63-ball (32 mb to 64 mb, x8/x16, low voltage) . . . . . . . . . . . . . . 12 figure 2-5. 63-ball (32 mb to 1 gb, x8, low voltage) . . . . . . . . . . . . . . . . . . . 12 figure 2-6. 84-ball (32 mb to 4 gb, x16/x32 low voltage) . . . . . . . . . . . . . . 13 figure 2-7. 84-ball (32 mb to 128 mb, x16/x3240-ball (64 mb, x8, ultranand only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 3: amd fortified-bga - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 package construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3-1. fortified-bga construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 effects of solder ball diameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 fortified-bga migration and transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 fortified-bga (FBGA) pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3-2. 64-ball fortified-bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3-3. 80-ball fortified-bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chapter 4: amd multi-chip packaging - - - - - - - - - - - - - - - - - - - - - - 17 package construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4-1. 2-die mcp construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4-2. same-die stack (sds) mcp construction . . . . . . . . . . . . . . . . . . . 17 system integration and space savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4-3. 2-die stack (flash+sram) mcp . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4-4. same-die-stack (sds) mcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mcp package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4-5. am29dl16xd and 4mb (x8/x16) sram mcp pinout . . . . . . . . . 19 figure 4-6. am29dl32xd and 4mb (x8/x16) sram mcp pinout . . . . . . . . . 19 figure 4-7. am29dl32xd and 8mb (x8/x16) sram mcp pinout . . . . . . . . . 20 figure 4-8. am29dl64xd and 8mb (x8/x16) sram mcp pinout . . . . . . . . . 20 chapter 5: daisy chains - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 21 figure 5-1. FBGA 16 mbit daisy chain schematic (top view) . . . . . . . . . . . 22 figure 5-2. FBGA 16 mbit board layout (top view) . . . . . . . . . . . . . . . . . . . 22
FBGA user?s guide 4 version 4.2, november 1, 2002 figure 5-3. FBGA 32 mbit daisy chain schematic (top view) . . . . . . . . . . . 23 figure 5-4. FBGA 32 megabit board layout (top view) . . . . . . . . . . . . . . . . 23 figure 5-5. FBGA 64 mbit daisy chain schematic (top view) . . . . . . . . . . . 24 figure 5-6. FBGA 64 mbit board layout (top view) . . . . . . . . . . . . . . . . . . . 24 figure 5-7. FBGA 84-ball daisy chain schematic (top view) . . . . . . . . . . . . 25 figure 5-8. fortified bga 84-ball board layout (top view) . . . . . . . . . . . . . 25 figure 5-9. fortified bga 64-ball board layout (top view) . . . . . . . . . . . . . 26 figure 5-10. fortified bga 64-ball daisy chain schematic (top view) . . . . 26 figure 5-11. fortified bga 80-ball daisy chain schematic (top view) . . . . 27 figure 5-12. fortified bga 80-ball board layout (top view) . . . . . . . . . . . . 27 chapter 6: package physical description - - - - - - - - - - - - - - - - - - - - 28 FBGA package materials descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.1: FBGA-bt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FBGA-bt ball attach detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6-1. FBGA package ball attach detail . . . . . . . . . . . . . . . . . . . . . . . . . 49 FBGA thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6-2. path of heat dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 6.2: thermal resistance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 7: board design and layout considerations - - - - - - - - - - - 53 general design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 7-1. solder wetting around pad during reflow . . . . . . . . . . . . . . . . . . 53 recommended board design dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 7-2. recommended dimensions for the amd 0.30 mm solder ball . . . 54 routing considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 7-3. example of 48-ball single layer board routing . . . . . . . . . . . . . . 55 figure 7-4. example of 63-ball single layer board routing recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 7-5. example of interstitial via design for high ball count packages 56 chapter 8: component qualification testing - - - - - - - - - - - - - - - - - 57 preconditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8.1: moisture sensitivity levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 temperature cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 hast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 thermal shock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 data retention bake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 htol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 esd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 FBGA-bt component level test results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
FBGA user?s guide version 4.2, november 1, 2002 5 chapter 9: board level characterization studies - - - - - - - - - - - - - - 61 experimental design and procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 assembly of packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 stress testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 test procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 chapter 10:miscellaneous - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 65 shipping container information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 sockets for FBGA-bt packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FBGA package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 FBGA package designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 appendix a: article reprints - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 67 reliability evaluation of chip scale packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 fgbas?the csp of choice for flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 memo on j?t , case level thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 appendix b: application note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 85 daisy chain samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 revision summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 91 revision e (version 2.2): march 13, 1999. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 revision f (version 2.3): may 17, 1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 revision f+1 (version 2.3.1): july 30, 1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 revision g (version 3.0): january 15, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 revision g+1 (version 3.1): march 12, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 revision h (version 4.0): january 24, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 revision i (version 4.1): april 12, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 revision j (version 4.2): november 1, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FBGA user?s guide 6 version 4.2, november 1, 2002
FBGA user?s guide version 4.2, november 1, 2002 7 chapter 1: introduction there is a trend in the electron industry to miniaturize. from tower pcs to lap-tops to pocketpcs, from giant cell phones to pager size handsets, the demand for smaller feature rich electronic devices will continue for years to come. the trend for chip scale packages (csp) have grown tremendously since their introduction. applications such as cell phones, home entertainments, automotive engine controllers and networking equipments all have adopted csp packages into their systems. to address the needs of different applications such as small package size, reliability or migration compatibility, amd offers three families of csp: fine-pitch ball grid array (FBGA), fortified-bga and stacked-mcm table 1.1: package highlights package highlights benefits target applications FBGA package small package ideal for space constraint pcb designs ideal for application with space constraints. portable application such as mobile phones, camcorders and pdas would benefit most 1.2mm max package height ideal for low-provide application bt-resin superior board level reliability fortified-bga uniform 11x13mm package size simple and smooth migration and compatibility across densi- ties up to 256mb removes concerns for automotive, network- ing, telecom and other applications that de- mand the highest board level reliabilities 1.0mm ball pitch allows for more relax pcb de- sign rules 0.6mm ball diameter improves board level reliabilities stacked-mcm small package size idea for space constrain pcb de- signs enabling applications with increase memory for higher performance without increase in board space. ideally suited for camcorders, mobile phones, pdas and other wireless appli- cations 1.4mm max height idea for low-profile applications combines flash and sram increase memory capacity with no increase in board spaces
FBGA user?s guide 8 version 4.2, november 1, 2002 available combina- tions: 128mb flash + flash 16mb flash + 2mb sram 16mb flash + 4mb sram 32mb flash + 4mb sram 32mb flash + 8mb sram 64mb flash + 8mb sram 64mb flash + 16mb sram flexible memory combinations for number design possibilities and opportunities table 1.1: package highlights
FBGA user?s guide version 4.2, november 1, 2002 9 chapter 2: amd fine-pitch ball grid array (FBGA) the amd FBGA package family offers flash memory designers significant reduction in board real estate over thin small outline packages (tsops). in addition amd FBGA packages provide many advantages over other flash memory supplies? chip scale packages, sush as alternatives robust board level reliability and smooth pinout migrations. the packages are available for several popular 1.8-volt and 3.0-volt flash memory densities. the FBGA packages are constructed similar to conventional ic packages and are an extension of the proven bga technologies. for pcb assembly, existing equipment and proven manufacturing processes may be used. package construction amd FBGA is constructed on rigid bt-resin substrates. the die is mounted on the substrate and the leads are bonded using gold wires. the device is encapsulated in plastic and solder balls are attached to the bottom of the substrate. figure 2-1. FBGA construction note: package height = 1.2 mm max. the impact of die size changes on FBGA package size there are many costs associated with the manufacturing of semiconductor devices: die cost, assembly cost and testing costs just to name a few. the die cost typically has the most impact on the total manufacturing cost. in order to drive down the cost of the final product, semiconductor manufacturers

FBGA user?s guide 10 version 4.2, november 1, 2002 will stride to reduce die sizes. amd?s FBGA packages allow smaller, lower cost die to be placed in the same package without affecting package dimensions or requiring pc board redesigns. the impact of die size changes on FBGA package size the minimum distance between balls on the FBGA, the ball pitch, great affects an oem?s pc board technology and system routing complexity. device with ball pitches of 0.8mm can be easily be routed with today?s widely used and cost effect pc board technology (fr4 with 0.005 inch lines and spaces).
FBGA user?s guide version 4.2, november 1, 2002 11 FBGA package pinouts all pinouts are shown top view, with balls facing down. figure 2-2. 48-ball ball (4 mb to 32mb, x8/x16, low voltage) figure 2-3. 48-ball (16 mb, x8, low voltage) am29lv400b ball b2 = a17 am29lv800b am29dl800b am29sl800c ball c3 = a18 6 mm 8 mm 6 mm 9 mm am29lv320d am29ds323d am29pds322d ball d3 = a20 ball d3 = wp#/acc 6 mm 12 mm am29lv160d ball d4 = a19 am29dl16xd am29sl160c ball d4 = a19 ball b3 = wp#/acc 8 mm 9 mm 1 2 3 4 5 6 abcdefgh a13 a12 a14 a15 a16 byte# dq15 /a-1 v ss a9 a8 wp#/ acc a10 a11 dq7 dq14 dq13 dq7 a7 a17 a6 a5 dq0 dq8 dq9 dq1 a3 a4 a2 a1 a0 ce# oe# v ss we# re- set# ry/ by# nc a19 dq5 dq12 v cc dq4 a18 a20 dq2 dq10 dq11 dq3 8 m m 9 mm am29lv017d reset# a14 a13 a15 a17 nc vss a20 a9 a8 a11 a12 a19 a10 dq7 dq6 we# nc nc dq4 vcc ry/by # nc nc nc dq2 dq3 nc vcc a7 a18 a6 a5 dq0 nc dq1 nc a3 a4 a2 a1 a0 ce# vss oe# a16 dq5 nc abcdefgh 1 3 2 4 5 6
FBGA user?s guide 12 version 4.2, november 1, 2002 all pinouts in this chapter are shown top view, balls facing down. figure 2-4. 63-ball (32 mb to 64 mb, x8/x16, low voltage) figure 2-5. 63-ball (32 mb to 1 gb, x8, low voltage) abcdefg j hklm a13 a12 a14 a16 byte # vss dq15/ a-1 a9 a8 a10 a11 dq7 dq14 dq6 dq13 we# reset# a21 dq12 dq4 vcc ry/ by# wp#/ acc a18 a20 dq2 dq10 dq3 dq11 a7 a17 a6 a5 dq0 dq8 dq1 dq9 a3 a4 a2 a1 a0 ce# vss oe# a15 dq5 a19 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 8 6 7 5 4 1 2 3 * balls are shorted together via the substrate but not connected to the die 14 mm 8 m m am29dl32x 12 mm 1 1 m m am29lv640du dq15 j7 acc d4 a22 = 64 megabit a23 = 128 megabit a24 = 256 megabit a25 = 512 megabit a26 = 1 gigabit 14 mm 8 m m am29lv033c a14 a13 a15 a17 a24 vss a20 a9 a8 a11 a12 a19 a10 dq7 dq6 we# reset# a22 nc dq4 vcc ry/ by# acc a23 a25 dq2 dq3 a21 a7 a18 a6 a5 dq0 a26 dq1 nc a3 a4 a2 a1 a0 ce# vss oe# a16 dq5 nc nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* 1 3 2 4 5 8 7 6 abcdefg j hklm nc* nc* * balls are shorted together via the substrate but not connected to the die am29lv065d 12 mm 1 1 m m v io j4 v cc j4
FBGA user?s guide version 4.2, november 1, 2002 13 all pinouts in this chapter are shown top view, balls facing down. figure 2-6. 84-ball (32 mb to 4 gb, x16/x32 low voltage) figure 2-7. 84-ball (32 mb to 128 mb, x16/x3240-ball (64 mb, x8, ultranand only) c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a8 b8 e7 f7 g7 h7 j7 k7 ce# v ss a17 a16 a18 dq25 dq10 v ss dq14 oe# c8 d8 e8 f8 g8 h8 j8 k8 v cc a19 dq24 v ss dq11 dq28 dq29 dq15 a14 a13 a15 dq8 rfu rfu dq31/a-1 a21 a24 a23 nc a5, d5 a25 a26 rfu rfu ry/by# wp# a9 a10 a11 a12 rfu dq2 a0 a3 a6 a7 a8 dq21 dq5 dq18 dq16 dq0 dq23 v ss dq7 dq6 dq4 dq19 v ss dq1 c1 d1 e1 f1 g1 h1 j1 dq22 v cc v ss dq20 dq1 v cc dq17 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 word# a20 c9 d9 e9 f9 g9 h9 j9 dq9 v cc dq26 dq27 dq12 dq13 v cc b9 dq30 rfu we# acc reset# a2 a1 a5 a4 v cc am29pl3200du 11 mm 12 mm a20: 64 mb a21:128 mb a22: 256 mb a23: 512 mb a24: 1 gb a25: 2 gb a26: 4 gb 15 mm 8 m m 1 3 2 4 5 6 abcdefg j hk nc nc vss nc nc nc nc nc nc vss ce# re# ry/ by# io7 io6 io4 io5 se# nc nc the keep- out zone is composed of additional balls that will be on- center relative to the array. am30lv0064d keep-out zones four corners. may be required in higher density devices with larger packages. nc nc vcc nc nc nc nc nc nc vccq cle ale we# wp# io0 io1 io3 io2 nc nc
FBGA user?s guide 14 version 4.2, november 1, 2002 chapter 3: amd fortified-bga new performance driven applications continues to demand high board level reliability packages from flash memories. in addition, as pcb designs become increasingly complex, assembly-friendly package becomes more desirable. amd?s fortified-bga for the flash memory combines both superior reliability beyond the standard requirements and ease-of-use in one single package. it is ideal for telecom, networking, automotive and avionics applications. package construction amd?s fortified-bga is offer in a single easy to use 13x11mm x 1.4mm ht. package size, with 0.6mm solder ball diameter at 1.0mm ball pitch. designed around amd's already robust FBGA (0.8mm ball pitch), the fortified-bga uses industry proven bt-substrate to lower the cte mismatch between the substrate and the pcb. figure 3-1. fortified-bga construction note: package height = 1.4mm max. effects of solder ball diameter it is well known in the industry that solder ball diam eter has a direct affect on solder joint reliability during temperature cycling. lager solder balls typically yield higher standoff heights after board assembly. the importance of higher standoff is easiest explained through cte mismatch. as describe in many papers, higher standoff typically yields higher solder joint reliability during temperature cycling. amd's fortified-bga currently has the largest solder ball size (0.6mm diameters) of any

FBGA user?s guide version 4.2, november 1, 2002 15 bga package for flash memory. as a result, amd?s fortified-bga offers superior board level reliability, during temperature cycling, compared to other competitor?s bga packages. when compared to a competitor?s 10x13mm bga, the 64-ball (8x8 matrix) fortified-bga is expected to have a higher relative life by a factor of 4.3x, and the 80-ball (8x10 matrix) fortified-bga is expected be 4.6x higher relative life. fortified-bga migration and transition amd?s fortified-bga has taken amd?s tradition of simple pinout migration to higher density one step further. it virtually allows migration between densities without new board designs. fortified-bga?s 11x13mm package size is designed to host any flash density up to 256mb. this concept greatly lowers cost for customers. by anticipating future density needs, customers can virtually have one board design. furthermore, this ?one-package-fits-all? concept can also help trim equipment cost. the same socket, test boards, handlers, traces etc. are now interchangeable between densities. thereby increases the useful life of equipments. amd's fortified-bga takes full advantage of the real estate underneath the package. with 1.0mm ball pitch, pcb design rules can be more relaxed. at any drill or pad size, 1.0mm pitch provides more clearance for traces and spaces. for example, either 5mil or 7mil trace and space design rules can by used. more clearance also allows for larger via capabilities, ideal for multi-layer pcb designs. board assembly also benefits from 1.0mm ball p itch. amd's fortified-bga is aligned with many fpgas and micro-controller in terms of ball pitch. this allows for less expensive pcb technology to be used. amd's fortified-bga, in essence, simplifies customers' transition to bga packages. it is a low- cost, highly reliable csp solution to tsop and other traditional leaded packages. fortified-bga ( f bga) pinouts all pinouts are shown top view, with balls facing down.
FBGA user?s guide 16 version 4.2, november 1, 2002 figure 3-2. 64-ball fortified-bga figure 3-3. 80-ball fortified-bga abcdef gh vss a3 a1 a2 a0 a4 ce# oe# dq1 a7 a5 a6 dq0 a17 dq8 dq9 dq 3 ry/ by# a20 a18 dq2 dq10 dq 11 dq4 we# a19 a21 dq5 rs t# dq 12 vcc dq6 a9 a11 a10 dq7 a8 dq 14 dq 13 vss a13 a15 a14 a16 a12 1 2 3 4 5 6 rfu rfu rfu rfu rfu rfu vccq rf u rfu vccq a23 vss a22 a24 a25 7 8 abcdef gh abcdef gh vss a3 a1 a2 a0 a4 ce# oe# dq1 a7 a5 a6 dq0 a17 dq8 dq9 dq 3 ry/ by# a20 a18 dq2 dq10 dq 11 dq4 we# a19 a21 dq5 rs t# dq 12 vcc dq6 a9 a11 a10 dq7 a8 dq 14 dq 13 vss a13 a15 a14 a16 a12 1 2 3 4 5 6 rfu rfu rfu rfu rfu rfu vccq rf u rfu vccq a23 vss a22 a24 a25 7 8 vs s a3 a1 a2 a0 a4 ce # oe # dq 1 a7 a5 a6 dq0 a1 7 dq 8 dq9 dq 3 ry/ by# a2 0 a1 8 dq2 dq 1 0 dq11 dq 4 we# a1 9 a2 1 dq5 rst# dq 1 2 vc c dq 6 a9 a1 1 a1 0 dq7 a8 dq 1 4 dq13 vs s a13 a1 5 a1 4 a16 a1 2 rf u rfu rf u rf u rfu rfu vc c q rf u rf u rfu vc c q rf u vs s rf u rf u rf u 13 mm 11 mm am29lv640x ball b4 = acc ball f 7 = rfu ball g 1 = rf u ball g 7 = dq 15 am29lv642x ball b4 = acc ball f 7 = rfu ball g 1 = ce2# ball g 7 = dq 15 am29dl640x ball b4 = wp #/a cc ball f 7 = byte# ball g 1 = rf u ball g 7 = dq 15/a-1 a22 = 128mb a23 = 256mb a24 = 512mb a25 = 1gb 13 mm 11 mm am29bdd160g a19 = 32mb a20 = 64mb a21 = 128mb wo rd \ dq 16 dq 20 vcc q vs s vc c q dq29 a0 a1 nc ind\, wa it\ dq 18 dq 23 dq 24 dq 26 dq 30 a- 1 a4 we\ oe\ dq 19 dq21 dq25 dq 28 dq31 a7 a5 vc c ce\ dq 17 dq 22 ry/by\ dq 27 a2 1 nc a8 vss nc wp\ dq9 dq5 dq 1 a2 0 a1 0 a9 ck ad v\ dq 11 dq 10 dq 6 dq 2 a1 9 a1 1 a12 res et\ dq 14 dq 12 dq8 dq7 dq 4 dq0 a1 8 a13 vc cq dq15 dq 13 vccq vs s vccq dq 3 a1 7 a16 a2 a3 a6 vss acc vcc a14 a15 1 2 3 4 5 6 7 8 abcdefghj k word\ dq1 6 dq2 0 vc cq vss vc c q dq2 9 a0 a1 nc ind\, wait\ dq1 8 dq 2 3 dq2 4 dq2 6 dq30 a-1 a4 we\ oe \ dq1 9 dq 2 1 dq2 5 dq2 8 dq3 1 a7 a5 vc c ce\ dq1 7 dq 2 2 ry/by\ dq2 7 a2 1 nc a8 vs s nc wp \ dq9 dq5 dq1 a20 a10 a9 ck adv\ dq1 1 dq 1 0 dq6 dq2 a1 9 a11 a1 2 res et\ dq1 4 dq1 2 dq8 dq7 dq4 dq0 a18 a1 3 vccq dq1 5 dq1 3 vc cq vss vc c q dq3 a17 a1 6 a2 a3 a6 vs s ac c vc c a1 4 a1 5 13 mm 11 mm am29bdd160g a19 = 32mb a20 = 64mb a21 = 128mb wo rd \ dq 16 dq 20 vcc q vs s vc c q dq29 a0 a1 nc ind\, wa it\ dq 18 dq 23 dq 24 dq 26 dq 30 a- 1 a4 we\ oe\ dq 19 dq21 dq25 dq 28 dq31 a7 a5 vc c ce\ dq 17 dq 22 ry/by\ dq 27 a2 1 nc a8 vss nc wp\ dq9 dq5 dq 1 a2 0 a1 0 a9 ck ad v\ dq 11 dq 10 dq 6 dq 2 a1 9 a1 1 a12 res et\ dq 14 dq 12 dq8 dq7 dq 4 dq0 a1 8 a13 vc cq dq15 dq 13 vccq vs s vccq dq 3 a1 7 a16 a2 a3 a6 vss acc vcc a14 a15 wo rd \ dq 16 dq 20 vcc q vs s vc c q dq29 a0 a1 nc ind\, wa it\ dq 18 dq 23 dq 24 dq 26 dq 30 a- 1 a4 we\ oe\ dq 19 dq21 dq25 dq 28 dq31 a7 a5 vc c ce\ dq 17 dq 22 ry/by\ dq 27 a2 1 nc a8 vss nc wp\ dq9 dq5 dq 1 a2 0 a1 0 a9 ck ad v\ dq 11 dq 10 dq 6 dq 2 a1 9 a1 1 a12 res et\ dq 14 dq 12 dq8 dq7 dq 4 dq0 a1 8 a13 vc cq dq15 dq 13 vccq vs s vccq dq 3 a1 7 a16 a2 a3 a6 vss acc vcc a14 a15 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 abcdefghj k abcdefghj k word\ dq1 6 dq2 0 vc cq vss vc c q dq2 9 a0 a1 nc ind\, wait\ dq1 8 dq 2 3 dq2 4 dq2 6 dq30 a-1 a4 we\ oe \ dq1 9 dq 2 1 dq2 5 dq2 8 dq3 1 a7 a5 vc c ce\ dq1 7 dq 2 2 ry/by\ dq2 7 a2 1 nc a8 vs s nc wp \ dq9 dq5 dq1 a20 a10 a9 ck adv\ dq1 1 dq 1 0 dq6 dq2 a1 9 a11 a1 2 res et\ dq1 4 dq1 2 dq8 dq7 dq4 dq0 a18 a1 3 vccq dq1 5 dq1 3 vc cq vss vc c q dq3 a17 a1 6 a2 a3 a6 vs s ac c vc c a1 4 a1 5 word\ dq1 6 dq2 0 vc cq vss vc c q dq2 9 a0 a1 nc ind\, wait\ dq1 8 dq 2 3 dq2 4 dq2 6 dq30 a-1 a4 we\ oe \ dq1 9 dq 2 1 dq2 5 dq2 8 dq3 1 a7 a5 vc c ce\ dq1 7 dq 2 2 ry/by\ dq2 7 a2 1 nc a8 vs s nc wp \ dq9 dq5 dq1 a20 a10 a9 ck adv\ dq1 1 dq 1 0 dq6 dq2 a1 9 a11 a1 2 res et\ dq1 4 dq1 2 dq8 dq7 dq4 dq0 a18 a1 3 vccq dq1 5 dq1 3 vc cq vss vc c q dq3 a17 a1 6 a2 a3 a6 vs s ac c vc c a1 4 a1 5 word\ dq1 6 dq2 0 vc cq vss vc c q dq2 9 a0 a1 nc ind\, wait\ dq1 8 dq 2 3 dq2 4 dq2 6 dq30 a-1 a4 we\ oe \ dq1 9 dq 2 1 dq2 5 dq2 8 dq3 1 a7 a5 vc c ce\ dq1 7 dq 2 2 ry/by\ dq2 7 a2 1 nc a8 vs s nc wp \ dq9 dq5 dq1 a20 a10 a9 ck adv\ dq1 1 dq 1 0 dq6 dq2 a1 9 a11 a1 2 res et\ dq1 4 dq1 2 dq8 dq7 dq4 dq0 a18 a1 3 vccq dq1 5 dq1 3 vc cq vss vc c q dq3 a17 a1 6 a2 a3 a6 vs s ac c vc c a1 4 a1 5
FBGA user?s guide version 4.2, november 1, 2002 17 chapter 4: amd multi-chip packaging in portable consumer product segment such as cell phones, pdas, digital cameras and audio players there are demands to increase features and functionalities as well as for smaller, thinner product size. in order to meet these demands, amd launched a line of mcp (multi-chip package) products. through system integration and pcb optimization, mcp enhances system design in numerous ways such as reduce pcb size, lower pcb cost, reduce components, lighter weight, smaller system, increase features and customer flexibility. package construction figure 4-1. 2-die mcp construction figure 4-2. same-die stack (sds) mcp construction punch or drill via die - 2 bt resin substrate bt resin substrate 0.8mm (FBGA) solder ball pad solder mask gold bond wire (standard) 1.4 mm max mold compound (standard) die attach (standard) 0.3, 0.35mm (FBGA) die - 1 punch or drill via die - 2 bt resin substrate bt resin substrate 0.8mm (FBGA) solder ball pad solder mask gold bond wire (standard) mold compound (standard) die attach (standard) (FBGA) die - 1 punch or drill via die-2 bt resin substrate bt resin substrate 0.8mm (FBGA) 1.0mm (fortified-bga) solder ball pad solder mask gold bond wire (standard) 1.7 mm max (FBGA) 1.7 mm max (fortified-bga) mold compound (standard) die attach (standard) 0.45mm (FBGA) 0.6mm (fortified-bga) die-1 si spacer punch or drill via die-2 bt resin substrate bt resin substrate 0.8mm (FBGA) 1.0mm (fortified-bga) solder ball pad solder mask gold bond wire (standard) 1.7 mm max (FBGA) 1.7 mm max (fortified-bga) mold compound (standard) die attach (standard) 0.45mm (FBGA) 0.6mm (fortified-bga) die-1 si spacer
FBGA user?s guide 18 version 4.2, november 1, 2002 system integration and space savings mcps are gaining momentum in the industry as a system integration solution. in the cellular phone market, flash and sram mcp combinations have become very popular. it stacks one die on top of the other on a rigid bt-substrate. both chips are wire- bonded to the top of the substrate and overmolded with encapsulant, so lder balls on the bottom of the package . this technology allows companies to immediately ta ke advantage space savings, with either smaller or more feature rich products. two die stacking is typically use if the top die size is small enough not to cover the bond pad of the bottom die. however, if both dies are similar in size same-die-stacking (sds) must be use. sds uses a spacer-die, between the top die and the bottom, to allow for addiquiet wire bonding space of the bottom die. sds provides powerful flexibility to system integration. with sds, not only can components of two different application be integrate in single package, same components can also be integrated to added feature or higher densities, such as flash+flash. figure 4-3. 2-die stack (flash+sram) mcp figure 4-4. same-die-stack (sds) mcp
FBGA user?s guide version 4.2, november 1, 2002 19 mcp package pinouts all pinouts are shown top view, with balls facing down. figure 4-5. am29dl16xd and 4mb (x8/x16) sram mcp pinout figure 4-6. am29dl32xd and 4mb (x8/x16) sram mcp pinout 8 mm 11 mm 8 mm 11 mm 8 mm 11 mm a7 a3 a2 nc nc nc nc nc dq8 dq14 ce1#s lb#s wp#/acc we# a8 a11 b3 b1 b4 b5 b6 b7 b8 a6 ub#s reset# ce2s a19 a12 a15 c2 c3 c4 c5 c6 c7 c8 c9 a5 a18 ry/by# nc a9 a13 nc d2 d3 d4 d5 d6 d7 d8 d9 a1 a4 a17 a10 a14 nc e1 e10 e2 e3 e4 e7 e8 e9 v ss dq1 a0 dq6 sa a16 f1 f10 f3 f4 f2 f7 f8 f9 ce#f dq0 oe# dq9 dq3 dq4 dq13 dq15/a - 1 ciof g2 g3 g4 g5 g6 g7 g8 g9 dq10 v cc f v cc s dq12 dq7 v ss h2 h3 h4 h5 h6 h7 h8 h9 dq2 dq11 cios dq5 j3 j8 j4 j5 j6 j7 nc nc nc a1 a5 a6 nc a10 nc nc nc k1 k5 k6 nc k10 sram only shared flash only 69-ball FBGA top view 8 mm 11.6 mm 8 mm 11.6 mm 8 mm 11.6 mm a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa dq15/a-1 dq7 dq14 a15 nc nc a16 ciof v ss nc nc nc nc nc nc sram only shared flash only 73-ball FBGA top view
FBGA user?s guide 20 version 4.2, november 1, 2002 figure 4-7. am29dl32xd and 8mb (x8/x16) sram mcp pinout figure 4-8. am29dl64xd and 8mb (x8/x16) sram mcp pinout 8 mm 11.6 mm 8 mm 11.6 mm a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa dq15/a-1 dq7 dq14 a15 nc nc a16 ciof v ss nc nc nc nc nc nc sram only shared flash only 73-ball FBGA top view 8 mm 11.6 mm 8 mm 11.6 mm a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa dq15/a-1 dq7 dq14 a15 a21 nc a16 ciof v ss nc nc nc nc nc nc sram only shared flash only 73-ball FBGA top view
FBGA user?s guide version 4.2, november 1, 2002 21 chapter 5: daisy chains daisy chains are primarily requested by oems to perform assembly evaluations. prior to production, an oem will generally solder daisy chain samples on to a daisy chain pcb and perform open/short testing to check for misalignments. this test will help oems characterize its assembly process and equipment prior to full production. daisy chains are also used in second level solder-joint board reliability studies. the daisy chain samples are assembled onto the matching pcb and subjected to temperature cycling in an oven. board level reliability tests are tools to help predict and measure the expected life of a packages. for more in depth information on second level solder-joint board reliability, please refer to ?reliability evaluation of chip scale packages? by ranjit gannamani, viswanath valluri, sidharth, and meilu zhang (see ?article reprints?). for more in-depth information on daisy chains please refer to the ?daisy chain samples application note?. both are listed in the appendices.
FBGA user?s guide 22 version 4.2, november 1, 2002 figure 5-1. FBGA 16 mbit daisy chain schematic (top view) figure 5-2. FBGA 16 mbit board layout (top view) a and b are the input and output of the network for this device. abcdefgh 6 5 4 3 2 1 abcdefgh a b 6 5 4 3 2 1
FBGA user?s guide version 4.2, november 1, 2002 23 figure 5-3. FBGA 32 mbit daisy chain schematic (top view) figure 5-4. FBGA 32 megabit board layout (top view) notes: 1. a, b are the input and output of the network for the device. 2. c, d are the input and output of a separate network for the support balls. abcdef gh 1 2 3 4 5 6 a b cdef gh a b 1 2 3 4 5 6
FBGA user?s guide 24 version 4.2, november 1, 2002 figure 5-5. FBGA 64 mbit daisy chain schematic (top view) figure 5-6. FBGA 64 mbit board layout (top view) abcde fgh j klm 1 2 3 4 5 7 6 8 abcde fgh j klm 1 2 3 4 5 7 6 8 a c b d
FBGA user?s guide version 4.2, november 1, 2002 25 figure 5-7. FBGA 84-ball daisy chain schematic (top view) figure 5-8. fortified bga 84-ball board layout (top view) ak j h g f e d b c 9 1 2 3 4 5 6 8 7 ak j h g f e d b c 9 1 2 3 4 5 6 8 7 ak j h g f e d b c 9 1 2 3 4 5 6 8 7 ak j h g f e d b c 9 1 2 3 4 5 6 8 7
FBGA user?s guide 26 version 4.2, november 1, 2002 figure 5-9. fortified bga 64-ball board layout (top view) figure 5-10. fortified bga 64-ball daisy chain schematic (top view) abcde f gh 1 2 3 4 5 6 7 8 abcde f gh abcde f gh 1 2 3 4 5 6 7 8 abcde f gh 1 2 3 4 5 6 7 8 ab abcde f gh abcde f gh 1 2 3 4 5 6 7 8 ab
FBGA user?s guide version 4.2, november 1, 2002 27 figure 5-11. fortified bga 80-ball daisy chain schematic (top view) figure 5-12. fortified bga 80-ball board layout (top view) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 a bcdefghj k a bcdefghj k 1 2 3 4 5 6 7 8 abcdefghj k ab 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 abcdefghj k abcdefghj k ab
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FBGA user?s guide version 4.2, november 1, 2002 49 FBGA package materials descriptions table 6.1: FBGA-bt FBGA-bt ball attach detail the ball attach for the FBGA-bt package used a 0.4 mm pad size and a soldermask opening of 0.25 mm, therefore it is soldermask defined. the ball size is 0.3 mm nominal. note that figure 6-1 shows ball-to-package attach, not ball-to-printed circuit board attach. figure 6-1. FBGA package ball attach detail material type thickness (m) material name young?s modulus (pa) cte ppm/c poisson?s ratio mold compound 530 smt-b-1n 1.50e+10 1.60 0.25 die attach 25.4 qmi 536 1.24e+09 8.00 0.4 silicon die 254 silicon 1.31e+11 2.60 0.28 eutectic solder ball 300 sn/pb 63/37 3.10e+10 2.40 0.4 copper metalli- zation 27 cu 1.21e+11 1.70 0.34 wire 25.4 gold pad plating 13 ni 2.00e+11 1.34 0.31 solder resist 50 epoxy res- in 2.75e+09 6.90 0.3 substrate core 200 bt resin 2.60e+10 (ex = ey); 1.10e+10 (ez) 1.50 (ctex = ctey); 5.20 (ctez) 0.11 copper pad (0.4 mm) ball size (0.3 mm) FBGA-bt soldermask opening (0.25 mm)
FBGA user?s guide 50 version 4.2, november 1, 2002 FBGA thermal management thermal energy management is important in today?s rapidly changing microelectronics. to receive the best possible performance of any electronic product, proper heat dissipation is crucial. the temperature at which a microelectronic device operates determines among other things the speed and reliability of the product. proper thermal management is achieved when heat is transferred or dissipated from the device to the system air, which is then vented out of the system. a few of the most important factors affecting device operation temperature are power dissipation, air temperature, package construction, and cooling mechanisms. the combinations of these factors determine the device?s operation temperature. how well FBGA packages dissipate heat can be measured or described by ja , the junction to air thermal resistance value. figure 6-2. path of heat dissipation ja ? junction to air referring to figure 6-2, ja describes the path of heat dissipation from the active circuit surface of the die through the mold compound to the ambient air. the equations that govern this model are: ja = jt - ta jt = (t jss ? t tss )/p d ta = (t tss - t ass )/p d jt = thermal characterization parameter from device junction to the top center of the package surface (c/w). ja = package thermal resistance from the die junction to the ambient air (c/w). ja is a measurement of the package internal thermal resistance as well as the conductive and convective thermal resistance from the package exterior to the ambient. ta = thermal characterization parameter from top surface of the package-to-air (c/w) t jss = the junction temperature at steady-state. ( o c) die j t ta
FBGA user?s guide version 4.2, november 1, 2002 51 t tss = the package (top surface) temperature, at steady-state, measured by the thermocouple, infrared sensor, or fluoroptic sensor. t ass = temperature of ambient air at steady state p d = power (watts) table 6.2: thermal resistance data pkg type x pad dim. (mils) y pad dim. (mils) ext. die num. x die dim. (mils) y die dim. (mils) pd (mw) ja (c/w) jma (c/w) j?t (c/w) spd (lfpm) test code fba048 281 200 thermal 208 102 770 790 806 815 821 95.8 81.6 71.0 65.8 62.3 14.1 0 200 400 600 800 1s0p fba048 281 200 thermal 208 102 1417 1437 1445 1453 1456 49.2 45.5 43.6 42.2 41.4 6.1 0 200 400 600 800 2s2p fbb048 330 212 thermal 208 102 697 716 728 735 739 89 74.0 65.2 59.8 56.9 10.5 0 200 400 600 800 1s0p fbb048 330 212 thermal 208 102 1439 1461 1469 1476 1480 46 42.0 40.3 39.0 38.1 4.4 0 200 400 600 800 2s2p fbc048 319 315 thermal 208 102 878 901 917 926 933 78.8 65.4 56.9 51.9 48.7 5.3 0 200 400 600 800 1s0p fbc048 319 315 thermal 208 212 2010 2044 2057 2069 2077 35.7 32.2 30.6 29.4 28.5 3.9 0 200 400 600 800 2s2p fgc048 354 315 thermal 208 212 729 752 767 775 779 89.2 74.0 63.1 54.6 53.9 0 200 400 600 800 1sop fgb048 354 236 thermal 102 212 2412 42.5 0 2s2p
FBGA user?s guide 52 version 4.2, november 1, 2002 notes: 1. all measurement date are following semi g38-87 (in a wind tunnel), unless marked. 2. test code describes test pcb. ?2 signal layer+2 power layer? or ?1 signal layer+0 power layer? 3. for more information on thermal management please refer to ?memo on j-t case level thermal parameter? in the appendix. 4. jma = theta of junction to moving air. 5. spd (lfpm) = speed of moving air, in terms of ?linear feet per minute?. fgb048 354 236 thermal 102 212 1134 91 0 1s0p fbd063 528 315 thermal 420 212 1042 1073 1090 1101 1109 64.5 51.1 44.2 39.8 37.1 5.2 0 200 400 600 800 1s0p table 6.2: thermal resistance data (continued) pkg type x pad dim. (mils) y pad dim. (mils) ext. die num. x die dim. (mils) y die dim. (mils) pd (mw) ja (c/w) jma (c/w) j?t (c/w) spd (lfpm) test code
FBGA user?s guide version 4.2, november 1, 2002 53 chapter 7: board design a nd layout considerations general design considerations one of the first decisions to be made when designing boards for chip scale packages is whether it will be possible to use conventional pcb technology and design rules, or whether microvia technology will be necessary. recently, microvia hdi (high density interconnects) boards have been adopted in several volume applications, particularly in cell-phones and camcorders, and the prices of microvia boards have been falling quickly. hdi are defined as having vias with a diameter less than 0.006 inch on pad size of 0.014 inch or smaller. however they are still more expensive. measured on the basis of price per unit area per metal layer, microvia boards are at least twice as expensive as high-density conventional multilayer pcbs, even with blind and buried vias. furthermore, there is also the question of availability: it may not be easy to find suppliers with production capacity for microvia boards. it is for this reason that a pitch of 0.8 mm has been chosen for amd?s FBGA. as shown in the next section, single-layer routing for flash memory FBGA can be accomplished with line and space widths of 0.005 inch or more. because of the relatively low lead count, this can be done in one layer, but if desired, connections down to inner layers can be accomplished through interstitial vias. solder-mask defined versus non-solder-mask defined there has been much discussion about the relative merits of solder-mask defined (smd) and non- solder-mask defined (nsmd) lands for attaching area array packages such as conventional bga and fine pitch bga. amd?s FBGA can be used with either, but there are two important benefits of nsmd pads. one is that smaller copper pads can be used, thus providing more generous clearance for the routing channels. (another is that the solder can wet around the sides of the pad during reflow (see figure 7-1) thus providing a stronger joint.) figure 7-1. solder wetting around pad during reflow note that if the kind of wetting shown in figure 7-1 is desired, it is important to provide sufficient clearance of solder mask around the pad. the pcb supplier may consider the edge of the solder mask touching the edge of the pad to be acceptable, however, this condition would prevent the solder from completely wetting the side of the pad. copper attachment pad
FBGA user?s guide 54 version 4.2, november 1, 2002 pc board surface finish another design consideration is the selection of the surface finish for the board. while hot air solder leveled (hasl) boards have been successfully used for FBGA, it is generally felt that the domed shape of the pads makes it more difficult to achieve consistent assembly yields. on the other hand, excellent yields have been achieved with both ni/au plated pads and also with bare copper pads coated with organic solderability preservatives (osp). in the case of ni/au plated pads, it is important to control the plating quality to prevent embrittlement of the solder joint. this can occur if the gold is too thick; gold thickness of 5 mils maximum is recommended. there has been some concern in the industry that certain kinds of nickel plating can cause embrittlement?your pcb supplier should be able to give advice on this subject. recommended board design dimensions figure 7-2. recommended dimensions for the amd 0.30 mm solder ball dimension function recommended design value 0.30 mm solder ball 0.35 mm solder ball 0.60 mm solder ball a solder mask opening on the package 0.25 0.03 mm 0.30 0.03 mm 0.50 0.03 mm b copper pad dimension 0.23 0.01 mm 0.27 0.015 mm 0.40 0.03 mm c copper pad to solder mask clearance 0.075 0.025 mm 0.075 0.025 mm 0.075 0.025 mm ? trace width 0.125 0.25 mm 0.125 0.25 mm 0.125 0.25 mm package side is mask defined solder wets only the pad a b package side printed circuit board c
FBGA user?s guide version 4.2, november 1, 2002 55 routing considerations figure 7-3. example of 48-ball single layer board routing trace to pad gap 0.007 in. (0.175 mm)
FBGA user?s guide 56 version 4.2, november 1, 2002 figure 7-4. example of 63-ball single layer board routing recommendation note: recommended dimensions are the same as the 48-ball FBGA. figure 7-5. example of interstitial via design for high ball count packages pad diameter 0.21 to 0.24 mm via diameter 0.36 to 0.41 mm via capture pad diameter 0.56 to 0.61 mm pad pitch 0.800 mm pad to via capture pad gap 0.20 mm pad to pad diagonal pitch 1.132 mm via pad pad pad pad
FBGA user?s guide version 4.2, november 1, 2002 57 chapter 8: component qualification testing amd has one of the highest reliability standards in the industry. beginning from wafer sort to shipping of products, amd has implemented vary stages of testing to ensure high quality and reliability. samples are subjected to accelerated stress tests. the advantages of accelerated stress testing are that these tests use fewer parts and can make failures occur faster. the stress levels used for these tests are more severe than that seen in the field with well- designed tests resulting in the same failure mechanisms. component level testing includes: 1. preconditioning (moisture level testing) 2. temperature cycling 3. highly accelerated stress test (hast) 4. thermal shock 5. data retention bake 6. high temperature operating life (htol) 7. latch-up 8. electrostatic discharge (esd) preconditioning the moisture level testing is modeled after jedec/ipc standard j-std-020a. this test is designed to determine the safe environmental conditions for product exposure, thus reducing the risk of moisture induced damages. moisture damages may include, delamination, package cracks during reflows of board assembly, and ?popcorn? effects. there are six level of moisture sensitivity (see table 8.1). products are tested at level-1 conditions, if fail, the next higher level is tested until it passes. the only difference between each level is the parameter of the moisture soak (also know as preconditioning). there are 3 basic components: 1. 24 hour dry bake at 125c 2. preconditioning: moisture storage parameters depending on jedec moisture sensitivity level at which the package is being qualified (see table 8.1).
FBGA user?s guide 58 version 4.2, november 1, 2002 table 8.1: moisture sensitivity levels 3. three exposures to conditions to simulate passage through ir convection reflow. the first two passes are intended to simulate the assembly of a double-sided board, and the third pass to simulate a rework operation?as follows. ramp-up rate: +3 c/second max. temperature maintained at 125 25 c: 120 seconds max. time at maximum temperature: 10?20 seconds maximum temperature: 235+5/?0 c ramp-down rate: ?6 c/second max. temperature cycling temperature cycling is designed to simulate stress that the device may experience at temperature range of ?40c to 150c for 1000 cycles, at a rate of 3 cycles/hour. hast highly accelerated stress test (hast) is design to accelerate possible corrosion, delamination, possible wirebond failure, and intermetallic growths. hast is performed at constant temperature and relative humidity for a duration of time. example: 110c/85% unbiased for 264 hours. thermal shock thermal shock test the integrity of the device under extreme temperate gradients. level floor life soak requirements standard accelerated equivalent time conditions time (hours) conditions time (hours) conditions 1 unlimited 30 c/85% rh 168 85 c/85% rh 21 year 30 c/60% rh 168 85 c/60% rh 2a 4 weeks 30 c/60% rh 696 30 c/60% rh 120 60 c/60% rh 3 168 hours 30 c/60% rh 192 30 c/60% rh 40 60 c/60% rh 4 72 hours 30 c/60% rh 96 30 c/60% rh 5 24 hours 30 c/60% rh 48/72 30 c/60% rh 6 6 hours 30 c/60% rh 6 30 c/60% rh
FBGA user?s guide version 4.2, november 1, 2002 59 data retention bake this test ensures that the device loses no data. test is performed at constant temperature with a specific duration, example, 150c for 168 hours. htol high temperature operating life (htol) is sometimes refer to as infant mortality. this test is used to weed out any early life failures and is typically performed for 168 hours at 150c. latch-up to withstand accidental shorting, all the device pins must meet the specification requirements to withstand up to 200 ma stress from ?1 v to v cc + 1 v. esd electrostatic discharge (esd) test the sensitivity of the device. two kinds of esd tests are: hbm : human body model simulates the esd event from a human finger to a pin cdm: charge device model simulates the spark between a single pin of a charged leadframe and a metallic ground. component level testing consists of but is not limited to the above accelerated tests. as it is not feasible to monitor the reliability of each device types that amd produces, device representative and extend of test are selected based on complexity of wafer fabrication process and package type.
FBGA user?s guide 60 version 4.2, november 1, 2002 FBGA-bt component level test results package qualification data?contingent release package: fine pitch bga (FBGA-bt) package body size: 8 x 9 mm product: am29lv160, 16 mb flash test 16 mb FBGA-bt 8 x 9 mm package preconditioning 0/448 jedec level 3 235+5/-0 degrees temp cycle (-40 to 150c) t = 1000 cycles 0/150 hast (110c/85%) unbiased t = 264 hrs 0/150 thermal shock t = 15 cycles 0/32 data retention bake t = 168 hrs 0/195 htol t = 500 hours 0/150 latch-up pass esd-hbm 1.1 kv pass
FBGA user?s guide version 4.2, november 1, 2002 61 chapter 9: board level characterization studies as part of an internal characterization study and ongoing product improvement program, amd has conducted board-level testing of the FBGA package for flash memory. the testing includes copper lead frame tsop as a benchmark. as of late january 1999, the results are as follows. amd intends to continue the testing until 63% failures occurs or until 9,000 cycles are completed, whichever occurs sooner. experimental design and procedure board design csp test boards were designed to have six packages (of one package type) on each board, to ensure adequate spacing between adjacent packages. space considerations limited the tsop boards to four tsops per board. on each board, half the packages were oriented at 90 to the other half. these precautions ensure that the data collected is free of any effects of location / orientation. all the packages have a daisy chained die in them. the daisy chain circuit is completed on the board level so that each package consists of a single net. any failure on any solder ball can be immediately captured as a break in the daisy chain. the board is 20 mils thick, which replicates the construction of a standard pcmcia card. board fabrication standard printed circuit board (pcb) processes were used in the fabrication of the boards. 16 mb FBGA-bt (ase) 16 mb tsop i 48-pin tes t : 0/100c te s t: 0/100c cycles completed: 7847 cycles completed: 7847 sample size: 54 sample size: 40 failure # cycle # failure # cycle # 1st 5800 1st 5560 2nd 6521 2nd 5708 3rd 6581 3rd 5868 4th 7312 5th 7512 6th 7512 7th 7662
FBGA user?s guide 62 version 4.2, november 1, 2002 materials most of the laminates for pcbs in the industry are produced using epoxy resins. the choice of epoxy resin is made because of its outstanding electrical, mechanical, and thermal properties. fr-4 epoxy fiberglass laminate is the standard for all high te chnology and professional electronic assemblies, and is the material selected for this study. design parameters pad defined land pattern for the csps was chosen in order to achieve a good interface between the solder balls and the pcb pads. the circular pad has a diameter of 12 mils, and is dipped with eutectic 63sn/37pb solder with thickness of 0.5 to 0.8 mils. the clearance (or spacing) between solder mask and pads is 3 mils; and the registration is +/- 2 mils. no solder mask is allowed on the pads. liquid photo imageable solder mask is coated over base copper with maximum thickness of 3 mils. 5 mil nominal trace width is used for all trace routing. assembly of packages the test boards were not panelized during assembly. only one piece of board was on each panel. fixtures were used at all stages of the process, including printing. the boards were taped onto the fixtures using kapton tape. no clean process was us ed for this study because the stand off height for csps is very low, and cleaning and drying under the csp package could lead to contamination. solder paste screen printing dek 265lt screen printer with 300 mm metal squeegee was the equipment used for the solder paste printing process. lr737 rosin, a no-clean paste from alpha metals was used for the study. it is designed for stencil application in surface mounting process where post reflow cleaning is not required. it has mesh size of ?325, which is equivale nt to a particle size of less than 45 m diameter. the key criteria of stencil performance are vertical wall straightness, wall smoothness and dimensional precision. laser cut stencils were used, since the laser cutting processes can produce stencils with smooth and straight vertical walls. while screen printing solder paste, the stencil thickness and aperture dimensions are combined to achieve a balance between printing resolution and the avoidance of either starved solder joints or pad bridging. the stencil was designed to have a thickness of 3 mils and aperture of 12 mils in this study. during the solder printing process, visual inspection for smear, slump, missing, and bridging is performed for each board. paste height at random locations is measured through scanning laser microscopy (lsm) for one of every five boards. the average paste height is controlled at 3.6 mils with deviation of 0.3 mils.
FBGA user?s guide version 4.2, november 1, 2002 63 convection reflow the heller 1800, a forced air convection reflow system was used in the assembly of the boards. high concentrations of oxygen (if using air reflow) can degrade the components due to oxidation when they are at elevated temperatures. in particular , the problem of combustion of the flux in air gives rise to only a small available process-temperature window for the reflow process. using nitrogen can significantly eliminate the oxidation of the parts and extends the available process-temperature window for the test boards and fluxes. therefore, nitrogen was used for the reflow process. amd preferred to control the oxygen level below 20 ppm during the reflow process. however, there was no oxygen analyzer available at the contractor manufacturer site to measure the actual oxygen level when processing amd test boards. we can only state at this time that the maximum oxygen level was 100ppm during reflow. the reflow profile characteristics were as follows: o ramp to 110c with rate of 1.2c/sec. o dwell between 110 and 135c for 90 seconds. o maintain time above liquidus (183c) for 45 seconds. o reach peak temperature at 213 to 215c. o cool down with ramp rate of 1.5c/sec. stress testing the assembled boards were subjected to temperature cycling. this is the appropriate stress test to accelerate the wearout failure mechanism being invest igated which is solder joint fatigue, primarily driven by coefficient of thermal expansion (cte) mismatches. the 0/100c temperature cycling range is the most commonly used test condition in the industry for the board level reliability assessment of csps and it accelerates the correct failure mechanism. it is also probably going to be the future high density packaging users group (hdpug) standard, and there is consensus among north american users and manufacturers for this test condition. the exact temperature profile used was: o 30 min cycles o 10 min ramp up/down o 5 min soak at hot and cold temperatures this profile is again consistent with the future hdpug standard for csps. test procedure the following is a brief description of the various steps involved in carrying out the board level temperature cycling experiment.
FBGA user?s guide 64 version 4.2, november 1, 2002 initial resistances / harnessing the initial resistance values of each of the nets (each package forms a single net) being monitored are recorded. these resistance values serve as the baseline. any packages that are open at time-zero are not considered in the experiment. this can occur due to manufacturing or assembly defects. in this study however, there were no time-zero failures. the individual boards are then harnessed, so that they can be connected to the event detection equipment. harnessing is essentially the soldering of teflon coated ribbon wire to the end connectors on the test boards. temperature cycling chamber profiling this is done to ensure a uniform temperature across the different boards in the chamber. the fluke hydra data bucket is used to collect the thermal mapping data. measurements are made on three boards (top, middle, and bottom). on each board, measurements are made at three locations, i.e. the two sides and the center. these precautions ensure that all the boards are subjected the exact temperature cycling profile conditions. event detection / continuous monitoring the anatech ly515 (analysis technology) 256 channel event detector is used to monitor the nets in real time. event detectors detect resistance spikes over some preset resistance level. any instance of measured resistance value exceeding the threshold resistance value shall be considered as open. an open followed by 10 additional opens within 10% of the time of the first open shall be considered as a failure and the time to failure shall be the time at which the first open occurred. this is to avoid any measurement glitch or noise. test strategy data collected includes the number of failures, if any, cycles to failure and their location (specific board, specific net, etc.). it is intended to con tinue the tests to approximately 63% failure. at the completion of the testing, the failed units will be analyzed by microsectioning to confirm the validity of the failures.
FBGA user?s guide version 4.2, november 1, 2002 65 chapter 10: miscellaneous shipping container information up to date shipping container information for the FBGA package can be found at the amd web site: ic packages and packing. http://www.amd.com/products/packaging/toc.html sockets for FBGA-bt packages * closed top socket may be available. contact socket vendor. vendor socket FBGA 6x9 mm wells open top # 703-1048-07 FBGA 8x9 mm wells open top # 703-1048-04 rev a yamaichi open top # np351-04878 rev c FBGA 8x14 mm (63 balls) wells open top # 703-1063-01 yamaichi open top # np351-06377-n
FBGA user?s guide 66 version 4.2, november 1, 2002 FBGA package marking FBGA package designators note: these package codes are not marked on the package ? for ordering purposes only. architecture and voltage density and sector org. technology boot or uniform speed (ns) voltage range temp. range l = lv d = dl f = f s = ds 400 800 017 160 162 163 033 322 323 640 b = 0.32m/cs39s c = thin oxide 0.32 m/cs39ls d = 0.23 m/cs49s t = top b = bottom u = uniform 55 70 80 90 12 = 120 15 = 150 r = regulated v = full c i e logo @97-amd device designation 2 spaces year week xx yy assembly loc. lot info zzz fab/technology definition q 8 spaces 6 x 8 mm wa 6 x 9 mm wb 8 x 9 mm wc 11 x 12 mm wh 11 x 13 mm pa, pb, pc 6 x 12 mm wm 8 x 14 mm wd 8 x 15 mm wg 10 x 15 mm pe fine-pitch bga fortified bga
FBGA user?s guide version 4.2, november 1, 2002 67 appendix a: article reprints
FBGA user?s guide 68 version 4.2, november 1, 2002 reliability evaluation of chip scale packages r e l i a b i l i t y e v a l u a t i o n o f c h i p s c a l e p a c k a g e s ranjit gannamani, viswanath valluri, sidharth, and meilu zhang advanced micro devices sunnyvale, california a b s t r a c t this paper evaluates various chip scale packages (csp's) with respect to board level reliability under accelerated temperature cycling stress tests. the solder joint reliability of three different types (based on substrate material) of fine pitch ball grid array (FBGA) packages and the microbga package is compared. the results are analyzed using weibull data analysis and extrapolated to low cumulative percentage fails. the effect of package and board design parameters such as solder ball size and board thickness is also presented. key words: csp, bga, FBGA, solde r joints, reliability. i n t r o d u c t i o n the goal of smaller and portable electronic products is driving the development of csps. csps are close to the die size and are much smaller than conventional packages. in 8mb density flash memory for example, a tsop48 (thin small outline package) measures about 18.4mm x 12mm whereas a comparable csp (FBGA) would measure only 6mm x 9mm. often, different csps offer similar reliability at the component or package level. once they are mounted on boards, their ?second level? or ?board level? reliability could however be very different, and is based on the unique material set and construction of each package type. this study was undertaken to evaluate (i) the board level reliability of some csps of different construction, and (ii) the effect of package and board design parameters such as solder ball size and board thickness. p a c k a g e s e v a l u a t e d the following packages were evaluated: (i) FBGA with polyimide (pi) tape substrate, or FBGA-pi, (ii) FBGA with bt (bismaleimide triazine) substrate, or FBGA-bt (bt is the rigid epoxy glass laminate used in the conventional plastic ball grid arrays), (iii) FBGA with ceramic substrate, or FBGA-cer, and (iv) microbga. each package has a different material set and structural construction. figure 1, figure 2 and table 1 illustrate the key differences between the various FBGAs. the FBGA-pi uses a thin 0.08mm pi tape substrate, while the FBGA-bt uses a relatively thick 0.36mm bt substrate. both packages conform to the same overall package height of 1.2mm, which is the maximum package body height specified in the jedec FBGA specification. consequently, the FBGA-bt uses 0.3mm solder balls while the FBGA-pi uses 0.4mm solder balls. the differences between the physical dimensions of the FBGA-cer and FBGA-bt are minimal. f i g u r e 1 . c r o s s - s e c t i o n o f f b g a - p i f i g u r e 2 . c r o s s - s e c t i o n o f f b g a - b t t a b l e 1 . d i f f e r e n c e s i n f b g a c o n s t r u c t i o n the basic construction of these FBGA packages is to some extent similar to that of conventional ball grid arrays. the microbga (figure 3) however has a unique construction. it uses a compliant elastomer material between the die and the polyimide tape. tab type beam leads are bonded onto a u b o n d w i r e 0 . 8 0 m m p i t c h 0 . 3 0 m m ? b a l l 0 . 2 5 m m s t a n d o f f b t r e s i n s u b s t r a t e b t r e s i n s u b s t r a t e d i e m o l d c o m p o u n d m o l d c o m p o u n d d i e d i e 0 . 3 5 m m s t a n d o f f 0 . 8 0 m m p i t c h 0 . 4 0 m m ? b a l l f b g a - p i f b g a - b t f b g a - c e r b a l l s i z e 0.4mm 0.3mm 0.3 mm s o l d e r eutectic eutectic eutectic s u b s t r a t e t h i c k n e s s 0.08 mm 0.36 mm 0.35 mm s u b s t r a t e m a t e r i a l polyimide bt resin alumina d i e t h i c k n e s s 0.3 mm 0.26 mm 0.26 mm a v g p k g h e i g h t ( m e a s u r e d ) 0.96 mm 1.07 mm 1.18 mm w h e n m o u n t e d o n b o a r
FBGA user?s guide version 4.2, november 1, 2002 69 the die, and the die is ?face down? and exposed on the back side. f i g u r e 3 . c r o s s - s e c t i o n o f m i c r o b g a t e s t b o a r d s each fr-4 test board measured 3.5" x 2". both 20mil and 62mil boards were used in this study. six csps were assembled on each board (figure 4). on each board, half the packages were oriented at 90 degrees to the other half, and precautions were taken in the layout of the board to ensure that the data collected is free of any effects of location or orientation. the boards had non solder mask defined pads with a hasl finish. standard best practices such as no-clean solder paste, laser cut stencils, and nitrogen convection reflow were used in the assembly of the csps on the boards. each csp contains a daisy chained die. the daisy chain circuit is completed on the board such that each package consists of a single net through all the joints. f i g u r e 4 . a t y p i c a l c s p t e s t b o a r d t e m p e r a t u r e c y c l i n g a 0c to 100c, 30 minute single chamber air-to-air temperature cycling profile with 10 minute ramps and 5 minute dwells was used. this is one of the commonly used test profiles in the industry. an event detector was used to monitor the daisy chained test boards in real time. the event detector was set to record resistance spikes greater than 300 ohms for 200 nanoseconds. any spike greater than 300 ohms was considered as "open". a package was considered failed when the first open was followed by 10 additional opens within 10% of the time of the first open. the thermal cycling chamber was profiled before starting the test, to ensure a uniform temperature across the different boards in the chamber. wherever possible, the tests were continued to 63% fail or greater. m o d e l i n g t e c h n i q u e after temperature cycling was completed, the failure data was fitted to a weibull statistical distribu tion. the weibull parameters (n 63.2% ) and (slope) were obtained for the test, and the data extrapolated to a low cumulative failure percentage (100 ppm). the test data was then extrapolated to field use conditions and the projected field life (at 100 ppm) calculated, in order to enable a more intuitive comparison of the reliability of the different packages. the norris-landzberg modified coffin-manson equation [1] was used to calculate the acceleration factor. the two example field conditions used in this paper are shown in table 2. t a b l e 2 . e x a m p l e f i e l d c o n d i t i o n s r e s u l t s extensive temperature cycling data on the different csps was collected. the test program included various experimental splits with different combinations of package and board types. for clarity, the presentation of the results has been divided into the following five sections. ( a ) c o m p a r i s o n o f d i f f e r e n t p a c k a g e t y p e s the weibull plots for the 8x9mm FBGA-bt, 8x9mm FBGA-pi, microbga, and 6x9mm FBGA-cer are shown in figure 5. here, the FBGA-cer csp contains the 8mb density flash device, while the other three csps contain the 16mb density flash device. this data was collected on 20mil (0.5mm) boar ds under 0/100 degc cycling. the weibull slope and cycles to 63.2% failure (n63.2%) are shown in table 3. the weibull plots show that the FBGA-bt and microbga packages have significantly larger n63.2% values than the FBGA-pi and FBGA-cer packages. it is too be noted that the initial microbga failures are not solder joint failures and a discussion follows in a later section. from figure 5 and table 3, it can be seen that the slope of the distribution is different for various sets of data and hence a direct comparison of n63.2% fails is not feasible for the whole set of data. it is pertinent to compare the results at low ppm cumulative percentage failure mark. hence, the 100 ppm number, which seems to be a very conservative number accepted in the industry, was chosen. figure 6 shows comparative life projections in the two example field conditions defined in table 2. in termsof board level reliability, it can be seen from figure 6 that the FBGA-bt and microbga ranked much higher than the other packages. both these packages demonstrated e x a m p l e f i e l d c o n d i t i o n s t e m p e r a t u r e s w i n g c y c l e s / d a y 40 c / 60 c 1 -15 c / 25c 1 e n c a p s u l a n t s o l d e r b a l l ( 6 3 / 3 7 p b s n ) a d h e s i v e p o l y i m i d e t a p e ( 5 0 u m ) e l a s t o m e r c u i n t e r c o n n e c t p i v i a : 0 . 3 3 n o m . d i e d i e b a l l d i a : 0 . 3 5 n o m . p i t c h : 0 . 7 5 m m . 1 . 0 0 m m m a x 0 . 2 3 m m
FBGA user?s guide 70 version 4.2, november 1, 2002 f i g u r e 5 . w e i b u l l p l o t s f o r v a r i o u s c s p s t a b l e 3 . w e i b u l l p a r a m e t e r s f o r v a r i o u s c s p s f i g u r e 6 . f i e l d l i f e p r o j e c t i o n s lifetimes considerably higher than the requirements of most customer applications. the 8x9mm FBGA-pi and 6x9mm FBGA-cer data translated to lower field life projections. the life projections in ?years? shown in figure-6 are for those two specific field conditions only. the estimation of lifetimes would vary depending upon the specific field conditions and the model used to calculate the acceleration factors between test and field. however, the key observation to be made is that the relative size of the different bars is a true representation of the comparative reliability of the different csps at the board level. the higher reliability of the FBGA-bt package can be attributed to the thick and rigid bt substrate isolating the silicon die (low cte) from the solder joint and the board. in the case of the microbga package, the compliant elastomer material isolates the silicon die from the solder joint and the board, and contributes to the high reliability. the comparatively lower reliability of the FBGA-pi is due to the fact that the package construction is dominated by the low cte silicon die. as seen in the package cross section, it is only the die attach layer and the copper traces on the pi substrate that separate the solder ball from the die. the pi tape itself is not in the path; it has openings that define the pads for ball attachment. the lower reliability of the FBGA-cer packages was expected since there is both global and local cte mismatch with the fr-4 board. a potential use of this package might be on ceramic boards, but that issue is not discussed in this study. on completion of the tests, failure analysis was carried out on a sample of the test vehicles. figure 7 shows micro- sections of the FBGA-pi and FBGA-bt test boards. solder joint cracks at the interface on the component side are seen. this is consistent with the classic bga solder joint failure mechanism that is well documented in the literature. figure 8 shows the results of the failure analysis on some of the initial microbga failures. a lifted beam lead was detected. the isolation of the low cte die by the compliant elastomer results in the beam leads absorbing most of the cyclic fatigue stress in temperature cycling. f i g u r e 7 . f a i l u r e a n a l y s i s o f f b g a - p i ( l e f t ) a n d f b g a b t ( r i g h t ) . c r a c k s o n c o m p o n e n t s i d e . f i g u r e 8 . f a i l u r e a n a l y s i s o f m i c r o b g a c o m p a r i s o n o f p a c k a g e s a t 1 0 0 p p m c u m e f a i l 4 0 c / 6 0 c , 1 c y c / d a y 0 20 40 60 80 100 ubga 8x9mm FBGA-bt 8x9mm FBGA-pi 6x9mm FBGA-cer p r o j e c t e d l i f e ( y r s ) c o m p a r i s o n o f p a c k a g e s a t 1 0 0 p p m c u m e f a i l - 1 5 c / 2 5 c , 1 c y c / d a y 0 20 40 60 80 100 ubga 8x9mm FBGA-bt 8x9mm FBGA-pi 6x9mm FBGA-cer p r o j e c t e d l i f e ( y r s w e i b u l l p l o t f o r v a r i o u s c s p s -6.9 -4.6 -2.3 0 2.3 4.6 6.9 9.2 11.5 l n ( c y c l e s ) l n ( l n ( 1 / ( 1 - f ( x ) ) ) ) 8x9 FBGA-bt 8x9 FBGA-pi 6x9 FBGA-cer ubga 63.2% 10% 1% 0.1% 99.99% (100000) (10000) (1000) (100) p a c k a g e n 6 3 . 2 ( c y c ) b e t a # f a i l s / s s 8x9 mm FBGA-bt 11586 5.0 39 / 48 8x9 mm FBGA-pi 2295 3.9 52 / 60 6x9 mm FBGA-cer 1918 5.2 46 / 60 microbga 9240 4.8 35 / 60
FBGA user?s guide version 4.2, november 1, 2002 71 in these experiments, the FBGA-bt packages (0.3mm solder balls) were assembled on test boards that were initially designed for the FBGA-pi package (0.4mm solder balls). the test boards were designed to have 0.3mm pads that matched the 0.3mm openings in the pi tape (where the solder balls are attached) of the FBGA-pi package. the corresponding opening in the solder mask of the FBGA-bt package is 0.25mm. it is hence expected that the use of test boards designed or optimized for the FBGA-bt package could result in even better FBGA-bt data than that presented here. ( b ) e f f e c t o f p a c k a g e b o d y s i z e i n f b g a - p i the FBGA-pi test discussed in the earlier section was on the 8x9mm body size, which is the package for the 16mb density flash product. the 6x9mm FBGA-pi, the package size for the 8mb density device, was also put on the 0/100 degc test. in this case also, 20mil test boards were used. figure 9 shows the weibull plots for both the 8x9mm and 6x9mm FBGA-pi packages. the relevant weibull parameters are in table 4 and field life projections in figure 10. as seen in the weibull plots and the field life projections, the larger 8x9mm package demonstrated a lower lifetime than the 6x9mm package. this difference is attributed to the larger package body size and the larger die size of the 16mb device, i.e. the domination of the low cte silicon die is more pronounced in the larger package for the higher density flash product. based on these findings, it was anticipated that even larger packages for higher density products (32/64mb) would show poorer solder joint lifetimes in the FBGA-pi package due to the same reasons. f i g u r e 9 . e f f e c t o f p a c k a g e b o d y s i z e i n f b g a - p i t a b l e 4 . w e i b u l l p a r a m e t e r s f o r d i f f e r e n t b o d y s i z e s ( c ) u s e o f l a r g e r s o l d e r b a l l s o n f b g a - p i design / package changes to improve the board level reliability of the FBGA-pi were investigated. design parameters that may impact the board level reliability are substrate material, substrate thickness, mold compound f i g u r e 1 0 . f i e l d l i f e p r o j e c t i o n s material, die attach compliancy, solder ball size, etc. the package design variable evaluated here was solder ball size. the solder ball size on the initial FBGA-pi package was 0.40mm nominal. this ball size was increased to 0.45mm nominal. though the ball size was increased, the overall height of the package was maintained below 1.2mm. the pi tape opening was increased from 0.3mm to 0.38mm. the new test boards had 0.35mm pads. based on industry practice, this was deliberately maintained a little smaller than the 0.38mm pi tape openings on the new FBGA-pi package. figure 11 shows the weibull plots for both the 0.4mm ball and 0.45mm ball FBGA-pi packages. the relevant weibull parameters are in table 5. figure 12 shows the field life projections for the FBGA-pi packages with 0.40mm and 0.45mm solder balls. as expected, the use of the larger solder balls results in an improved solder joint lifetime. f i g u r e 1 1 . u s e o f l a r g e r s o l d e r b a l l s o n f b g a - p i t a b l e 5 . w e i b u l l p a r a m e t e r s f o r s o l d e r b a l l s i z e from the weibull plots it can be seen that it is challenging to quantify the improvement due to the use of larger solder c o m p a r i s o n o f p a c k a g e s a t 1 0 0 p p m c u m e f a i l - 1 5 c / 2 5 c , 1 c y c / d a y 0 10 20 30 40 6x9mm FBGA-pi 8x9mm FBGA-pi p r o j e c t e d l i f e ( y r s e f f e c t o f p a c k a g e b o d y s i z e w e i b u l l p l o t f o r 6 x 9 m m a n d 8 x 9 m m f b g a - p i -6.9 -4.6 -2.3 0 2.3 4.6 6.9 9.2 11.5 l n ( c y c l e s ) l n ( l n ( 1 / ( 1 - f ( x ) ) ) ) 6x9 FBGA-pi 8x9 FBGA-pi 63.2% 10% 1% 0.1% 99.99% (10000) (100000) (1000) (100) 8 x 9 m m f b g a - p i w i t h l a r g e r s o l d e r b a l l s -6.9 -4.6 -2.3 0 2.3 4.6 6.9 9.2 11.5 l n ( c y c l e s ) l n ( l n ( 1 / ( 1 - f ( x ) ) ) ) 8x9 FBGA-pi 0.4 mm dia ball 8x9 FBGA-pi 0.45 mm dia ball 63.2% 10% 1% 99.99% p a c k a g e n 6 3 . 2 ( c y c ) b e t a # f a i l s / s s 8x9 mm FBGA-pi, 0.40 ball 2295 3.9 52 / 60 8x9 mm FBGA-pi, 0.45 ball 2424 5.5 40 / 60 p a c k a g e n 6 3 . 2 ( c y c ) b e t a # f a i l s / s s 8x9 mm FBGA-pi 2295 3.9 52 / 60 6x9 mm FBGA-pi 2685 6.0 38 / 60
FBGA user?s guide 72 version 4.2, november 1, 2002 balls. while the n63.2% values are relatively close, the different slopes tend to amplify the difference between the two datasets, especially when projected to lower ppm. for example, if a 1000 ppm criterion is used, the improvement obtained (of 1.8x) is significantly lower than that shown in figure 12 (2.1x). to get an average picture of the whole data the slopes from the two datasets were pooled to obtain a common slope of 4.7, and an n63.2% fitted to both datasets. now comparing n63.2% values results in an improvement of 1.13x with the use of larger solder balls. from this analysis it is seen that even in a best case scenario for the larger solder balls, the improved lifetime is still lower than that of the FBGA-bt and microbga packages. f i g u r e 1 2 . f i e l d l i f e p r o j e c t i o n it should also be noted that at 0.45mm, the solder ball size is quite close to the maximum possible for the solder ball array with a pitch of 0.8mm, in order to retain sufficient room to route traces to internal solder balls. additionally, the eventual move to a 0.5mm pitch solder ball array (necessitated by shrinking die sizes due to improved fab processes, and the need for smaller form factor packages) will make the use of a 0.45mm ball impossible. the FBGA-bt package that currently uses 0.3mm solder balls would be able to transition to a 0.5mm solder ball pitch without requiring a change in ball size. ( d ) e v a l u a t i o n o f t e s t v e h i c l e s b u i l t o n 6 2 m i l b o a r d s all the data discussed in earlier sections was collected on test boards that were 20mil thic k. testing (0/100 degc cycling) was also carried out on 62mil (1.6mm) boards to evaluate the effect of these thicker boards on the solder joint lifetimes. figure 13 shows the weibull plots for the 6x9mm FBGA-pi on both 20mil and 62mil boards. figure 14 shows similar plots for the 8x9mm FBGA-bt package. the relevant weibull parameters are listed in table 6. it should be noted here that the FBGA-bt / 62mil board data presented here is preliminary. this will be updated as more failures are collected. it can be seen from figure 13 that the same challenge of quantifying the difference (as outlined in the previous section) exists for these two sets of FBGA-pi data as well. using the technique of pooling to a common slope of 7 and recomputing the n63.2% values, it is found that on an average, the solder joint life on thinner board exceeds that on the thicker board by 1.34x for FBGA-pi package. the slope (beta) for the thicker board was higher than that for thinner board, and so projections to a low ppm value showed minimal difference (figure 15). for the FBGA-bt package the results are preliminary as the tests on 62mil boards are still in progress. initial data shows minimal difference as the failures obtained so far have lined up on the existing data on the 20mil boards (see figure 14 and preliminary life projections in figure 15). it should also be noted that that the 62mil boards were assembled at a different site. hence, while these may not be exact comparisons the information presented is still useful to demonstrate that there is no significant difference in the lifetimes projected even when the same packages are assembled on thicker boards. f i g u r e 1 3 . f b g a - p i o n 2 0 a n d 6 2 m i l b o a r d s f i g u r e 1 4 . f b g a - b t o n 2 0 a n d 6 2 m i l b o a r d s t a b l e 6 . w e i b u l l p a r a m e t e r s 6 x 9 m m f b g a - p i o n 2 0 m i l a n d 6 2 m i l b o a r d s -6.9 -4.6 -2.3 0 2.3 4.6 6.9 9.2 11.5 l n ( c y c l e s ) l n ( l n ( 1 / ( 1 - f ( x ) ) ) 6x9 FBGA-pi/20 mil board 6x9 FBGA-pi/62 mil board 63.2% 10% 1% 0.1% 99.99% (10000) (100000) (1000) (100) 8 x 9 m m f b g a - b t o n 2 0 m i l a n d 6 2 m i l b o a r d s -6.9 -4.6 -2.3 0 2.3 6.9 9.2 11.5 l n ( c y c l e s ) l n ( l n ( 1 / ( 1 - f ( x ) ) ) ) 8x9 FBGA-bt/20 mil board 8x9 FBGA-bt/62 mil board 63.2% 10% 1% 0.1% 99.99% (10000) (100000) (1000) c o m p a r i s o n o f p a c k a g e s a t 1 0 0 p p m c u m e f a i l - 1 5 c / 2 5 c , 1 c y c / d a y 0 10 20 30 40 8x9mm FBGA-pi, 0.4 mm ball 8x9mm FBGA-pi, 0.45 mm ball p r o j e c t e d l i f e ( y r s p a c k a g e n 6 3 . 2 ( c y c ) b e t a # f a i l s / s s 6x9 mm FBGA-pi, 20mil board 2685 6.0 38 / 60 6x9 mm FBGA-pi, 62mil board 1932 7.9 45 / 48 8x9 mm FBGA-bt, 20mil board 11586 5.0 39 / 48 8x9 mm FBGA-bt, 62mil board 11757 5.2 5 / 30
FBGA user?s guide version 4.2, november 1, 2002 73 f i g u r e 1 5 . e v a l u a t i o n o n 6 2 m i l b o a r d s ( e ) t e m p e r a t u r e c y c l i n g a t - 4 0 / 1 0 0 d e g c a limited amount of data was also collected at the -40/100 degc, 30 minute cycle test condition on 20mil boards. table 7 is a summary of that data. the 8x9mm FBGA-bt and the 8x9mm FBGA-pi packages were evaluated. the test was terminated at 2507 cycles. at that point, there were zero fails (0/60) of the FBGA-bt test vehicles and extensive failures (49/60) in the FBGA-pi test vehicles. while no field projections are included here, this information again gives an indication of the relative robustness of the two packages. t a b l e 7 . b o a r d l e v e l r e l i a b i l i t y d a t a a t ? 4 0 / 1 0 0 d e g c t e s t c o n d i t i o n c o n c l u s i o n s (i) in the packages evaluated, the FBGA-bt and microbga demonstrated lifetimes considerably higher than the FBGA-pi and FBGA-ceramic packages. these differences in board level reliability can be explained by the differences in package construction and material sets. (ii) in the FBGA-pi package, the larger 8x9mm package for the higher density 16mb device (larger silicon die) demonstrated lower reliability than the 6x9mm package for the 8mb device. based on this trend, it was anticipated that even larger packages (for 32/64mb) would show lower solder joint lifetimes in the FBGA-pi construction. (iii) the use of the larger solder balls (0.45mm vs. 0.4mm) on the FBGA-pi package resulted in an improved solder joint fatigue life. even in the best case scenario for the larger solder balls, the improved lifetime was still lower than that of FBGA-bt and microbga packages. feasibility of using a 0.45mm ball size would be challenged as migration to 0.5mm ball pitch is made. (iv) at 100 ppm no significant difference in the board level reliability was detected for both the FBGA-bt and FBGA-pi packages assembled on the thicker 62mil boards when compared to those mounted on the 20mil boards. (v) limited data at the -40/100 degc test condition indicates the relative robustness of FBGA-bt over FBGA-pi with respect to board level reliability, that is consistent with the rest of the 0/100 degc data discussed in this paper. a c k n o w l e d g m e n t the authors would like to acknowledge melissa lee, john hunter, bruce schupp, james hayward, and ed fontecha for their guidance and support, dave morken for the sem analysis and robert dudero for cross-sectioning of the samples. r e f e r e n c e s [1] k. norris and a. landzberg, ibm journal of research and dev, 13, pp 266, 1969. [2] k. ano, et al, ?reliability study of the chip scale package using flex substrate?, smi proc, pp44-47, 1997. [3] r. darveaux, j. heckman, a. mawer, ?effect of test board design on the 2 nd level reliability of a fine pitch bga package?, proc of smi, pp 105-111, 1998. [4] c.f. coombs jr., ?printed circuits handbook?, mcgraw hill, ny, 1995. e f f e c t o f b o a r d t h i c k n e s s c o m p a r i s o n a t 1 0 0 p p m c u m e f a - 1 5 c / 2 5 c , 1 c y c / d a y 0 25 50 75 100 6x9 FBGA-pi, 20mil board 6x9 FBGA-pi, 62mil board 8x9 FBGA-bt, 20mil board 8x9 FBGA-bt, 62mil board p r o j e c t e d l i f e ( y r s ) t e s t c o n d i t i o n : - 4 0 / 1 0 0 d e g c 8 x 9 f b g a - b t 8 x 9 f b g a - p i c y c l e s c o m p l e t e d 2507 2507 d a t a n o f a i l s 49 fail out of 60 out of 60 f i r s t f a i l a t : n/a 754 t e s t s t a t u s stopped stopped
FBGA user?s guide 74 version 4.2, november 1, 2002 fgbas?the csp of choice for flash memories msg the csp of choice for flash memories FBGAs ? when it comes to package technology for flash memories, amd can do anything that can be done. we have the licenses, the technology, and the ability. ? bruce schupp, nvd product marketing a publication of the manufacturing services group amd recently played a pivotal role in the emergence of the FBGA (fine pitch ball grid array) as the new chip scale pack- age (csp) of choice for flash memory devices. this time two years ago, the micro ball grid array ( bga) was the only csp available for downsizing from the larger, traditional leaded packages used for flash memories (such as the thin small outline plastic (tsop) package). that changed last year when amd be- gan offering an FBGA design that afforded so many advantages, it put a fork in the package roadmap for flash memories in automotive, telecom, and new consumer product applications (e.g., cellu- lar phones, pagers, hand-held computers, etc.). as this story unfolds, you will see how amd persevered in the face of an estab- lished preference for intels bga to win overwhelming acceptance of the FBGA as the preferred csp in these applications. package size matters in applications where miniatur- ization is a priority, csps are a crucial stepping stone on the way to direct chip attach (dca), in which the die is bonded directly 2000
FBGA user?s guide version 4.2, november 1, 2002 75 figure 1 shows the smaller size of csps next to a comparable density tsop. figure 2 shows a cross-section of the die-down configuration of a bga package. to the end-use printed circuit board (pcb). while dca technology of- fers the ultimate in miniaturiza- tion, the infrastructure for it is not established enough for dca to be cost competitive. moreover, dca is not a viable option when the die has been designed for wirebonded interconnects (i.e., the bond pads are located around the periphery of the die), as is the case with all flash memories in traditional leaded packages. dca is better suited for die having the bond pads in an array across the die surface, en- abling the connections to be made with flip-chip technology instead of conventional wirebonding. figure 1 shows the smaller foot- print of a csp next to a comparable density tsop. the smaller form/fit factor saves considerable board space and provides a lower profile C all of which is needed when try- ing to cram more memory capacity onto ever smaller motherboards, or in products striving to fit into the palm of your hand. not just any csp will do in addressing the demand for a flash memory csp, amd first looked at the bga, since market acceptance of it was already es- tablished. amds lv800 flash family was initially offered in a bga, and we shipped modest quantities of it. but these early bga package designs included polyimide tape embedded with solid gold traces for routing the signals from the die to the exter- nal terminals, and this was too costly. so we had the polyimide tape replaced with a copper core tape that had gold-plated copper traces ("beam leads") instead of solid gold. this flash gold was bondable and kept oxidation from growing, and the copper brought the costs down. we ran into a roadblock, however, when our supplier was unable to produce the copper core tape in sufficient quantities. it was a roadblock that soon proved to be a blessing in disguise. faced with no reliable, cost- effective csp to offer flash cus- tomers, we turned to fijitsu, amd's fasl business partner. fijitsu had an FBGA with a polyimide tape substrate that looked promising, so we got per- mission to adopt their package technology. besides being cheaper than the bga, the FBGA con- struction was appealing because the package size could remain the same even if the die size became smaller. to better understand this, it helps to look at the configura- tion of an FBGA versus a bga. bga construction C one die size only please the bga package is not like a standard ic package in which you attach a die. it is a construction that is built on top of the die, so the package is nearly the same size as the die itself. the cross- section drawing in figure 2 shows the die-down configuration, in- terconnected by gold-plated beam leads to traces that route through the polyimide tape to an array of external solder balls. this package construction pre- sented a problem for amd be- cause of our die size. for many of the popular densities of the time, our die size was smaller than any other flash manufacturers. while this is good for keeping fab costs down (more die per wafer), our die size was too small to provide room for the size of the solder ball array while keeping the pitch (the distance between the centerlines of adjacent solder balls) at a manageable 0.75 mm for board assembly. moreover, even if our die could have fit ini- tially, every time we implemented a die shrink we would face the
FBGA user?s guide 76 version 4.2, november 1, 2002 msg figure 3 shows a cross-section of the die-up configuration of an FBGA package. same size problem. thus, with die shrinks occurring regularly, bgas are not an attractive csp solution for flash memories C either for us or for our customers C because the form/fit of the pack- age must change with every die shrink. this was becoming pain- fully apparent to several top-tier oems who were attempting to use the bga package for flash memories. FBGA construction C die shrink friendly in the FBGA construction, the die is wirebonded to a substrate and then overmolded with epoxy, a construction very much like that of a standard bga (see figure 3). the minimum package size winds up being about 1.2 times the size of the die, slightly larger than a com- parable density bga. but this size advantage wins no points when it comes to die shrinks. because of the FBGA construction, it can do what the bga cannot: accommo- date a reduction in die size with no change to the package dimen- sions. this renders a die shrink transparent mechanically to both amds and our customers manu- facturing lines C clearly, a win- win situation. building infrastructure for any new package technol- ogy, it is critical that there be a supporting industry infrastruc- ture. we already knew that in the flash market oems want: ? the smallest, most powerful flash memory they can get in a package that has the largest pitch; ? multiple supply sources; ? package designs that do not change with every die shrink. so we set our sights on qualify- ing the FBGA and on fortifying the infrastructure for it, the latter of which was no small task in a market where the bga was al- ready synonymous with csp. with no appreciable tooling or reliability data available at the time for the FBGA, we knew we needed to tackle these four pre- requisites to market acceptance: ? board level reliability; ? board level rework ability; ? socket suppliers; ? alternative supply sources. board level reliability we began testing the reliability of the FBGA after it was mounted onto a pcb similar to those in use by our major customers. we soon learned that the substrate of the FBGA C the polyimide tape C was too thin to absorb the stress in- curred from the different cte (co- efficient of thermal expansion) rates of the silicon versus the pcb (using fr4 material). when heated, the pcb expands at a much higher rate than the sili- con, and the package substrate has to manage this difference. although the polyimide substrate proved reliable enough for many applications, it did not meet the long-lifetime reliability that is needed in commercial and indus- trial outdoor applications, such as in the telecommunications infrastructure or automotive environments. tape vs rigid substrate while we were testing the tape FBGA, we also evaluated an FBGA design that had an organic sub- strate of bt (bismaleimide triaz- ine) resin. because this material was thicker and had a cte closer to that of the pcb, it could better manage the stress than could the thinner polyimide tape. so we switched. the results of the ex- tensive tests on the board level reliability performance can be found in the white paper, reli- ability evaluation of chip scale packages, published in 1999 by the following amders: ranjit gannamani, vis valluri, sidharth sidharth, and meilu zhang. a copy of this paper can be obtained from msd engineering (x26415). as for the bga, its board-level reliability performance is compa- rable to that of the FBGA due to the ability of its elastomer layer to absorb the stress from the different cte rates. these reliability
FBGA user?s guide version 4.2, november 1, 2002 77 msg results are also presented in the white paper referenced earlier. board level rework ability and socket suppliers nvd and msd engineers teamed up to familiarize board- level rework companies with the FBGA package. they also worked with socket suppliers, for those customers who do programming prior to system assembly, to ar- range support for amd's FBGA package. alternative supply sources nvd marketing contacted some of our competitors and showed them footprints and pinouts for our flash memory parts. after negotiating some pinout changes, nvd got their commitment to support both the bga and the FBGA pack-age styles for the same flash memo- ries. nvd also worked with the industry-wide jedec jc-42.4 committee to establish amds version of the FBGA pinout as an official industry standard. be- cause of this, all FBGA packaged flash memories manufactured in the world today conform to the amd footprint. we are continu- ing to work with jedec for the adoption of additional FBGA footprints designed to accommo- date future generations of very high-density, high-performance flash memories. the fruits of our labors this infrastructure work took about a year to come to fruition and, because of amds success in this effort, FBGAs are now the most preferred csp package for flash memories used in com- mercial and industrial applica- tions. bga shipments still outnumber FBGAs due to the top two or three cellular telephone oems using them in large quan- tities; however, the number of oems now choosing FBGAs for flash far exceeds those preferring the bga. with amd able to pro- duce flash memory roadmaps knowing what the package foot- print will look like years in the future, whether it be burst mode, page mode, or random access types of flash memory, even the oems committed to bga are now want- ing FBGAs for future designs. thanks go to the following amders for their valuable con- tributions to this article and for the instrumental roles they played in bringing the industry around to embracing the FBGA: bruce schupp, melissa lee, ranjit gannamani, vis valluri, and sidharth sidharth.
FBGA user?s guide 78 version 4.2, november 1, 2002 memo on j?t , case level thermal parameter 1 msd engineering memo on j-t , case level thermal parameter introduction a new thermal parameter has been developed by the eia/jedec jc15.1 subcommittee on thermal phenomenon in electronic packaging. the parameter is called j-t , (psi j-t) and is a modification and replacement of the much abused junction-to-case thermal resistance, jc , value for plastic packages. this memo outlines the history and physical description of jc measurements, and shows why they are poor performance indicators for plastic packages. the j-t parameter is introduced and its use is explained. history jc is a measurement that is used to describe the internal thermal resistance of a packaged semiconductor device. originally, the measurement was developed as a method of calculating junction temperature (t j ) from a known reference point on the outside of the package. the natural place for this reference point is defined as "the shortest thermal path from the junction to the outside of the package," which is also the best heat sinking surface. in the days when the specification was generated, the mainstream package was the ceramic dip, which for the military, were mounted onto 'cold rails'; flat liquid cooled tubes that contacted the bottoms of the dips in the application. these cold rails were held at a constant temperature and served as a reference point for calculating t j . the test method is performed by bringing the desired package surface to thermal equilibrium, an isothermal case condition at some defined temperature, by using a large cold plate or heat sink. the idea is to keep the external package temperature constant while the device is powered up. heating voltage and current are supplied to the device to power up the die while keeping the package surface at the initial defined temperature. when the device comes to steady-state temperature and power conditions, the junction temperature is measured and junction to case thermal resistance is calculated using equation (1). jc = t j -t r /p d (1) where: t j = junction temperature t r = reference temperature (case) p d = power dissipation heat flow in microelectronic packaging heat flow in a hermetic package is well defined as illustrated in figure 1. in the diagram it is seen that the die is attached to a ceramic substrate inside of a cavity. when the package is assembled, the cavity is left intact, that is, only air or some other gas comes in contact with the die surfaces not bonded to the cavity. since the thermal conductivity of the ceramic is
FBGA user?s guide version 4.2, november 1, 2002 79 2 quite high when compared to air or other gasses, most of the heat generated (~90%) from the circuitry on the die surface is conducted through the silicon and into the ceramic substrate. the heat travels through the ceramic and is dissipated into the air or into a heat sink. some spreading occurs in the ceramic (at an approximate 45 angle), so the analysis can be almost purely one-dimensional. this approach works well in any type of hermetic package including pgas, cqfps, cbgas, and other ceramic packages. die lid heat flow surface figure 1. heat flow in hermetic package when plastic packages gained popularity, much of the thermal analysis was left intact, such as the ja (junction-to-air thermal resistance) parameter, and jc . it was assumed, incorrectly, that the junction-to-case value could be used in plastic packages to predict junction temperature the same way it was used for hermetic packages. the problem with jc for plastic packages is fundamental, and it is easily seen how the physical construction of plastic packages negates the use of this simple parameter. figure 2 shows the typical construction and heat flow in a plastic quad flat pack (pqfp). heat flow paths are represented by a resistor network analogy in the diagram. as can be seen from the figure, heat flow in the plastic package is very complex when compared to the hermetic package. in plastic packages, the die is usually mounted onto a copper alloy die pad, wire bonded to the lead fingers which radially or orthogonally emanate from the die area, and is finally encapsulated in plastic moulding compound. because the die is contacted on all sides by solid matter, heat can flow easily in a multitude of directions. due to the copper alloy's high thermal conductivity, the heat immediately spreads into the die attach paddle, and subsequently into the lead frame. some heat also flows into the moulding compound and is released by convection from the package external surfaces. it is due to this complex heat flow that jc is ill defined for plastic packages. problematic jc for plastic first, the shortest thermal path is difficult to determine. if the package is thin, and the die paddle is close to the exterior of the package, this may be the shortest path. on the other hand, if the lead fingers are close to the die paddle, the most direct path may be through the lead frame and into the printed circuit board(pcb). the latter of these two possible paths
FBGA user?s guide 80 version 4.2, november 1, 2002 3 is more likely, but in any case, the external environment plays a crucial role in the thermal performance of plastic surface mount devices. as an example, if the pcb is relatively low in thermal conductivity, e.g. no internal planes and minimized metal traces on the surface, then the shortest path may well be through the bottom of the package. but, if the pcb has internal voltage and heat spreading planes, the leads may dominate the heat flow. secondly, how are these surfaces made to be isothermal as to satisfy the original intent of the ceramic based measurements? it was believed that using a well stirred fluid bath with a fluorinert liquid would force all surfaces on the plastic package to an isothermal state. due to the nature of stirred fluids, the measurement breaks down to a moving fluid measurement and the package surfaces are not isothermal. recently methods have been developed to use jet impingement to create high heat transfer coefficients on package surfaces, very nearly creating the isothermal specification. although these methods are useful for creating specific boundary conditions for conduction models, the measurement is still not useful for predicting junction temperature from a known package temperature. figure 2. heat flow in plastic packages customer use through the years, the real identity of jc was diluted, and today most system houses predict temperature by placing a thermocouple on the package surface and using the manufacturer's published jc values to compute junction temperature. this is a fallacy and is wholly inaccurate. today, it is an all too common practice and is accepted as correct. for hermetic packages, the correct method is to install a heat sink on the surface identified as the isothermal reference plane, and then use a thermocouple imbedded in the heat sink and touching the case to properly calculate junction temperature using jc . for plastic packages, there is no equivalent method. enter j-t during discussions with industry leading suppliers, it became obvious that the practices described above were in use regularly and without question. users of semiconductors had grown accustomed to placing the thermocouple and calculating the junction temperature without really understanding the implications of their actions. to counter this trend and
FBGA user?s guide version 4.2, november 1, 2002 81 4 provide a more meaningful method to predict junction temperature in plastic packaged devices, the parameter j-t was created. an excerpt from the eia/jesd51-2 standard follows describing the method and use of j-t . 4.0 thermal characterization parameter - jt junction-to-top cen ter of package the thermal characterization parameter, jt , is proportional to the temperature difference between the top center of the package and the junction temperature. hence, it is a useful value for an engineer verifying device temperatures in an actual environment. by measuring the package temperature of the device, the junction temperature can be estimated if the thermal characterization parameter has been measured unde r similar conditions. the use of jt should not be confused with jc which is the thermal resistance from the device junction to th e external surface of the package or case nearest the die attachment as the case is held at a constant temperature. the use and reporting of the case temperature during the junction to ambient thermal resistance test is optional. the measurement may be made using a temperature transducer such as a thermocouple, fluoroptic sensor, or infrared sensor. 4.1 thermocouple placement location the thermocouple bead shall be attached to the package at the geometric center of the top surface. the position must be reported, in all cases, along with the measurement data. 4.2 package thermocouple application caution: u sefulness of this measurement is dependent on the procedure. application of the thermocouple is critical to ensure proper thermal contact to the package and to ensure that the ja measurement is not disturbed. determination of the package surface temperature, of a low conductance package body, requires that the following factors be considered: 4.2.1 the thermocouple wire and bead shall touch the surface of the package. 4.2.2 best practice for attaching the wire and thermocouple bead is the use of a minimal amount of thermally conducting epoxy. the distance across the epoxy bead shall not exceed .1? (2.54 mm) in any direction. 4.2.3 the thermocouple wire shall be routed next to the package body down to the board and along the board. this reduces cooling of the thermocouple junction by heat flowing along the wire. 4.2.4 thermocouple wire size shall be small such that heat loss along the wire does not cause anomalous low readings. recommended maximum thermocouple sizes is 36 gauge. for type t thermocouples, 40 gauge is preferred. 4.3 procedure the junction temperature and package temperatures are determined at the steady-state condition in the jt , is calculated using the following equation:
FBGA user?s guide 82 version 4.2, november 1, 2002 5 jt = (t jss - t tss )/p h (4) where jt = thermal characterization parameter from device junction to the top center of the package surface( c/w) t jss = the junction temperature at steady-state. t tss = the package (top surface) temperature, at steady-state, measured by the thermocouple, infrared sensor, or fluoroptic sensor. the relationship between the junction-to-ambient thermal resistance, ja , and the junction-to-top center of package thermal characterization parameter, jt , is described by equation 5: ja = jt + ta (5) where ta = thermal characterization parameter from top surface of the package-to-air ( c/w) the package-to-air thermal characterization parameter, ta , is based on the steady-state ambient air temperature as shown here: ta = (t tss - t ass )/p h (6) the thermal characterization parameters, jt and ta , have the units c/w but are mathematical constructs rather than thermal resistances because not all of the heating power flows through the exposed case surface. it is not necessary to report ta because it can be determined from the relationship between ja and jt . also, ta is very dependent on the application-specific environment. conclusion this memo has attempted to educate and inform package, process, and product engineers in the correct use of temperature measurements on the external surface of the package to determine junction temperature. if we educate our customers, system level thermal analysis will be more accurate, allowing a larger application range for our products, especially in critical situations. because the measurement is relatively new, we are in the process of generating j-t values for all amd surface mount plastic packages. if a value is needed for a particular product, please contact the package characterization group in msd engineering. references 1. "methodology for the thermal measurement of component packages (single semiconductor device), eia/ jesd51 standard, electronic industries association, 1995 2. "integrated circuit thermal measurement method - electrical test method (single semiconductor device), eia/jesd 51-1 standard, electronic industries association, 1995 3. "integrated circuit thermal test method environmenatl conditions - natural convection (still air), eia/jesd 51-2 standard, electronic industries association, 1995 4. "low effective thermal conductivity test board for leaded surface mount packages," eia/jesd 51-3 standard, electronic industries association, 1996 5. "thermal test chip guideline (wire bond type chip)," eia/jesd 51-4 standard, electronic industries association, 1996 6. ? extension of thermal test board standards for packages with direct attach mechanisims? , eia/jesd 51-5, electronic industries association, 1999
FBGA user?s guide version 4.2, november 1, 2002 83 6 7. ? integrated circuit thermal test method environmental conditions ? forced convection (moving air), eia/jesd 51-6, electronic industries association, 1999 8. ? high effective thermal conductivity test board for leaded surface mount packages? , eia/jesd 51-7, electronic industries association, 1999 9. "accepted practices for making microelectronic device thermal characteristics tests - a user's guide," jedec engineering bulletin no. 20, electronic industries association, washington, dc. 10. "thermal characteristics," method 1012.1, mil-std-883c test methods and procedures for microelectronics, department of defense, washington, dc. 11. "unencapsulated thermal test chip," semi g32-86 guideline, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca. 12. "junction-to-case thermal resistance measurements of molded-plastic packages," semi g43-87 test method, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca. 13. "thermal test board standardization for measuring junction-to-ambient thermal resistance of semiconductor packages," semi g42-88 specification, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca. 14. ? junction-to-case thermal resistance measurements of ceramic packages," semi g30-88 test method, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca. 15. "thermal transient testing for die attachment evaluation of integrated circuits," semi g46-88 test method, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca. 16. "still-and forced-air junction-to-ambient thermal resistance measurements of integrated circuit packages," semi g38-87 test method, 1989 book of semi standards, vol. 4, packaging division, semi, inc. mountain view, ca.
FBGA user?s guide 84 version 4.2, november 1, 2002
FBGA user?s guide version 4.2, november 1, 2002 85 appendix b: application note the following information is excerpted from a published amd application note, number 22142.
publication# 22142 rev: a amendment/ +2 issue date: april 15, 2002 daisy chain samples application note daisy chain samples are non-functional parts with a pattern of inter-connected balls. these samples are typically assembled onto a printed circuit board (pcb) with matching patterns. once assembled on the match- ing pcb, all balls are connected creating a continuous network. refer to figure 1. notes: 1. ?_____? solid traces are daisy chain patterns on the FBGA package. 2. ?- - - - -? dash traces are daisy chain patterns on the pcb. 3. ?a?, ?b? are the input and output of the network for the device. 4. ?c?, ?d? are the input and output of a separate network for the support balls. figure 1. FBGA 32 mb and 64 mb silicon daisy chain with matching pcb schematic (top view) daisy chain samples are primarily requested by oems to perform assembly evaluations. prior to production, an oem will generally solder daisy chain samples on to a daisy chain pcb and perform open/short testing to check for misalignments. this test will help an oem characterize its assembly process and equipment prior to full production. daisy chains are also used in second level solder- joint board reliability studies. the daisy chain sam- ples are assembled onto the matching pcb and sub- jected to temperature cycling in an oven. board level reliability tests are tools to help predict and measure the expected life of packages. for more in depth infor- mation on second level solder-joint board reliability,
b - 87 FBGA user?s guide please refer to ?reliability evaluation of chip scale packages? by ranjit gannamani, viswanath valluri, sidharth, and meilu zhang. currently amd has three types of FBGA daisy chains: stitched daisy chains, metal mask daisy chains and substrate daisy chains. since the main purpose is to characterize assembly process and equipment, oems typically have no preference on the type of daisy chain used. descriptions stitched daisy chains the functional substrate is used with a dummy silicon slug. daisy chain patterns are produced by shorting pairs of adjacent bond-fingers on the substrate via wire bonding. there are no wire bonds from the dummy sil- icon slug to the substrate. metal mask daisy chains the functional substrate is used with a special daisy chained wafer. there is no active circuitry on the wafer, only the simulated bond-pads. adjacent bond-pads are shorted via metal mask. daisy chain patterns are pro- duced by wire bonding the bond-fingers on the sub- strate to the bond-pads on the wafer. substrate daisy chains a dummy silicon slug is used with a special daisy chained substrate. shorting adjacent balls on the sub- strate produces daisy chain patterns. 9 x 8 mm fine pitch-bga (wc) daisy chain schematic note: a and b are input and output of the network. 12 x 6 mm 48-ball fine pitch-bga daisy chain schematic note: a and b are input and output of the network. abcdefgh 6 5 4 3 2 1 abcdefgh a b 6 5 4 3 2 1 package connection (bottom view) board connection (top view) abcdef gh 1 2 3 4 5 6 package connection (bottom view) board connection (top view) a b cdef gh a b 1 2 3 4 5 6
FBGA user?s guide 88 version 4.2, november 1, 2002 12 x 11 mm 63-ball fine pitch-bga daisy chain schematic ? note: a and b are input and output of the network. c and d are input and output of a separate network for support balls. 13 x 11 mm 64-ball fortified-bga daisy chain schematic note: a and b are input and output of the network. package connection (bottom view) board connection (top view) abcdefghj klm 1 2 3 4 5 7 6 8 abcde fghj klm 1 2 3 4 5 7 6 8 a c b d ab cde fgh 1 2 3 4 5 6 7 8 a b board connection (top view) ab cde fgh 1 2 3 4 5 6 7 8 a b board connection (top view) ab cde fgh 1 2 3 4 5 6 7 8 package connection (top view) ab cde fgh 1 2 3 4 5 6 7 8 package connection (top view) ab cde fgh 1 2 3 4 5 6 7 8 package connection (top view)
FBGA user?s guide version 4.2, november 1, 2002 89 13 x 11 mm 80-ball fortified-bga daisy chain schematic note: a and b are input and output of the network. 1 2 3 4 5 6 7 8 a bc defgh j k package connection (top view) 1 2 3 4 5 6 7 8 a bc defgh j k 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 a bc defgh j k a bc defgh j k package connection (top view)
FBGA user?s guide 90 version 4.2, november 1, 2002 ordering information amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: to place an order, please contact your local amd sales representative. for a current list of contacts via the internet go to http://www.amd.com/support/sales.html am29lv160d wc d 2 2 b substrate type a = top or internal/intermediate layers shorted on the substrate b = bottom layer shorted on the substrate c = wirebond daisy chain connection 1 = daisy chain connection is on the die (metal mask) 2 = daisy chain connection is on the substrate solder mask opening and ground plane 1 = no ground plane 2 = 0.25 mm solder mask opening 3 = 0.27 mm solder mask opening 5 = 0.50 mm solder mask opening 6 = 0.55 mm solder mask opening daisy chain package types pb = 80-ball fortified ball grid array ( f bga) 1.00 mm pitch, 13 x 11 mm package pc = 64-ball fortified ball grid array ( f bga) 1.00 mm pitch, 13 x 11 mm package wc = 48-ball fine pitch ball grid array (FBGA) 0.80 mm pitch, 9 x 8 mm package wh = 63-ball fine pitch ball grid array (FBGA) 0.80 mm pitch, 12 x 11 mm package wm = 48-ball fine pitch ball grid array (FBGA) 0.80 mm pitch, 12 x 6 mm package device number/description valid combinations for bga daisy chain density package order number package marking 16 mb 9 x 8 fine pitch bga (wc) 13 x 11 mm fortified bga (pb) am29lv160dwcd22b am29bdd160gpbd62b lv160dd22b bdafgd62b 32 mb 12 x 6 mm FBGA (wm) am29dl323dwmd22b dl323dd22b 64 mb 12 x 11 fine pitch bga (wh) 13 x 11 mm fortified bga (pc) am29dl640dwhd22b am29lv640dpcd62b dl640dd22b lcedd62b
FBGA user?s guide version 4.2, november 1, 2002 91 revision summary revision e (version 2.2): march 13, 1999 chapter 2 modified 32 and 64 mb daisy chain and board layout drawings. 32 and 64 mb pinout drawings now show outrigger balls that are shorted. revision f (version 2.3): may 17, 1999 construction of the FBGA-bt figure revised the following callouts: mold compound (del eted ?multi-functional?), die attach (deleted ?non-conductive?), solder mask (deleted ?50 nom?), copper foil (deleted ?12?), plating (deleted thickness from cu and au). FBGA package materials descriptions in the table, renamed the following parameters: rigid substrate; molding compound; die attach material. deleted ?interposer? from copper metallization. FBGA ball attach detail clarified type of attach. component level testing, FBGA-bt changed jc-14.1-98-135, level 2 qualifications is planned for q2, 1999 to jcb-98-104. in the table, added rows 4 through 6. in item 3, changed ramp-up rate to 3 c, time at max. temperature to 10?20 seconds. FBGA-bt component level test results replaced and reformatted data in table. test strategy deleted reference to data supplied to amd weekly. FBGA package marking added ?d? technology designator. revised explanatory table. FBGA package dimensions renamed we and wf designators to wg and wh, respectively.
FBGA user?s guide 92 version 4.2, november 1, 2002 revision f+1 (version 2.3.1): july 30, 1999 chapter 2 16 mb daisy chain and board layout figures. added new 99xx date code daisy chain schematic and board layout. added 98xx date code to previous drawings. revision g (version 3.0): january 15, 2001 chapter 2 replaced all fgba pinout figures with new illustrations. chapter 3 updated package outline diagrams with specification 16-038-9 illustrations. replaced table 3-1 FBGA-bt with new information. section on ?FBGA thermal resistance data? replaced with section on ?FBGA thermal management?. chapter 4 added hdi information in the ?general design considerations? section. replaced ?routing dimensions? section with ?routing recommendation? section. added ?gold thickness of 5 mils max is recommended? to the ?pc board surface finish? subsection. updated ?recommended design values? in the table below figure 4-2. replaced ?routing dimensions? and ?routing for 32-megabit? figure with ?example of routing? figures. chapter 5 replaced entire chapter with new information. appendix a new article reprints. appendix b new application note. revision g+1 (version 3.1): march 12, 2001 chapter 2?daisy chains added ? both are listed in the appendices.? to the end of the second paragraph.
FBGA user?s guide version 4.2, november 1, 2002 93 chapter 3?FBGA thermal management added ?t ass = temperature of ambient air at steady state? to the ? ja ? junction to air? equations table 3-2. thermal resistance data: changed table headings ? jc (c/w)? to ? jma (c/w)? and ? jma (c/w)? to ? j?t (c/w). shifted down the values in the jma (c/w) table column. moved data of the fgc048 j?t (c/w) table cell to the fgc048 jma (c/w) location. added the following table notes: ?4. jma = theta of junction to moving air.? and ?5 . spd (lfpm) = speed of moving air, in terms of ?linear feet per minute?.? corrected the fbd063 ja (c/w) data. revision h (version 4.0): january 24, 2002 chapters 1?4 chapters were completely rewritten. it is recommended that users of previous editions read through these chapters to familiarize themselves with the revised content. chapter 5 new daisy chain schematics and board layouts have been added. the first two figures from the previous user?s guide have been deleted. revision i (version 4.1): april 12, 2002 chapter 2 figure 2-3: added am29pds322d to list of devices in 8 x 9 mm package. figure 2-7: corrected 4gb to 128 mb. chapter 5 corrected figure 5-7 from 80 to 84 ball; figure 5-8 from 64 to 84 ball, figure 5-10 from 80 to 64 ball. chapter 6 table 6.1: corrected units of measure in thickness column from mm to m. deleted e-05 from specifications in cte ppm/c column. added descriptions for fla069, flb073, laa064, laa080, lab 080, and lba176 chapter 7 recommended board desin dimensions: modified table to show both 0.30 and 0.60 mm balls.
FBGA user?s guide 94 version 4.2, november 1, 2002 chapter 10 FBGA package designators: added 6 x 12, 11 x 13 , and 10 x 15 mm sizes. appendix b updated information from october 25, 2001 revision of application note. revision j (version 4.2): november 1, 2002 chapter 7 modified table to include values for 0.35 mm solder balls. changed tolerances on dimension a for 0.30 and 0.60 solder balls. changed dimension c for 0.30 solder balls.
FBGA user?s guide version 4.2, november 1, 2002 95
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