View W149H_2693840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

440bx agpset spread spectrum frequency synthesizer w149 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 november 16, 2000, rev. *b features ? maximized emi suppression using cypress?s spread spectrum technology single chip system frequency synthesizer for intel ? 440bx agpset two copies of cpu output six copies of pci output one 48-mhz output for usb one 24-mhz output for sio two buffered reference outputs one ioapic output thirteen sdram outputs provide support for 3 dimms spread spectrum feature always enabled smbus interface for programming power management control inputs smooth cpu frequency switching from 66.8?124 mhz key specifications cpu cycle-to-cycle jitter: ......................................... 250 ps cpu to cpu output skew: ........................................ 175 ps pci to pci output skew: ............................................ 500 ps v ddq3 : ..................................................................... 3.3v5% v ddq2 : ..................................................................... 2.5v5% sdramin to sdram0:12 delay:.......................... 3.7 ns typ. table 1. mode input table [1] mode pin 2 0 pci_stop# 1 ref0 table 2. pin selectable frequency input address cpu0:1 (mhz) pci_f, 1:5 (mhz) spread % fs2 fs1 fs0 1 1 1 100 33.3 (cpu/3) ?0.5 1 1 0 (reserved) 1 0 1 100 33.3 (cpu/3) 0.5 1 0 0 103 34.3 (cpu/3) ?0.5 0 1 1 66.8 33.4 (cpu/2) ?0.5 0 1 0 83.3 41.7 (cpu/2) ?0.5 0 0 1 66.8 33.4 (cpu/2) 0.5 0 0 0 124 41.3 (cpu/3) ?0.5 intel is a registered trademark of intel corporation. notes: 1. mode input latched at power-up. 2. internal pull up resistors(*) should not be relied upon for setting i/o pins high. pin function with parentheses determined b y mode pin resistor strapping. logic block diagram pin configuration [2] vddq3 ref0/(pci_stop#) vddq2 cpu0 pci_f/mode xtal pll ref freq pll 1 x2 x1 ref1/fs2 vddq3 stop clock control pci2 pci3 pci4 48mhz/fs0 24mhz/fs1 pll2 2/3 osc vddq2 vddq3 ioapic pci5 smbus sdata logic sclk i/o pin control sdram0:12 sdramin 13 vddq3 pci1 cpu1 2 vddq3 ref0/(pci_stop#) gnd x1 x2 vddq3 pci_f/mode pci1 gnd pci2 pci3 pci4 pci5 vddq3 sdramin gnd sdram11 sdram10 vddq3 sdram9 sdram8 gnd sdata sclk w149 vddq2 ioapic ref1/fs2* gnd cpu0 cpu1 vddq2 oe sdram12 gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4 sdram5 vddq3 sdram6 sdram7 vddq3 48mhz/fs0* 24mhz/fs1* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 smbus {
w149 2 pin definitions pin name pin no. pin type pin description cpu0:1 44, 43 o cpu clock outputs: see ta b l e s 2 and 6 for detailed frequency information. output voltage swing is controlled by voltage applied to vddq2. pci1:5 8, 10, 11, 12, 13 o pci clock outputs 1 through 5: these five pci clock outputs are controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. pci_f/mode 7 i/o fixed pci clock output: frequency is set by the fs0:1 inputs or through serial input interface, see tables 2 and 6 . this output is not affected by the pci_stop# input. upon power-up the mode input w ill be latc hed, which will determine the func- tion of pin 2, ref0/(pci_stop#). see table 1 . oe 41 i output enable input: when brought low, all outputs are placed in a high-imped- ance state. when brought high, all clock outputs activate. ioapic 47 o ioapic clock output: provides 14.318-mhz fixed frequency. the output voltage swing is controlled by vddq2. 48mhz/fs0 26 i/o 48-mhz output: 48 mhz is provided in normal operation. in standard systems, this output can be used as the reference for the universal serial bus. upon power-up, fs0 input will be latched, which will set clock frequencies as described in table 2 . this output does not have the spread spectrum feature. 24mhz/fs1 25 i/o 24-mhz output: 24 mhz is provided in normal operation. in standard systems, this output can be used as the clock input for a super i/o chip. upon power-up fs1 input will be latched, which will set clock frequencies as described in ta b l e 2 . this output does not have the spread spectrum feature. ref1/fs2 46 i/o i/o dual-function ref1 and fs2 pin: upon power-up, fs2 input will be latched which will set clock frequencies as described in ta b l e 2 . when an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the x1/x2 pins. ref0/ (pci_stop#) 2i/o fixed 14.318-mhz output 0 or pci_stop# pin: function is determined by the mode input. when set as an input, the pci_stop# input enables the pci 1:5 outputs when high and causes them to remain at logic 0 when low. the pci_stop signal is latched on the rising edge of pci_f. its effects take place on the next pci_f clock cycle. when an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the x1/x2 pins. sdramin 15 i buffered input pin: the signal provided to this input pin is buffered to 13 outputs (sdram0:12). sdram0:12 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 o buffered outputs: these thirteen dedicated outputs provide copies of the signal provided at the sdramin input. the swing is set by vddq3, and they are deacti- vated when clk_stop# input is set low. sclk 24 i clock pin for smbus circuitry. sdata 23 i/o data pin for smbus circuitry. x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 5 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. vddq3 1, 6, 14, 19, 27, 30, 36 p power connection: power supply for core logic, pll circuitry, sdram outputs, pci outputs, reference outputs, 48-mhz output, and 24-mhz output. connect to 3.3v supply. vddq2 42, 48 p power connection: power supply for ioapic and cpu0:1 output buffers. connect to 2.5v, or 3.3v. gnd 3, 9, 16, 22, 33, 39, 45 g ground connections: connect all ground pins to the common system ground plane.
w149 3 overview the w149 was developed as a single chip device to meet the clocking needs of the intel 440bx agpset. in addition to the typical outputs provided by standard 100-mhz 440bx agpset ftgs, the w149 adds a thirteen output buffer, supporting sdram dimm modules in conjunction with the chipset. cypress proprietary spread spectrum frequency synthesis technique is a feature of the cpu and pci outputs. this feature reduces the peak emi measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. functional description i/o pin operation pins 7, 25, 26, 46 are dual-purpose l/o pins. upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. a short time after power-up, the logic state of each pin is latched and the pins become clock outputs. this feature reduces device pin count by combining clock outputs with input select pins. an external 10-k ? ? strapping ? resistor is connected between the l/o pin and ground or v dd . connection to ground sets a latch to ? 0 ? , connection to v dd sets a latch to ? 1 ? . figure 1 and figure 2 show two suggested methods for strapping resistor connections. upon w149 power-up, the first 2 ms of operation is used for input logic selection. during this period, the four i/o pins (7, 25, 26, 46) are three-stated, allowing the output strapping re- sistor on the l/o pins to pull each pin and its associated capac- itive clock load to either a logic high or low state. at the end of the 2-ms period, the established logic ? 0 ? or ? 1 ? condition of the l/o pin is latched. next the output buffer is enabled, con- verting the l/o pins into operating clock outputs. the 2-ms tim- er starts when v dd reaches 2.0v. the input bits can only be reset by turning v dd off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of clock output is <40 ? (nominal), which is minimally af- fected by the 10-k ? strap to ground or v dd . as with the series termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v dd should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that v dd has stabilized. if v dd has not yet reached full value, output frequency initially may be below target but will increase to target once v dd voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. power-on reset timer output three-state data latch hold qd w149 v dd clock load 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option power-on reset timer output three-state data latch hold qd w149 v dd clock load r 10 k ? output buffer output low output strapping resistor series termination resistor jumper options resistor value r figure 2. input logic selection through jumper option
w149 4 spread spectrum clocking the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 3 . as shown in figure 3 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log10(p) + 9*log10(f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 4 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is either ? 0.5% or 0.5% of the selected frequency. figure 4 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking cannot be deactivated on the w149. figure 3. clock harmonic with and without sscg modulation frequency domain representation ssftg typical clock frequency span (mhz) amplitude (db) center spread max (+0.5%) min ( ? 0.5%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 4. typical modulation profile
w149 5 serial data interface the w149 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. upon power-up, the w149 initializes with default register settings, therefore the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applications, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power manage- ment functions. ta b l e 3 summarizes the control functions of the serial data interface. operation data is written to the w149 in eleven bytes of eight bits each. bytes are written in the order shown in ta b l e 4 . table 3. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock outputs to unused pci slots. cpu clock frequency selection provides cpu/pci frequency selections through software. frequency is changed in a smooth and controlled fashion. for alternate microprocessors and power management options. smooth frequency transition allows cpu frequency change under normal system operation. output three-state puts clock output into a high-impedance state. production pcb testing. (reserved) reserved function for future device revision or production device testing. no user application. register bit must be written as 0. table 4. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the w149 to accept the bits in data bytes 0 ? 6 for internal register configuration. since other devices may exist on the same com- mon serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the w149 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the w149, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writing to anoth- er addressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the w149, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communication protocol and may be used when writing to anoth- er addressed slave receiver on the serial data bus. 4 data byte 0 refer to ta b l e 5 the data bits in data bytes 0 ? 7 set internal w149 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 5 , data byte serial configuration map. 5 data byte 1 6 data byte 2 7 data byte 3 8 data byte 4 9 data byte 5 10 data byte 6 11 data byte 7
w149 6 writing data bytes each bit in data bytes 0 ? 7 control a particular device function except for the ? reserved ? bits which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 5 gives the bit formats for registers located in data bytes 0 ? 7. ta b l e 6 details additional frequency selections that are avail- able through the serial data interface. ta b l e 7 details the select functions for byte 0, bits 1 and 0. table 5. data bytes 0 ? 7 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 0 7-- --don ? t care -- -- 0 6 -- -- sel_2 see ta bl e 6 0 5 -- -- sel_1 see ta bl e 6 0 4 -- -- sel_0 see ta bl e 6 0 3 -- -- hardware/software frequency select hardware software 0 2-- --don ? t care -- -- 0 1 ? 0-- -- bit 1 bit 0 function (see ta b l e 7 for function details) 0 0 normal operation 0 1 (reserved) 1 0 normal operation 1 1 all outputs three-stated 00 data byte 1 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 40 sdram12 clock output disable low active 1 2 -- -- (reserved) -- -- 0 1 43 cpu1 clock output disable low active 1 0 44 cpu0 clock output disable low active 1 data byte 2 7 -- -- (reserved) -- -- 0 6 7 pci_f clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 13 pci5 clock output disable low active 1 3 12 pci4 clock output disable low active 1 2 11 pci3 clock output disable low active 1 1 10 pci2 clock output disable low active 1 0 8 pci1 clock output disable low active 1 data byte 3 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 26 48mhz clock output disable low active 1 4 25 24mhz clock output disable low active 1 3 -- -- (reserved) -- -- 0 2 21, 20, 18, 17 sdram8:11 clock output disable low active 1
w149 7 1 32, 31, 29, 28 sdram4:7 clock output disable low active 1 0 38, 37, 35, 34 sdram0:3 clock output disable low active 1 data byte 4 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 5 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 47 ioapic clock output disable low active 1 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 46 ref1 clock output disable low active 1 0 2 ref0 clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 7 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 table 5. data bytes 0 ? 7 serial configuration map (continued) bit(s) affected pin control function bit control default pin no. pin name 0 1
w149 8 table 6. additional frequency selections through serial data interface data bytes [3] input conditions output frequency spread % data byte 0, bit 3 = 1 cpu0:1, sdram0:12 (mhz) pci_f, 1:5 (mhz) bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 1 1 1 100. 2 33.4 ? 0.5 1 1 0 (reserved) (reserved) (reserved) 1 0 1 100 33.3 0.5 1 0 0 103 34.3 ? 0.5 0 1 1 66.8 33.4 ? 0.5 0 1 0 83.3 41.65 ? 0.5 0 0 1 66.8 33.4 0.5 0 0 0 124 41.3 ? 0.5 table 7. select function for data byte 0, bits 0:1 function input conditions output conditions data byte 0 cpu0:1 pci_f, pci1:5 ref0:1, ioapic 48 mhz 24 mhz bit 1 bit 0 normal operation x 0 note 1 note 1 14.318 mhz 48 mhz 24 mhz three-state 1 1 hi-z hi-z hi-z hi-z hi-z note: 3. cpu and pci frequency selections are listed in ta bl e 2 and table 6 .
w149 9 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min) kv dc electrical characteristics: t a = 0 c to +70 c; v ddq3 = 3.3v5%; v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit supply current i dd 3.3v supply current cpu0:1 = 100 mhz outputs loaded [4] 260 ma i dd 2.5v supply current cpu0:1 = 100 mhz outputs loaded [4] 25 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [5] ? 25 a i ih input high current [5] 10 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = 1 ma 3.1 v v oh output high voltage cpu0:1, ioapic i oh = ? 1 ma 2.2 v i ol output low current cpu0:1 v ol = 1.25v 27 57 97 ma pci_f, pci1:5 v ol = 1.5v 20.5 53 139 ma ioapic v ol = 1.25v 40 85 140 ma ref0:1 v ol = 1.5v 25 37 76 ma 48mhz v ol = 1.5v 25 37 76 ma 24mhz v ol = 1.5v 25 37 76 ma i oh output high current cpu0:1 v oh = 1.25v 25 55 97 ma i oh output high current pci_f, pci1:5 v oh = 1.5v 31 55 139 ma ioapic v oh = 1.25v 40 87 155 ma ref0:1 v oh = 1.5v 27 44 94 ma 48mhz v oh = 1.5v 27 44 94 ma 24mhz v oh = 1.5v 25 37 76 ma notes: 4. all clock outputs loaded with 6" 60 ? traces with 22-pf capacitors. 5. w149 logic inputs have internal pull-up devices (pull-ups not full cmos level).
w149 10 crystal oscillator v th x1 input threshold voltage [6] v ddq3 = 3.3v 1.65 v c load load capacitance, imposed on external crystal [7] 14 pf c in,x1 x1 input capacitance [8] pin x2 unconnected 28 pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh notes: 6. x1 input threshold voltage (typical) is v ddq3 /2. 7. the w149 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total l oad placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 8. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected). dc electrical characteristics: (continued) t a = 0 c to +70 c; v ddq3 = 3.3v5%; v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit
w149 11 ac electrical characteristics t a = 0 c to +70 c; v ddq3 = 3.3v5%; v ddq2 = 2.5v5%; f xtl = 14.31818 mhz ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum clocking is disabled. cpu clock outputs, cpu_f, cpu1 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 15 15.5 10 10.5 ns t h high time duration of clock cycle above 2.4v, at min. edge rate (1.5 v/ns) 5.6 3.3 ns t l low time duration of clock cycle below 0.4v, at min. edge rate (1.5 v/ns) 5.3 3.1 ns t r output rise edge rate measured from 0.4v to 2.4v 1.5 4 1.5 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.5 4 1.5 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v, at min. edge rate (1.5 v/ns) 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. max- imum difference of cycle time between two adjacent cycles. 250 250 ps t sk output skew measured on rising edge at 1.5v 175 175 ps f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transi- tion. used for determining series termi- nation value. 20 20 ?
w149 12 sdram clock outputs, sdram, sdram0:11 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 66.6 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.5v 30 30 ns t h high time duration of clock cycle above 2.4v, at min. sdge rate (1.5 v/ns) 5.6 3.3 ns t l low time duration of clock cycle below 0.4v, at min. sdge rate (1.5 v/ns) 5.3 3.1 ns t r output rise edge rate measured from 0.4v to 2.4v 1.5 4 1.5 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.5 4 1.5 4 v/ns t plh prop delay lh input edge rate faster than 1 v/ns 1 5 1 5 ns t phl prop delay hl input edge rate faster than 1 v/ns 1 5 1 5 ns t d duty cycle measured on rising and falling edge at 1.5v, at min. sdge rate (1.5 v/ns) 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 250 ps t sk output skew measured on rising edge at 1.5v 250 250 ps t o cpu to pci clock skew covers all cpu/pci outputs. mea- sured on rising edge at 1.5v. cpu leads pci output. 1.5 4 1.5 4 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 30 ?
w149 13 pci clock outputs, pci_f and pci1:5 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns t h high time duration of clock cycle above 2.4v 12.0 ns t l low time duration of clock cycle below 0.4v 12.0 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adja- cent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 500 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 1.5 4 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist pri- or to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 ? ioapic clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate measured from 0.4v to 2.0v 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref0:1 clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v. 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabili- zation. 3ms z o ac output impedance average value during switching transition. used for de- termining series termination value. 40 ?
w149 14 document #: 38-00856-b 48-mhz clock output (lump capacitance test load = 20 pf= 66.6/100 mhz parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabili- zation. 3ms z o ac output impedance average value during switching transition. used for de- termining series termination value. 40 ? 24-mhz clock output (lump capacitance test load = 20 pf= 66.6/100 mhz parameter description test condition/comments cpu = 66.6/100 mhz unit min. typ. max. f frequency, actual determined by pll divider ratio (see m/n below) 24.004 mhz f d deviation from 24 mhz (24.004 ? 24)/24 +167 ppm m/n pll ratio (14.31818 mhz x 57/34 = 24.004 mhz) 57/34 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabili- zation. 3ms z o ac output impedance average value during switching transition. used for de- termining series termination value. 40 ? ordering information ordering code package name package type w149 h 48-pin ssop (300-mil)
w149 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102 48-pin shrink small outline package (ssop, 300 mils)

▲Up To Search▲

Price & Availability of W149H

	To Download W149H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .