View MT36JCZS1G72PY-1G0XX_3760418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm features pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 1 ?2008 micron technology, inc. all rights reserved. ddr3 sdram rdimm mt36jczs1g72p ? 8gb for component data sheets, refer to micron?s web site: www.micron.com features ? ddr3 functionality and operations supported as defined in the component data sheet ? 240-pin, registered dual in-line memory module (rdimm) ? fast data transfer rates: pc3-8500 or pc3-6400 ? 8gb (1 gig x 72) ? full module heat spreader ? vdd = 1.5v 0.075v ? vddspd = +3.0v to +3.6v ? supports ecc error detection and correction ? nominal and dynamic on-die termination (odt) for data and strobe signals ? dual rank, using 4gb twindie ? devices ?on board i 2 c temperature sensor with integrated serial presence-detect (spd) eeprom ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? selectable bc4 or bl8 on-the-fly (otf) ? gold edge contacts ?lead-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin low-profile rdimm notes: 1. contact micron for industrial temperature module offerings. 2. not recommended for new designs. options marking ? operating temperature 1 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 240-pin dimm (lead-free) y ? frequency/cas latency ? 1.87ns @ cl = 7 (ddr3-1066) -1g1 ? 1.87ns @ cl = 8 (ddr3-1066) 2 -1g0 ? 2.5ns @ cl = 5 (ddr3-800) 2 -80c ? 2.5ns @ cl = 6 (ddr3-800) 2 -80b pcb height: 19.5mm (0.768in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 8 cl = 7 cl = 6 cl = 5 -1g1 pc3-8500 1066 1066 800 ? 13.125 13.125 50.625 -1g0 pc3-8500 1066 ? 800 ? 15 15 52.5 -80c pc3-6400 ? ? 800 800 12.5 12.5 50 -80b pc3-6400 ? ? 800 ? 15 15 52.5
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 2 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm features notes: 1. the data sheet for the base devi ce can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for curre nt revision codes. example: mt36jczs1g72py-1g1d1 . table 2: addressing parameter 8gb refresh count 8k row address 32k a[14:0] device bank address 8 ba[2:0] device configuration 4gb twindie (1 gig x 4) column address 2k a[11, 9:0] module rank address 2 s#[1:0] table 3: part numbers and timing parameters ? 8gb modules base device: mt41j1g4thu, 1 4gb twindie ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36jczs1g72p(i)y-1g1__ 8gb 1 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 mt36jczs1g72p(i)y-1g0__ 8gb 1 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 8-8-8 mt36jczs1g72p(i)y-80c__ 8gb 1 gig x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt36jczs1g72p(i)y-80b__ 8gb 1 gig x 72 6.4 gb/s 2.5ns/800 mt/s 6-6-6
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 3 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm pin assignments and descriptions pin assignments and descriptions table 4: pin assignments 240-pin ddr3 rdimm front 240-pin ddr3 rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vrefdq 31 dq25 61 a2 91 dq41 121 vss 151 vss 181 a1 211 vss 2 vss 32 vss 62 vdd 92 vss 122 dq4 152 dqs12 182 vdd 212 dqs14 3 dq0 33 dqs3# 63 nf 93 dqs5# 123 dq5 153 dqs12# 183 vdd 213 dqs14# 4 dq1 34 dqs3 64 nf 94 dqs5 124 vss 154 vss 184 ck0 214 vss 5 vss 35 vss 65 vdd 95 vss 125 dqs9 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 vdd 96 dq42 126 dqs9# 156 dq31 186 vdd 216 dq47 7 dqs0 37 dq27 67 vrefca 97 dq43 127 vss 157 vss 187 event# 217 vss 8 vss 38 vss 68 par_in 98 vss 128 dq6 158 cb4 188 a0 218 dq52 9 dq2 39 cb0 69 vdd 99 dq48 129 dq7 159 cb5 189 vdd 219 dq53 10 dq3 40 cb1 70 a10 100 dq49 130 vss 160 vss 190 ba1 220 vss 11 vss 41 vss 71 ba0 101 vss 131 dq12 161 dqs17 191 vdd 221 dqs15 12 dq8 42 dqs8# 72 vdd 102 dqs6# 132 dq13 162 dqs17# 192 ras# 222 dqs15# 13 dq9 43 dqs8 73 we# 103 dqs6 133 vss 163 vss 193 s0# 223 vss 14 vss 44 vss 74 cas# 104 vss 134 dqs10 164 cb6 194 vdd 224 dq54 15 dqs1# 45 cb2 75 vdd 105 dq50 135 dqs10# 165 cb7 195 odt0 225 dq55 16 dqs1 46 cb3 76 s1# 106 dq51 136 vss 166 vss 196 a13 226 vss 17 vss 47 vss 77 odt1 107 vss 137 dq14 167 nc 197 vdd 227 dq60 18 dq10 48 vtt 78 vdd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 vtt 79 nc 109 dq57 139 vss 169 cke1 199 vss 229 vss 20 vss 50 cke0 80 vss 110 vss 140 dq20 170 vdd 200 dq36 230 dqs16 21 dq16 51 vdd 81 dq32 111 dqs7# 141 dq21 171 a15 201 dq37 231 dqs16# 22 dq17 52 ba2 82 dq33 112 dqs7 142 vss 172 a14 202 vss 232 vss 23 vss 53 err_out# 83 vss 113 vss 143 dqs11 173 vdd 203 dqs13 233 dq62 24 dqs2# 54 vdd 84 dqs4# 114 dq58 144 dqs11# 174 a12 204 dqs13# 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 vss 175 a9 205 vss 235 vss 26 vss 56 a7 86 vss 116 vss 146 dq22 176 vdd 206 dq38 236 vddspd 27 dq18 57 vdd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 vss 178 a6 208 vss 238 sda 29 vss 59 a4 89 vss 119 sa2 149 dq28 179 vdd 209 dq44 239 vss 30 dq24 60 vdd 90 dq40 120 vtt 150 dq29 180 a3 210 dq45 240 vtt
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 4 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm pin assignments and descriptions table 5: pin descriptions symbol type description a[15:0] input address inputs: provide the row address for acti vate commands, and the column address and auto precharge bit (a10) for re ad/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whethe r the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all ba nks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also used for bc4/bl8 iden tification as ?bl on-the-fly? during cas commands. the addr ess inputs also provide th e op-code during the mode register command set . a[14:0] address the 4gb ddr3 device s. a15 is needed to calculate parity on the command/address bus. ba[2:0] input bank address inputs: ba[2:0] define the device bank to which an activate, read, write, or precharge command is being appl ied. ba[2:0] define which mode register (mr0, mr1, mr2, and mr3) is loaded duri ng the load mode command. ba[1:0] are used as part of the parity calculation. ck0, ck0# input clock: ck and ck# are differential clock inputs. all control, command, and address input signals are sampled on the crossing of the posi tive edge of ck and the negative edge of ck#. cke[1:0] input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and cloc ks on the dram. odt[1:0] input on-die termination: odt enables (registe red high) and disables (registered low) termination resistance internal to the dram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, and dqs#. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for the addr ess, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input (lvcmos) reset: reset# is an active low cmos input refe renced to vss. the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 vdd and dc low 0.2 vdd. reset# assertion and deassertion are asynchronous. s#[1:0] input chip select: s# enables (registered low) and disa bles (registered high) the command decoder. sa[2:0] input serial address inputs: these pins are used to configure the temperature sensor/spd eeprom address range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: scl is used to synchronize communication to and from the temperature sensor/spd eeprom. cb[7:0] i/o check bits: data used for ecc. dq[63:0] i/o data input/output: bidirectional data bus. dqs[17:0], dqs#[17:0] i/o data strobe: dqs and dqs# are differential data s trobes. output with read data. edge- aligned with read data. input with writ e data. center-aligned with write data. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/spd eepr om on the module on the i 2 c bus. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. vdd supply power supply: 1.5v 0.075v. the component vdd and vddq are connected to the module vdd. vddspd supply temperature sensor/spd eeprom power supply: +3.0v to +3.6v. vrefca supply reference voltage: control, command, and address (vdd/2). vrefdq supply reference voltage: dq, dm (vdd/2). vss supply ground.
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 5 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm pin assignments and descriptions vtt supply termination voltage: used for control, comma nd, and address (vdd/2). nc ? no connect: these pins are not co nnected on the module. nf ? no function: connected within the module, but provides no functionality. table 5: pin descriptions (continued) symbol type description
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 6 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm functional block diagram functional block diagram figure 2: functional block diagram notes: 1. the zq ball on each ddr3 component is connec ted to an external 240 1% resistor that is tied to ground. it is used for the calibration of the component?s odt and output driver. dm cs# dqs dqs# dq dq dq dq zq dq0 dq1 dq2 dq3 vss dq dq dq dq u1b u1t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq4 dq5 dq6 dq7 vss dq dq dq dq u20b u20t dm cs# dqs dqs# dqs0 dqs0# dqs9 dqs9# dm cs# dqs dqs# dq dq dq dq zq dq8 dq9 dq10 dq11 vss dq dq dq dq u2b u2t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq12 dq13 dq14 dq15 vss dq dq dq dq u19b u19t dm cs# dqs dqs# dqs1 dqs1# dqs10 dqs10# dm cs# dqs dqs# dq dq dq dq zq dq16 dq17 dq18 dq19 vss dq dq dq dq u3b u3t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq20 dq21 dq22 dq23 vss dq dq dq dq u18b u18t dm cs# dqs dqs# dqs2 dqs2# dqs11 dqs11# dm cs# dqs dqs# dq dq dq dq zq dq24 dq25 dq26 dq27 vss dq dq dq dq u4b u4t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq28 dq29 dq30 dq31 vss dq dq dq dq u17b u17t dm cs# dqs dqs# dqs3 dqs3# dqs12 dqs12# dm cs# dqs dqs# dq dq dq dq zq cb0 cb1 cb2 cb3 vss dq dq dq dq u5b u5t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq cb4 cb5 cb6 cb7 vss dq dq dq dq u16b u16t dm cs# dqs dqs# dqs8 dqs8# dqs17 dqs17# dm cs# dqs dqs# dq dq dq dq zq dq32 dq33 dq34 dq35 vss dq dq dq dq u7b u7t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq36 dq37 dq38 dq39 vss dq dq dq dq u14b u14t dm cs# dqs dqs# dqs4 dqs4# dqs13 dqs13# dm cs# dqs dqs# dq dq dq dq zq dq40 dq41 dq42 dq43 vss dq dq dq dq u8b u8t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq44 dq45 dq46 dq47 vss dq dq dq dq u13b u13t dm cs# dqs dqs# dqs5 dqs5# dqs14 dqs14# dm cs# dqs dqs# dq dq dq dq zq dq48 dq49 dq50 dq51 vss dq dq dq dq u9b u9t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq52 dq53 dq54 dq55 vss dq dq dq dq u12b u12t dm cs# dqs dqs# dqs6 dqs6# dqs15 dqs15# dm cs# dqs dqs# dq dq dq dq zq dq56 dq57 dq58 dq59 vss dq dq dq dq u10b u10t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq60 dq61 dq62 dq63 vss dq dq dq dq u11b u11t dm cs# dqs dqs# dqs7 dqs7# dqs16 dqs16# rs0# rs1# zq zq zq zq zq zq zq zq vss zq zq zq zq zq zq zq zq zq zq r e g i s t e r a n d p l l s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 par_in reset# ck0 ck0# rs0#: rank 0 rs1#: rank 1 rba[2:0]: ddr3 sdram ra[14:0]: ddr3 sdram rras#: ddr3 sdram rcas#: ddr3 sdram rwe#: ddr3 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 err_out# u6 vrefca vss vss ddr3 sdram ddr3 sdram vdd ddr3 sdram vddspd temperature sensor/spd eeprom vtt ddr3 sdram ddr3 sdram vrefdq ck ck# ddr3 sdram ddr3 sdram rank 0: u1b?u5b, u7b?u14b, u16b?u20b rank 1: u1t?u5t, u7t?u14t, u16t?u20t vss rs#[1:0], rcke[1:0], ra[14:0], rras#, rcas#, rwe#, rodt[1:0], rba[2:0] ck ck# clock, command, control, and address line terminations: ddr3 sdram vtt ddr3 sdram vdd u15 a0 temperature sensor/ spd eeprom a1 a2 sa0 sa1 sda scl evt event# vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 7 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm general description general description the mt36jczs1g72p ddr3 sdram module is a high-speed, cmos dynamic random access 8gb memory module organized in a x72 configuration. this ddr3 sdram module uses internally configured, 8-bank 4gb twindie ddr3 sdram devices. ddr3 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. ddr3 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. control, command, and address signals are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. fly-by topology these ddr3 modules use faster clock speed s than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, wh ere the termination is off the module near the connector). inherent to fly-by topology , the timing skew between the clock and dqs signals can be easily accounted for by using the write-leveling feature of ddr3. registering clock driver operation registered ddr3 sdram modules use a registering clock driver consisting of a register and a phase-lock loop (pll) and comply with the jedec standard, ?definition of the sste32882 registering clock driver with parity and quad chip selects for ddr3 rdimm applications.? the register section of the registering clock driver latches command and address input signals on the rising clock edge. the pll section of the registering clock driver receives and redrives the differential clock signals (c k, ck#) to the ddr3 sdram devices. the register(s) and pll reduce clock, control, command, and address signals loading by isolating dram from the system controller. parity operations the registering clock driver can accept a pari ty bit from the system?s memory controller, providing even parity for the control, comm and, and address bus. parity errors are flagged on the err_out# pin. systems not using parity are expected to function without issue if par_in and err_out# are left as no connects to the system.
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 8 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm general description temperature sensor with serial presence-detect eeprom thermal sensor operations the temperature from the integrated thermal sensor is monitored and converts into a digital word via the i 2 c bus. system designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. programming and configuration details comply with jedec standard no. 21-c, page 4.7-1 ?mobile platform memory module thermal sensor component specification.? serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are prog rammed by micron to comply with jedec standard jc-45 ?appendix x: serial presence detect (spd) for ddr3 sdram modules.? these bytes identify module-specific timing parameters, configuration information, and physical attributes. user-specific inform ation can be written into the remaining 128 bytes of storage. read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/eeprom addresses. write protect (wp) is connected to vss internal to the temp sensor/eeprom, permanently disabling hardware write protection.
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 9 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 6 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. vtt termination voltage in excess of the stated limit will adversely affect the command and address signals? voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: ?thermal applications,? available on micron?s web site. 4. the refresh rate is requir ed to double when 85c < t c 95c. table 6: absolute maximum ratings symbol parameter min max units vdd vdd supply voltage relative to vss ?0.4 +1.975 v vin, vout voltage on any pin relative to vss ?0.4 +1.975 v table 7: operating conditions symbol parameter min nom max units notes vdd vdd supply voltage 1.425 1.5 1.575 v ivtt termination reference current from vtt ?600 ? +600 ma vtt termination reference voltage (dc) ? command/address bus 0.49 vdd - 20mv 0.5 vdd 0.51 vdd + 20mv v 1 ii input leakage current; any input 0v vin vdd; vref input 0v vin 0.95v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, s#, cke, odt, ba, ck, ck# tbd tbd tbd a ioz output leakage current; 0v vout vdd; dq and odt are disabled; odt is high dq, dqs, dqs# ?10 0 +10 a ivref vref supply leakage current; vrefdq = vdd/2 or vrefca = vdd/2 (all other pins not under test = 0v) ?36 0 +36 a t a module ambien t operating temperature commercial 0 ? +70 c 2, 3 industrial ?40 ? +85 c t c ddr3 sdram component case operating temperature commercial 0 ? +95 c 2, 3, 4 industrial ?40 ? +95 c
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 10 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 8: module and component speed grades ddr3 components may exceed th e listed module speed grades module speed grade component speed grade -1g1 -187e -1g0 -187 -80c -25e -80b -25
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 11 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm electrical specifications idd specifications table 9: ddr3 idd specifications and conditions ? 8gb values are for the mt41j1g4thu ddr3 sdram only and are computed from va lues specified in the 4gb twindie (1 gig x 4) component data sheet parameter combined symbol 1066 800 units operating current 0: one bank activate-to-precharge icdd0 1890 1620 ma operating current 1: one bank activate-to-read-to-precharge icdd1 2340 2070 ma precharge power-down current: slow exit icdd2p 360 360 ma precharge power-down current: fast exit icdd2p 630 630 ma precharge quiet standby current icdd2q 1260 1080 ma precharge standby current icdd2n 1350 1170 ma active power-down current icdd3p 1080 990 ma active standby current icdd3n 1620 1440 ma burst read operating current icdd4r 3870 3420 ma burst write operating current icdd4w 4320 3780 ma refresh current icdd5b 5490 5220 ma self refresh temperature current: max t c = 85c icdd6 324 324 ma self refresh temperature current (srt-enabled): max t c = 95c icdd6et 432 432 ma all banks interlea ved read current icdd7 6480 6030 ma
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 12 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm registering clock driver specifications registering clock driver specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr3 sdram rdimms. these are mean t to be a subset of the parameters for the specific device used on the module. table 10: registering clock driver electrical characteristics sste32882 devices or equivalent symbol parameter pins min nom max units vdd dc supply voltage ? 1.425 1.5 1.575 v vref dc reference voltage ? 0.49 vdd - 20mv 0.5 vdd 0.51 vdd + 20mv v vtt dc termination voltage ? 0.49 vdd - 20mv 0.5 vdd 0.51 vdd + 20mv v vih(ac) ac high-level input voltage control, command, address vref + 175mv ? vdd + 400mv v vil(ac) ac low-level input voltage control, command, address ?0.4 ? vref - 175mv v vih(dc) dc high-level input voltage control, command, address vref + 100mv ? vdd + 0.4 v vil(dc) dc low-level input voltage control, command, address ?0.4 ? vref - 100mv v vih(cmos) high-level input voltage reset#, mirror 0.65 vdd ? vdd v vil(cmos) low-level input voltage reset#, mirror 0 ? 0.35 vdd v vix(ac) differential input crosspoint voltage range ck, ck#, fbin, fbin# 0.5 vdd - 175mv 0.5 vdd 0.5 vdd + 175mv v vid(ac) differential input voltage ck, ck# 350 ? vdd + tbd mv ioh high-level output current all outputs except err_out# ??tbdma iol low-level output current all outputs except err_out# ??tbdma iol low-level output current (err_out#) err_out# tbd ? tbd ma vod differential redriven clock swing y n , y n #500? vddmv vox differential output crosspoint voltage y n , y n # 0.5 vdd - 100mv ? 0.5 vdd + 100mv v
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 13 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom temperature sensor with se rial presence-detect eeprom the temperature sensor continuously monitors the module?s temperature and can be read back at any time over the i 2 c bus shared with the spd eeprom. event# pin the temperature sensor also adds the event# pin (open drain). not used by the spd eeprom, event# is a temperature sensor output used to flag critical events that can be set up in the sensor?s configuration register. event# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. the open-drain output of event# under the three separate operating modes is illustrated in figure 3 on page 14. event thresholds are programmed in the 0x01 register using a hysteresis. the alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. when the alarm window is enabled, event# will trigger whenever the temperature is outside the min or max values set by the user. the interrupt mode enables software to re set event# after a critical temperature threshold has been detected. threshold points are set in the configuration register by the user. this mode triggers the critical temper ature limit and both the min and max of the temperature window. table 11: temperature sensor with serial presence-detect eeprom operating conditions parameter/condition symbol min max units supply voltage vddspd +3.0 +3.6 v supply current: vdd = 3.3v idd ? +2.0 ma input high voltage: logic 1; scl, sda vih +1.45 vddspd + 1 v input low voltage: logic 0; scl, sda vil ? +0.55 v output low voltage: iout = 2.1ma vol ? +0.4 v input current iin ?5.0 +5.0 a temperature sensing range ? ?40 +125 c temperature sensor accuracy (class b) ??1.0+1.0c table 12: sensor and eeprom serial interface timing parameter/condition symbol min max units time bus must be free before a new transition can start t buf 4.7 ? s sda fall time t f20300ns sda rise time t r ? 1000 ns data hold time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 ? s clock high period t high 4.0 50 s clock low period t low 4.7 ? s scl clock frequency f scl 10 100 khz data setup time t su:dat 250 ? ns start condition setup time t su:sta 4.7 ? s stop condition setup time t su:sto 4.0 ? s
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 14 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom the compare mode is similar to the interrupt mode, except event# cannot be reset by the user and only returns to the logic high state when the temperature falls below the programmed thresholds. critical temperature mode triggers event# only when the temperature has exceeded the programmed critical trip point. when the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical event# cannot be cleared through software. sm bus slave subaddress decoding the temperature sensor?s physical address differs from the spd eeprom?s physical address: 0011 for a0, a1, a2, and rw# in binary where a2, a1, and a0 are the three slave subaddress pins and the rw# bit is the read/write flag. if the slave base address is fixed for the temperature sensor/spd eeprom, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. for example, they could be set from 30h to 3eh. figure 3: event# pin functionality time temperature c riti c al alarm win d ow (max) alarm win d ow (min) event# interrupt mo d e event# c omparator mo d e event# c riti c al temperature only mo d e c lears event hysteresis affects these trip points
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 15 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pointer register the pointer register selects which of the 16-bit registers is being accessed in subsequent read and write operations. this register is a write-only register. table 13: temperature sensor registers name address power-on default pointer register not applicable undefined capability register 0x00 0x0001 configuration register 0x01 0x0000 alarm temperature uppe r boundary register 0x02 0x0000 alarm temperature lower boundary register 0x03 0x0000 critical temperature register 0x04 0x0000 temperature register 0x05 undefined table 14: pointer register bits 0?7 bit 7 6 5 4 3 2 1 0 0000register select register select register select register select table 15: pointer register bits 0?2 descriptions bit register 2 1 0 000 capability register 001 configuration register 010 alarm temperature upper boundary register 011 alarm temperature lower boundary register 100 critical temperature register 101 temperature register
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 16 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom capability register the capability register indicates the features and functionality supported by the temper- ature sensor. this register is a read-only register. configuration register table 16: capability register (address: 0x00) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu rfu rfu rfu bit 7 6 5 4 3 2 1 0 rfu rfu rfu temperature resolution wider range precision has alarm and critical temperature table 17: capability register bit descriptions bit description 0 basic capability 1: has alarm and critical trip point capabilities 1 accuracy 0: 2c over the acti ve range and 3c ov er the monitor range 1: 1c over the acti ve range and 2c ov er the monitor range 2 wider range 0: temperatures lower than 0c ar e clamped to a binary value of 0 1: temperatures below 0c can be read 4:3 temperature resolution 00: 0.5c lsb 01: 0.25c lsb 10: 0.125c lsb 11: 0.0625c lsb 15:5 0: must be set to zero table 18: configuration register (address: 0x01) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu hysteresis shutdown mode bit 7 6 5 4 3 2 1 0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 17 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom table 19: configuration register bit descriptions bit description notes 0 event mode 0: comparator mode 1: interrupt mode event mode cannot be changed if either of the lock bits is set. 1 event# polarity 0: active low 1: active high event# polarity cannot be chan ged if either of the lock bits is set. 2 critical event only 0: event# trips on alarm or critical temperature event 1: event# trips only if critical temperature is reached 3 event output control 0: event output disabled 1: event output enabled 4 event status 0: event# has not been asserted by this device 1: event# is being asserted due to an alarm window or critical temper ature condition this is a read-only field in the register. the event causing the event can be determined from the read temperature register. 5 clear event 0: no effect 1: clears the event when the temperature sensor is in the interrupt mode 6 alarm window lock bit 0: alarm trips are not locked and can be changed 1: alarm trips are locked and cannot be changed 7 critical trip lock bit 0: critical trip is not locked and can be changed 1: critical trip is locked and cannot be changed 8 shutdown mode 0: enabled 1: shutdown the shutdown mode is a power-saving mode that disables the temperature sensor. 10:9 hysteresis enable 00: disable 01: enable at 1.5c 10: enable at 3c 11: enable at 6c when enabled, a hysteresis is applied to temperature movement around the trip points. as an example, if the hysteresis register is enabled to a delta of 6c, the preset trip points will to ggle when the temperature reaches the programmed valu e. these values will reset when the temperature drop s below the trip points minus the set hysteresis level. in this case, this would be critical temperature minus 6c. the hysteresis is applied both to the above alarm window and the below alarm window bits found in the read-only temperature register. event# is also affected by this register.
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 18 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom figure 4: hysteresis notes: 1. t h is the value set in the alarm temp erature upper boundary trip register. 2. t l is the value set in the alarm temp erature lower boun dary trip register. 3. hyst is the value set in the hysteresis bits of the configuration register. table 20: hysteresis condition below alarm window bit above alarm window bit temperature gradient critical temperature temperature gradient critical temperature sets falling t l - hyst rising t h clears rising t l falling t h - hyst t h t l t h - hyst t l - hyst below window bit above window bit 1 2 3
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 19 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom temperature format the temperature trip point registers and temperature readout register use a ?2?s complement? format to enable negative numbers. the least significant bit (lsb) is equal to 0.0625c or 0.25c depending on which register is referenced. as an example, assuming an lsb of 0.0625c: ? a value of 0x018c would equal 24.75c ? a value of 0x06c0 would equal 108c ? a value of 0x1e74 would equal ?24.75c temperature trip point registers the upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. lsb for these registers is 0.25c. all rfu bits in the register will always report zero. critical temperature register the critical temperature register is used to set the maximum temperature above the alarm window. the lsb for this register is 0.25c. all rfu bits in the register will always report zero. table 21: alarm temperature lower boundary register (address: 0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu alarm window upper boundary temperature table 22: alarm temperature lower boundary register (address: 0x03) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu alarm window lower boundary temperature table 23: critical temperature register (address: 0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu critical temperature trip point
pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 20 ?2008 micron technology, inc. all rights reserved. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom temperature register the temperature register is a read-only regi ster that provides the current temperature detected by the temperature sensor. the lsb fo r this register is 0.0625c with a resolu- tion of 0.0625c. the most significant bit (m sb) is 128c in the readout section of this register. the upper three bits of the register are used to monitor the trip points that are set in the previous three registers. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 24: temperature register (address: 0x05) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 above critical trip above alarm window below alarm window msb lsb temperature table 25: temperature register bit descriptions bit description 13 below alarm window 0: temperature is equal to or above the lower boundary 1: temperature is below alarm window 14 above alarm window 0: temperature is equal to or below the upper boundary 1: temperature is above alarm window 15 above critical trip point 0: temperature is below critical trip point 1: temperature is above critical trip point
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron, the micron logo, and twindie are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 8gb (x72, ecc, dr): 240-pin ddr3 sdram rdimm module dimensions pdf: 09005aef8333011d/source: 09005aef833301e5 micron technology, inc., reserves the right to change products or specifications without notice. jczs36c1gx72py.fm - rev. c 12/08 en 21 ?2008 micron technology, inc. all rights reserved. module dimensions figure 5: 240-pin ddr3 rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 19.6 (0.772) 19.4 (0.764) pin 1 2.5 (0.098) d (2x) 2.3 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.8 (0.031) typ 0.75 (0.03) r (6x) 0.76 (0.03) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) max 2.2 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) x4 typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 1.37 (0.054) 1.17 (0.046) 9.01 (0.354) max* with heat spreader attached u1 u1 u1 u2 u2 u2 u3 u3 u3 u4 u4 u4 u5 u5 u5 u7 u7 u7 u8 u8 u8 u9 u9 u9 u10 u10 u10 u11 u11 u11 u12 u12 u12 u13 u13 u13 u14 u14 u14 u16 u16 u16 u17 u17 u17 u18 u18 u18 u19 u19 u19 u20 u20 u20 1.75 (0.069) typ * nominal width 8.77 (0.345)

▲Up To Search▲

Price & Availability of MT36JCZS1G72PY-1G0XX

	To Download MT36JCZS1G72PY-1G0XX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .