 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| the m pd70433 (v55pi) is a microprocessor in which a 16-bit cpu, ram, serial interface, parallel interface, a/d converter, timers, dma controller, interrupt controller, etc., are integrated in a single chip. the v55pi is software-compatible with the m pd70320 and 70330 (v25 tm and v35 tm ) single-chip microcontrollers. the v55pi provides a migration path from the v25. it offers higher-level functions and higher performance, and is particularly suitable for control of data processing systems associated with mechanical control, including printer and facsimile. detailed functions are described in the following users manuals, which should be read when carrying out design work. ? v55pi users manual hardware : u10514e ? v55pi users manual instruction : u10231e features internal 16-bit architecture, selectable external data bus width (16/8 bits) software compatible with v20 tm and v30 tm (native mode) and v25 and v35 (includes additional instructions) minimum instruction cycle: 160 ns/12.5 mhz (external 25 mhz) 125 ns/16 mhz (external 32 mhz) address space: 16m bytes: 1-mbyte basic memory space 16-mbyte extended memory space register file space (in on-chip ram) : 512 bytes/16 register banks i/o space : 64k bytes automatic wait control with memory space divided in variable sizes (max. 6 blocks) i/o line (input ports: 11 bits, input/output ports: 42 bits) dma controller (dmac): max. 4-channel configuration possible ? four dma transfer modes (single transfer, demand release, single step, burst) ? intelligent dma modes 1 and 2 serial interface: 2 channels ? asynchronous mode (uart) or clocked mode (csi) selectable parallel interface: 8 bits ? centronics data input/output and general-purpose data input/output a/d converter (8 bits): 4 channels real-time output port: 4 bits 2 channels or 8 bits 1 channel pmw (pulse width modulation) output function : 8 bits description mos integrated circuit m pd70433 v55pi tm 16-bit microprocessor document no. u11775ej4v0ds00 (4th edition) previous no. ic-8257 date published november 1996 p printed in japan 1995 data sheet the information in this document is subject to change without notice. the mark shows major revised points.
2 m pd70433 ordering information part number package m pd70433gd-12-5bb 120-pin plastic qfp (28 28 mm) 12.5 m pd70433gd-16-5bb 120-pin plastic qfp (28 28 mm) 16 m pd70433r-12 132-pin ceramic pga 12.5 m pd70433r-16 132-pin ceramic pga 16 m pd70433gj-12-3eb 120-pin plastic qfp (fine pitch) (20 20 mm) 12.5 m pd70433gj-16-3eb 120-pin plastic qfp (fine pitch) (20 20 mm) 16 interrupt controller ? programmable priority (4 levels) ? three interrupt servicing methods vectored interrupt function, register bank switching function, macro service function 16-bit timer: 4 channels watchdog timer function software interval timer (16 bits) address field wait insertion function and ras/cas switchover timing generation function dram and pseudo-sram refresh functions standby functions (stop mode, halt mode) on-chip clock generator applications control of data processing systems using serial or parallel communication (data processing terminals, printer, g3 facsimile, etc.) maximum operating frequency (mhz) 3 m pd70433 pin configuration (top view) (1) 120-pin plastic qfp (28 28 mm), 120-pin plastic qfp (fine pitch) (20 20 mm) m pd70433gd-xx-5bb m pd70433gj-xx-3eb remark ic: internally connected notes 1. the ic (h) pin should be connected to v dd with an external resistor (1 to 10 k w ). 2. the ic (l) pin should be connected to gnd with an external resistor (1 to 10 k w ). 3. no connection should be made to the open pin. 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 open dex ras iord iowr rd wrl wrh astb ic (l) d8/d16 gnd v dd a23 a22 a21 a20 a19 a18 a17 a16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 91 313233343536373839404142434445464748495051525354555657585960 p20/pwm p21/to00 p22/to01 p23/to20 p24/to21 p25/to30 p30/t x d0/sb0/so0 p31/r x d0/sb1/si0 p32/t x c/sck0 p33/cts0 p34/t x d1/so1 p35/r x d1/si1 p36/sck1/cts1 v dd p40/pd0 p41/pd1 p42/pd2 p43/pd3 p44/pd4 p45/pd5 p46/pd6 p47/pd7 gnd p50/datastb p51/ack p52/busy av ss v dd p60/ani0 p61/ani1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ic (h) gnd v dd tce1 tce0 dmaak1 dmaak0 p81/dmarq1 p80/dmarq0 v dd p77/rtpt7 p76/rtpt6 p75/rtpt5 p74/rtpt4 p73/rtpt3 p72/rtpt2 p71/rtpt1 p70/rtpt0 gnd av dd av ref p63/ani3 p62/ani2 72 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v dd buslock hldak hldrq ready poll clkout reset wdtout v dd x1 x2 gnd refrq p00 p01 p02 p03 p04 p05 p06 p07 gnd p10/nmi p11/intp0 p12/intp1 p13/intp2 p14/intp3/ti p15/intp4 p16/intp5 4 m pd70433 (2) 132-pin ceramic pga m pd70433r-xx remark the locator pin is not included in the pin count. no. signal nane port no. signal name port no. signal name port a1 ani1 p61 b5 pd7 p47 c9 cts0 p33 a2 av ss CC b6 pd5 p45 c10 to30 p25 a3 ack p51 b7 pd2 p42 c11 to00 p21 a4 datastb p50 b8 pd0 p40 c12 nc CC a5 pd6 p46 b9 r x d1/si1 p35 c13 intp4 p15 a6 pd4 p44 b10 r x d0/sb1/si0 p31 c14 intp0 p11 a7 pd1 p41 b11 to21 p24 d1 rtpt2 p72 a8 nc CC b12 to01 p22 d2 gnd CC a9 sck1/cts1 p36 b13 nc CC d3 ani3 p63 a10 t x d1/so1 p34 b14 intp3/ti p14 d12 intp5 p16 a11 t x c/sck0 p32 c1 rtpt1 p71 d13 intp2 p13 a12 t x d0/sb0/so0 p30 c2 av ref CC d14 nmi p10 a13 to20 p23 c3 nc CC e1 rtpt5 p75 a14 pwm p20 c4 nc CC e2 rtpt3 p73 b1 av dd CC c5 v dd CC e3 rtpt0 p70 b2 ani2 p62 c6 gnd CC e12 intp1 p12 b3 ani0 p60 c7 pd3 p43 e13 gnd CC b4 busy p52 c8 v dd CC e14 CC p06 locator pin a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bottom view p n m l k j h g f e d c b a top view index mark 5 m pd70433 remark ic: internally connected nc: non-connection notes 1. the ic (h) pin should be connected to v dd with an external resistor (1 to 10 k w ). 2. the ic (l) pin should be connected to gnd with an external resistor (1 to 10 k w ). 3. no connection should be made to the open pin. no. signal nane port no. signal name port no. signal name port f1 rtpt7 p77 k3 ad2 CCC n3 ad9 CCC f2 rtpt6 p76 k12 poll CCC n4 ad11 CCC f3 rtpt4 p74 k13 wdtout CCC n5 ad14 CCC f12 CCC p07 k14 x1 CCC n6 a18 CCC f13 CCC p05 l1 ad0 CCC n7 a21 CCC f14 CCC p04 l2 ad3 CCC n8 a23 CCC g1 nc CCC l3 ad6 CCC n9 d8/d16 CCC g2 dmarq0 p80 l12 buslock CCC n10 astb CCC g3 v dd CCC l13 ready CCC n11 iowr CCC g12 CCC p03 l14 reset CCC n12 dex CCC g13 CCC p02 m1 ad1 CCC n13 v dd CCC g14 CCC p01 m2 ad5 CCC n14 hldrq CCC h1 dmarq1 p81 m3 nc CCC p1 ad7 CCC h2 dmaak0 CCC m4 ad8 CCC p2 ad10 CCC h3 dmaak1 CCC m5 ad12 CCC p3 ad13 CCC h12 refrq CCC m6 a16 CCC p4 ad15 CCC h13 CCC p00 m7 a20 CCC p5 a17 CCC h14 nc CCC m8 v dd CCC p6 a19 CCC j1 tce0 CCC m9 wrh CCC p7 nc CCC j2 tce1 CCC m10 iord CCC p8 a22 CCC j3 gnd CCC m11 nc CCC p9 gnd CCC j12 v dd CCC m12 nc CCC p10 ic (l) CCC j13 x2 CCC m13 hldak CCC p11 wrl CCC j14 gnd CCC m14 clkout CCC p12 rd CCC k1 v dd CCC n1 ad4 CCC p13 ras CCC k2 ic (h) CCC n2 nc CCC p14 open CCC 6 m pd70433 internal block diagram x1 x2 av ref av ss av dd ani0?ni3 busy ack datastb 4 8 cts1/sck1 pd0?d7 t x d1/so1 r x d1/si1 cts0 t x c/sck0 t x d0/sb0/so0 r x d0/sb1/si0 system control 8-bit a/d piu uart/csi uart/csi dma request general registers & data memory 512 bytes alu micro rom micro sequence control exu bcu prefetch queue 6 bytes bus control & prefetch control dmac pwm unit timer/ counter unit wdt programmable interrupt controller port rtop 4 4 8 7 6 7 8 3 4 8 2 6 4 ?pwm ?to00 ?to20 ?to03 ?wdtout ?to01 ?to21 ?intp0 ?intp1 ?intp2 ?intp3/ti ?intp4 ?intp5 rtp0?tp3 rtp4?tp7 port0 port1 port2 port3 port4 port5 port6 port7 port8 nmi reset clkout v dd gnd astb ready rd wrh wrl iord iowr ras dex d8/d16 buslock poll hldrq hldak a16?23 ad0?d15 dmarq0 dmaak0 tce0 dmarq1 dmaak1 tce1 refrq 7 m pd70433 contents 1. pin functions ............................................................................................................................... ........ 10 1.1 list of pin function ............................................................................................................................... ..... 10 1.1.1 port pins ............................................................................................................................... ................. 10 1.1.2 non-port pins ............................................................................................................................... ......... 11 2. block configuration ....................................................................................................................... 14 2.1 bus control unit (bcu) ............................................................................................................................. 14 2.2 execution unit (exu) ............................................................................................................................... .... 14 2.3 interrupt controller (intc) ................................................................................................................. 14 2.4 dma controller (dmac) ........................................................................................................................... 14 2.5 uart/clocked serial interface (uart/csi) ...................................................................................... 14 2.6 parallel interface unit (piu) ................................................................................................................ 14 2.7 a/d converter unit (8-bit a/d) ................................................................................................................ 14 2.8 timer/counter unit (tcu) ......................................................................................................................... 14 2.9 pwm (pulse width modulation) unit (pwm) ....................................................................................... 14 2.10 watchdog timer (wdt) .............................................................................................................................. 1 4 2.11 ports (port) ............................................................................................................................... .................... 14 2.12 real-time output port (rtop) ................................................................................................................ 14 2.13 clock generator (cg) .............................................................................................................................. 1 5 2.14 software interval timer (sit) .............................................................................................................. 15 3. cpu functions ............................................................................................................................... ........ 16 3.1 features ............................................................................................................................... ........................... 16 3.2 registers ............................................................................................................................... .......................... 17 3.2.1 register banks ............................................................................................................................... ....... 17 3.2.2 general registers (aw, bw, cw, dw) .............................................................................................. 19 3.2.3 pointers (sp, bp) and index registers (ix, iy) ................................................................................. 20 3.2.4 segment registers (ps, ss, ds0, ds1) ............................................................................................. 20 3.2.5 extended segment registers (ds2, ds3) ......................................................................................... 21 3.2.6 special function registers (sfr) ...................................................................................................... 22 3.3 program counter (pc) .............................................................................................................................. 2 3 3.4 program status words (psw) ............................................................................................................... 23 3.5 memory space ............................................................................................................................... ................ 24 3.5.1 basic memory space ........................................................................................................................... 24 3.5.2 extended memory space ..................................................................................................................... 25 3.5.3 special function register area .......................................................................................................... 26 3.5.4 vector table area ............................................................................................................................... .. 34 3.6 register file space ............................................................................................................................... ...... 36 3.7 i/o space ............................................................................................................................... ........................... 38 4. bus control functions .................................................................................................................... 39 4.1 wait function ............................................................................................................................... ................ 39 4.2 refresh function ............................................................................................................................... ......... 41 4.2.1 refresh mode register (rfm) ............................................................................................................. 41 4.2.2 wait control in refresh cycle ............................................................................................................ 41 4.2.3 refresh address ............................................................................................................................... .... 41 8 m pd70433 5. interrupt functions ......................................................................................................................... 42 5.1 features ............................................................................................................................... .......................... 42 5.2 interrupt response methods ............................................................................................................... 45 5.2.1 vectored interrupts .............................................................................................................................. 4 5 5.2.2 register bank switching function .................................................................................................... 46 5.2.3 macro service function ....................................................................................................................... 47 6. dma function (dma controller) ..................................................................................................48 6.1 features ............................................................................................................................... ........................... 48 7. serial interface functions ........................................................................................................... 50 7.1 features ............................................................................................................................... ........................... 50 7.2 protocols ............................................................................................................................... ........................ 50 7.3 uart ............................................................................................................................... .................................... 51 7.3.1 features ............................................................................................................................... .................. 51 7.4 clocked serial interface (csi) ............................................................................................................... 52 7.4.1 features ............................................................................................................................... .................. 52 8. parallel interface functions .....................................................................................................53 8.1 features ............................................................................................................................... ........................... 53 9. timer function ............................................................................................................................... ...... 55 9.1 features ............................................................................................................................... ........................... 55 9.2 timer unit configuration ....................................................................................................................... 55 9.3 real-time output port function .......................................................................................................... 57 9.3.1 real-time output port configuration ................................................................................................ 57 9.3.2 real-time output port operation ...................................................................................................... 59 10. pwm unit ............................................................................................................................... ................... 61 10.1 features ............................................................................................................................... ........................... 61 10.2 pwm unit configuration ......................................................................................................................... 61 11. watchdog timer function .............................................................................................................. 63 11.1 features ............................................................................................................................... ........................... 63 11.2 watchdog timer configuration and operation .......................................................................... 63 12. a/d converter function .................................................................................................................. 64 12.1 features ............................................................................................................................... ........................... 64 13. standby function ............................................................................................................................... 66 13.1 halt mode ............................................................................................................................... ........................ 66 13.2 stop mode ............................................................................................................................... ........................ 67 14. clock generator ............................................................................................................................... 68 14.1 clock generator configuration and operation ......................................................................... 68 9 m pd70433 15. software interval timer function ........................................................................................... 70 15.1 software interval timer configuration ........................................................................................ 70 16. codec instruction .............................................................................................................................. 7 1 16.1 features ............................................................................................................................... ........................... 71 16.2 memory map ............................................................................................................................... .................... 74 16.3 processing flow ............................................................................................................................... .......... 76 17. instruction set ............................................................................................................................... ..... 78 17.1 instructions newly added to v20/v30 and v25/v35 ..................................................................... 78 17.2 instruction set operations ................................................................................................................... 80 17.3 instruction set table ............................................................................................................................. 10 5 18. electrical specifications ............................................................................................................128 19. characteristic curves (for reference only) ................................................................... 158 20. package drawings ........................................................................................................................... 159 21. recommended soldering conditions ...................................................................................... 162 10 m pd70433 port 6 input/output specifiable bit-wise 4-bit input/output port port 0 input/output specifiable bit-wise 8-bit input/output port 1. pin functions 1.1 list of pin functions 1.1.1 port pins pin name input/output function alternate function p00 to p07 input/output p10 * nmi p11 intp0 p12 intp1 p13 intp2 p14 intp3/ti p15 intp4 p16 intp5 p20 pwm p21 to00 p22 to01 p23 to20 p24 to21 p25 to30 p30 txd0/sb0/so0 p31 rxd0/sb1/si0 p32 txc/sck0 p33 cts0 p34 txd1/so1 p35 rxd1/si1 p36 cts1/sck1 p40 to p47 pd0 to pd7 p50 datastb p51 ack p52 busy p60 to p63 ani0 to ani3 p70 to p77 rtp0 to rtp7 p80 dmarq0 p81 dmarq1 port 1 7-bit input port port 2 input/output specifiable bit-wise 6-bit input/output port port 3 input/output specifiable bit-wise 7-bit input/output port port 4 input/output specifiable bit-wise 8-bit input/output port * unusable as general-purpose port (non-maskable interrupt) port 5 input/output specifiable bit-wise 3-bit input/output port port 7 input/output specifiable bit-wise 8-bit input/output port port 8 input/output specifiable bit-wise 2-bit input/output port input/output input/output input input 11 m pd70433 pin name function ad0 to ad15 a16 to a23 external bus cycle address signal output in external bus rd output wrl wrh CCC 1.1.2 non-port pins (1) bus control pins input/ alternate output function astb external bus cycle address strobe signal output in external bus external memory cycle data read strobe signal output in external bus external memory cycle lower byte data write strobe signal output in external bus external memory cycle upper byte data write strobe signal output in external bus ready input external bus cycle ready signal input in external bus dex external bus cycle upper byte data enable signal output output ras dram low address latch timing signal output d8/d16 input external bus data bus width selection signal input buslock output external bus bus lock signal output poll input of poll signal (sampled in poll instruction execution) input hldrq external bus hold request signal input hldak external bus hold acknowledge signal output output refrq refresh pulse signal output 3Cstate external bus cycle address/data multiplex signal input/output input/output in external bus 3Cstate output iord external i/o cycle data read strobe signal output output iowr external i/o cycle data write strobe signal output dmarq0 dma request signal input (channel 0) p80 input dmarq1 dma request signal input (channel 1) p81 dmaak0 dma acknowledge signal output (channel 0) dmaak1 dma acknowledge signal output (channel 1) output CCC tce0 dma termination signal output (channel 0) tce1 dma termination signal output (channel 1) 12 m pd70433 (2) other pins input/ alternate output function gnd gnd potential v dd positive power supply CCC av ss a/d converter gnd potential av dd a/d converter analog power supply av ref a/d converter reference voltage input CCC reset input system reset signal input x1 connection pins of crystal resonator/ceramic resonator for system clock generation. in case of external clock supply, input x2 CCC to x1 and leave x2 open. clkout internal system clock ? output output wdtout watchdog timer overflow signal output nmi non-maskable interrupt request input *1 p10 intp0 p11 intp1 p12 intp2 p13 input external interrupt request input *2 intp3 p14/ti intp4 p15 intp5 p16 ti external event clock input p14/intp3 pwm pwm output p20 to00, to01, to20, to21, to30 t x d0 uart transmission data output p30/sb0/so0 r x d0 input uart reception data input p31/sb1/si0 t x c output uart transmission clock output p32/sck0 cts0 p33 input uart transmission enable signal input cts1 p36/sck1 sb0 p30/t x d0/so0 input/output sbi transmission/reception data input/output sb1 p31/r x d0/si0 pin name function output timer unit output p21 to p25 *1. because nmi interrupt is unmaskable, nmi interrupt is always initiated by detecting a valid edge (when reading from port 1, the pin level is read). 2. by masking or disabling (ie = 0) these interrupts, these pins can be used as generalCpurpose input/output ports, respectively. 13 m pd70433 input/ alternate output function so0 p30/t x d0/sb0 output csi transmission data output so1 p34/t x d1 si0 p31/r x d0/sb1 input csi reception data input si1 p35/r x d1 sck0 p32/t x c csi serial clock input/output sck1 p36/cts1 pd0 to pd7 parallel interface data input/output p40 to p47 input/output datastb parallel interface data strobe signal p50 ack parallel interface acknowledge signal p51 busy parallel interface busy signal p52 ani0 to ani3 input analog input signal to a/d converter p60 to p63 rtp0 to rtp7 output real-time output port p70 to p77 pin name function 14 m pd70433 2. block configuration 2.1 bus control unit (bcu) the bcu performs control of the main bus. the bcu starts the necessary internal/external bus cycle on the basis of the physical address obtained from the execution unit (exu). 2.2 execution unit (exu) the exu controls address calculation, arithmetic and logical operations, data transfer, etc., by means of a microprogram (firmware for controlling the microsequencer on the basis of decoded op code). the exu contains 512 bytes of ram (corresponding to the register file space). 2.3 interrupt controller (intc) the intc services hardware interrupt requests generated by on-chip peripheral hardware and interrupt requests generated externally with vectored interrupts, bank switching, or macro service. it can also control the programmable 4- level interrupt priority order, and can also perform multiprocessing control for interrupt. 2.4 dma controller (dmac) the dmac is a general-purpose dma controller, capable of handling the 16m-byte memory space in a linear fashion. operating modes comprise memory-to-memory transfer mode, intelligent dma (ring buffer method and counter control method) mode, next address specification mode, and 2-channel operation. 2.5 uart/clocked serial interface (uart/csi) this block supports the asynchronous interface (uart) in which data synchronization is achieved by means of start/ stop bits, and the clocked serial interface (csi), allowing either to be used. for the clocked serial interface there is a further choice of serial bus interface mode (sbi) or 3-wire serial i/o mode. 2.6 parallel interface unit (piu) this performs input/output using strobe signal synchronization in 8-bit units, and supports the centronics interface and general-purpose parallel data communication functions. 2.7 a/d converter unit (8-bit a/d) this is an a/d converter with 4 analog inputs, and provided with 4 a/d conversion result registers. 2.8 timer/counter unit (tcu) the timer/counter unit incorporates a 16-bit timer/counter, and can be used as an interval timer, free-running counter, or event counter. 2.9 pwm (pulse width modulation) unit (pwm) an 8-bit precision pwm (pulse width modulation) signal output function. 2.10 watchdog timer (wdt) the wdt incorporates an 8-bit watchdog timer for detection of inadvertent program looping, system errors, etc. the wdtout pin is provided to give external notification of the generation of watchdog timer interrupts. 2.11 ports (port) 53 port pins are provided, allowing port pin and control pin functions to be selected. 2.12 real-time output port (rtop) this is a real-time output port which uses an interrupt from timer 0 as a trigger. it can output the contents of the 8-bit buffer register at programmable intervals in 4-bit or 8-bit units. 15 m pd70433 2.13 clock generator (cg) the cg generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the x1 and x2 pins and supplies it as the cpu operating clock. 2.14 software interval timer (sit) the sit incorporates a 16-bit software interval timer as a software timer function and watch function timer. interval interrupts can be set by input clock (count clock) selection and software timer/counter compare register setting. 16 m pd70433 3. cpu functions the cpu of the v55pi is software upword compatible with the v20 and v30 (native mode), and the v25 and v35. 3.1 features software upward compatible with v20 & v30 (native mode) and v25 & v35 (includes additional instructions) minimum instruction cycle: 160 ns/12.5 mhz (external 25 mhz clock) 125 ns/16 mhz (external 32 mhz clock) address space: 16m bytes 1m-byte basic memory (program) space 16m-byte extended memory (data) space register file space (in on-chip ram): 512 bytes/16 register banks i/o space: 64k bytes register configuration (compared with v20/v30 and v25/v35) internal 16-bit architecture, switchable external data bus width (16/8 bits) automatic wait control with memory divided in variable sizes (max. 6 blocks) ? programmable wait function ? wait function using ready pin refresh function ? automatic generation of refresh cycle (ras only) ras pin functions ras pin ? dram ras timing rd, wrh, wrl pins ? dram cas timing astb pin ? dram row/column address switching timing psw none ibrk ibrk item v20, v30 v25, v35 v55pi extended segment register none none ds2, ds3 register bank none 8 banks (in memory space) 16 banks (in register file space) mode flag md none none register bank flags none rb0 to rb2 rb0 to rb3 input/output instruction trap flag user flag none f0, f1 none 240 bytes 496 bytes special function register area none (memory mapping onto (memory mapping onto fff00h to fffefh) ffe00h to fffefh) 17 m pd70433 3.2 registers the v55pi cpu has general register sets compatible with the v20 and v30 (native mode), and the v25 and v35. the general register sets are mapped onto the register file space. these general register sets are also used as on-chip ram, and there can be a maximum of 16 register sets in bank form. in addition, the v55pi has various special function registers for controlling on-chip peripheral hardware. these special function registers are mapped onto memory space addresses 0ffe00h to 0fffefh. 3.2.1 register banks the general register sets are mapped onto the register file space (in on-chip ram). the general register sets are used in a bank arrangement; each bank consists of 32 bytes and up to 16 banks can be set. the cpu normally uses register bank 15 for program execution, and it is possible to switch to another bank automatically by means of maskable hardware interrupt or software interrupt (brkcs instruction). it is possible to return from the switched- to register bank to the original register bank by means of the instruction for returning from an interrupt (retrbi). the register bank configuration is shown in figure 3-1. the general register sets are mapped onto the area with an offset of (+08h) to (+1fh) from the start address of each register bank. the word address from the start in a register bank is the extended segment register (ds2) area. the vector pc/ds3 area is used to set the value to be loaded into the pc when the register bank is switched, that is, the offset value of the start address of the interrupt service routine. this area is al so used as the extended segment register (ds3) area. the psw save area is used to save the psw when the register bank is switched, and the pc save area is used to save the pc when the register bank is switched. after a reset, register bank 15 is selected automatically. also, segment register initialization after a reset is performed for register bank 15 only. the register file space onto which these general register sets are mapped can also be accessed as data memory by addition of a special prefix instruction (iram:) to a memory manipulation instruction. of the 16 set register banks, banks 0 and 1 have macro service channels (parameter and work area for macro service) allocated in duplicate. 18 m pd70433 figure 3-1. register bank configuration register file space (512 bytes) register bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (offset from the starting address of each register bank) ds2 bw bh +02h dh ch ah bl dl cl al dw cw aw 000h 020h 040h 060h 080h 0a0h 0c0h 0e0h 100h 120h 140h 160h 180h 1a0h 1c0h 1e0h 1ffh vector pc/ds3 psw save pc save +04h +06h +08h +0ah +0ch +0eh +10h +12h +14h +16h +18h +1ah +1ch +1eh ds0 ss ps ds1 iy ix bp sp +00h 15 87 0 19 m pd70433 3.2.2 general registers (aw, bw, cw, dw) there are four 16-bit general registers. in addition to being accessed as 16-bit registers, these registers can also be accessed as 8-bit registers by dividing each register into upper and lower 8-bit halves (ah, al, bh, bl, ch, cl, dh, dl). these registers are used as 8-bit or 16-bit registers with a wide range of instructions including transfer, arithmetic and logical operation instructions. each register is also used as the default register for specific instruction processing, as shown below. aw : word multiplication/division, word input/output, data conversion al : byte multiplication/division, byte input/output, bcd rotation, data conversion ah : byte multiplication/division bw : data conversion cw : loop control branch, repeat prefix cl : shift instructions, rotate instructions, bcd operations dw : word multiplication/division, indirect addressing input/output these registers are mapped onto the register file space (in on-chip ram). the address is the value obtained by adding the offset for each register to (register bank number 32). register offset register offset al 1eh aw 1eh ah 1fh bl 18h bw 18h bh 19h cl 1ch cw 1ch ch 1dh dl 1ah dw 1ah dh 1bh table 3-1. general register offsets 20 m pd70433 3.2.3 pointers (sp, bp) and index registers (ix, iy) these are 16-bit registers used as base pointers or index registers in memory accesses using based addressing (bp), indexed addressing (ix, iy), based indexed addressing (bp, ix, iy), etc. the sp is also used as the pointer in stack operations. as with general registers, these are used with transfer instructions, arithmetic operation instructions, etc., but in this case they cannot be used as 8-bit registers. each register is also used as the fixed address pointer for specific instruction processing, as shown below. sp : stack manipulation ix : block transfers, bcd operation source side address specification iy : block transfers, bcd operation destination side address specification these registers are mapped onto the register file space (in on-chip ram). the address is the value obtained by adding the offset for each register to (register bank number 32). table 3-2. pointer and index register offsets register offset sp 16h bp 14h ix 12h iy 10h 3.2.4 segment registers (ps, ss, ds0, ds1) the cpu manages the 1m-byte basic memory space by dividing it into 64k-byte units. the cpu specifies the start address of each segment with a segment register, and uses another register or effective address for the specification of phyiscal address, with the relative address from the start address as the offset. the physical address is created as shown below. segment register 4-bit fixed xxxx0h 0xxxxh xxxxxh + there are four segment registers: ps (program segment), ss (stack segment), ds0 (data segment 0), and ds1 (data segment 1). the respective segments are used in the following cases. ps : program fetch ss : stack manipulation instructions, addressing using bp as base register ds0 : general variable accesses, source block data accesses such as block transfer instructions, etc. ds1 : destination block data accesses such as block transfer instructions, etc. .... segment start address .... offset value ..... physical address (20 bits) 21 m pd70433 however, using a segment override prefix instruction makes it possible for access of general variables to change from ds0 to another segment register. also, in addressing which uses bp as the base register, another segment register can be used instead of ss. example mov aw, 1000h mov ds1 : aw mov bl, ds1, byte ptr [ix]; dsi : byte data read from ix when a reset is performed, ps of register bank 15 is initialized to ffffh, and ss, ds0 and ds1 are initialized to 0000h. these registers are mapped onto the register file space (in on-chip ram). the address is the value obtained by adding the offset for each register to (register bank number 32). table 3-3. segment register offsets register offset ds0 08h ds1 0eh ss 0ah ps 0ch 3.2.5 extended segment registers (ds2, ds3) in addition to the segment registers for accessing the 1m-byte basic memory space, the v55pi is provided with extended segment registers which specify the start address of each 64k-byte segment of the 16m-byte extended memory space. there are two extended segment registers, ds2 (data segment 2) and ds3 (data segment 3), which are used as shown below. ds2: extended memory space general variable accesses (by segment override prefix instructions), source block data accesses in extended memory space block transfer instructions, etc. ds3: extended memory space general variable accesses (by segment override prefix instructions), destination block data accesses in extended memory space block transfer instructions, etc. the data access using an extended semgnet register is performed by using the segment override prefix. especially, in the block transfer instruction, ds2 and ds3 can be specified simultaneously by segment override prefix. (in this case, the order for ds2 and ds3 is optional.) example rep ds2: ds3: movbkw ; word memory block transfer from ds2 : ix to ds3 : iy. the cpu specifies the start address of each segment with an extended segment register, and performs an access by using another register or effective address for the specification of physical address, with the relative address from the start address as the offset value. the physical address is created as shown in the next page. 22 m pd70433 extended segment register 8-bit fixed ... segment start address ... offset value ... physical address (24 bits) when a reset is performed, ds2 and ds3 of register bank 15 are initialized to 0000h. these registers are mapped onto the register file space (in on-chip ram). the address is the value obtained by adding the offset for each register to (register bank number 32). table 3-4. extended segment register offsets register offset ds2 00h ds3 02h (also used as vectored pc) 3.2.6 special function registers (sfr) the v55pi has a group of registers with the function of controlling on-chip peripheral hardware. a number of registers are provided according to the type of cotrol for each peripheral hardware unit, and the actual operation can be set using the individual bits in the registers. these registers are mapped onto the memory space, and are read and written to using the same method as for ordinary memory (see 3.5.3 "special function register area" ). example mov aw, 0ffe0h mov ds1, aw mov bl, ds1 : byte ptr [1efh]; 0ffe0h : 1efh (prc register) read there are also two instructions, btclr and btclrl, which are only valid for special function registers. of these, btclrl is an instruction newly provided in the v25 or v35. the btclr instruction is valid for registers in the upper 240 bytes (0fff00h to 0fffefh) of the special function register area, and the btclrl instruction is valid for registers in the lower 256 bytes (0ffe00h to 0ffeffh). xxxx00h 00xxxxh xxxxxxh + 23 m pd70433 3.3 program counter (pc) this is a 16-bit binary counter which holds the offset value of the program memory address on which the cpu is to perform execution. the pc is incremented each time an instruction code is fetched from the instruction queue, and is also loaded with the new location address value when a branch, call, return or break instruction is executed. when a reset is performed, 0000h is loaded into the pc. because the ps register is initialized to ffffh in a reset, after a reset the cpu begins execution at physical address 0ffff0h. 3.4 program status words (psw) the psw consists of 6 status flags and 5 control flags. ? status flags ? v (overflow) ...overflow detection flag ? s (sign) ...sign bit detection flag ? z (zero) ...all zero detection flag ? ac (auxiliary carry) ...4-bit carry/borrow detection flag ? p (parity) ...parity detection flag ? cy (carry) ...carry/borrow detection flag ? control flags ? rb0 to rb3 (register banks 0 to 3) ...register bankspecification flags ? dir (direction) ...block transfer/input/output instruction direction control flag ? ie (interrupt enable) ...interrupt enabled state control flag ? brk (break) ...single-step interrupt control flag ? ibrk (i/o break) ...input/output instruction trap control flag the status flags are set (1) or reset (0) automatically according to the result (data value) of execution of various kinds of instructions. the cy flag can be directly set, reset or inverted by an instruction. the control flags are set or reset by instructions, and control the operation of the cpu. the ie and brk flags are always reset when interrupt servicing is initiated. the contents of the psw can be saved to and restored from the stack by the push and pop instructions. however, when the contents are restored by the pop psw instruction, bits 12 to 15 (rb0 to rb3) are not returned to the psw. the low-order 8 bits of the psw can also be saved to or restored from the ah register by an mov instruction. the psw bit configuration is shown below. rb3 rb2 rb1 rb0 y dir ie brk s z 0 ac 0 p ibrk cy 15141312111098 7654 3210 24 m pd70433 3.5 memory space the v55pi has a 16m-byte memory space. of this, using lowest 1m bytes (000000h to 0fffffh) as the basic memory space, the 16m bytes including the basic memory space (000000h to ffffffh) can be accessed as the extended memory space. the basic memory space can be accessed using the segment registers (ps, ss, ds0, ds1) in the same way as in the v25 and v35. the extended memory space can be accessed using the extended segment registers (ds2, ds3), and has the basic memory space mapped onto the lowest 1m bytes. see 3.2.4 "segment registers (ps, ss, ds0, ds1)" and 3.2.5 "extended segment registers (ds2, ds3)" for the physical addresses. the 496-byte space 0ffe00h to 0fffefh has mapped onto it a group of registers to which specific functions are allocated such as on-chip peripheral hardware registers, control registers, etc., and these are manipulated by memory accesses. in addition, independent of these, there is a 512-byte register file space (in on-chip ram). in addition to being accessed by using register manipulation instructions as in the v25 and v35, the register file space can also be accessed as data memory by adding a special prefix instruction (iram:) to a memory manipulation in. figure 3-2. memory space 3.5.1 basic memory space the memory space comprises a 1m-byte basic memory space and 16m-byte extended memory space. the basic memory space is mapped onto the lowest 1m bytes (000000h to 0fffffh) of the extended memory space. the 1m-byte basic memory space is shown in figure 3-3. conditions for accessing the basic memory space by software are the same as for the v20/v30 and v25/v35. a basic memory space physical address is specified by the segment start address indicated by the segment register (ps, ss, ds0, ds1) and the offset value from the segment start position indicated by another register or immediate data. the basic memory space has the vectored interrupt vector area and special function register area mapped onto it. for an area in which special function registers are mapped, data accesses cannot be made to external memory (program fetches are possible.) 000000h 0fffffh 100000h ffffffh 003ffh ffe00h fffefh basic memory space (1m bytes) vector area extended memory space (16m bytes) special function register area (on-chip area) 25 m pd70433 figure 3-3. basic memory space 0fff0h to 0fffffh is a program area used for the system boot, and ps and pc become 0fffh and 0h, respectively, therefore the program execution starts from 0ffff0h. 3.5.2 extended memory space the 16m-byte extended memory space is shown in figure 3-4. the only accesses that can be performed on the extended memory space are data accesses. the basic memory space is mapped onto the lowest 1m bytes (000000h to 0fffffh) of the extended memory space, and can be accessed using the segment registers ps, ss, ds0 and ds1. data accesses can be performed in the extended memory space using the extended segment registers ds2 and ds3. with ds2 and ds3 it is possible to use a specification as a segment override prefix instruction added to a memory manipulation instruction. an extended memory space physical address is specified by the segment start address indicated by the extended segment register and the offset value from the segment start position indicated by another register or immediate data. if the generated address indicates the lowest 1m-byte area (000000h to 0fffffh), the basic memory space is accessed. vector area spaecial function register area (internal area) 000000h 0fffffh 00000h 003ffh ffe00h fffefh 1m bytes 26 m pd70433 figure 3-4. extended memory space vector area spaecial function register area (internal area) 0fffffh 00000h 003ffh ffe00h fffefh 100000h 000000h ffffffh 1m bytes 16m bytes 3.5.3 special function register area the 496-byte space 0ffe00h to 0fffefh has mapped onto it a group of registers to which functions such as on-chip peripheral hardware operation specification, status monitoring, etc., are assigned. program fetches cannot be performed from these areas. special function register manipulation is performed by accesses by means of memory manipulation instructions. if the special function register area is accessed, rd, wrh, wrl, iord, iowr and other control signals do not become active. a list of special function registers is given in table 3-5. the meaning of the items in the table is explained below. ? symbol ............................ the symbol used to indicate the special function register name. corresponds to the operand description format (symbol name) in a memory manipulation instruction. ? r/w ................................. indicates whether this special function register is read/write enabled. r/w : read/write enabled r : read only w : write only ? manipulation method ..... indicates which of the following can be used on the register: bit manipulation, 8-bit manipulation, 16-bit manipulation, 32-bit manipulation. ? reset ............................ indicates the status of the register after reset input. note addresses which are not listed are the reserved area, therefore, they should not be accessed by the user program. 27 m pd70433 mk0 mk1 *1. varies according to input/output mode. 2. some bits r, others r/w (possible). address special function register name symbol r/w after reset table 3-5. special function registers (1/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0ffe00h a/d conversion result register 0 adcr0 r ? undefined 0ffe02h a/d conversion result register 1 adcr1 r ? undefined 0ffe04h a/d conversion result register 2 adcr2 r ? undefined 0ffe06h a/d conversion result register 3 adcr3 r ? undefined 0ffe10h parallel interface buffer pad r/w *1 ? undefined 0ffe18h parallel interface control register 0 pac0 r/w ?? 90h 0ffe19h parallel interface control register 1 pac1 r/w ?? 03h 0ffe1ah parallel interface status register pas r/w *2 ? 40h 0ffe1ch parallel interface acknowledge interval register 1 pai1 w ? undefined 0ffe1dh parallel interface acknowledge interval register 2 pai2 w ? undefined 0ffe20h a/d converter mode register adm r/w ?? 00h 0ffec0h interrupt mask flag register 0 (low) mk0l r/w ?? ? ffh 0ffec1h interrupt mask flag register 0 (high) mk0h r/w ?? ffh 0ffec2h interrupt mask flag register 1 (low) mk1l r/w ?? ? ffh 0ffec3h interrupt mask flag register 1 (high) mk1h r/w ?? ffh 0ffec4h in-service priority register ispr r ?? 00h 0ffec5h interrupt mode control register imc r/w ? 80h 0ffec9h interrupt request control register 09 ic09 r/w ?? 43h 0ffecah interrupt request control register 10 ic10 r/w ?? 43h 0ffecbh interrupt request control register 11 ic11 r/w ?? 43h 0ffecch interrupt request control register 12 ic12 r/w ?? 43h 0ffecdh interrupt request control register 13 ic13 r/w ?? 43h 28 m pd70433 address special function register name symbol r/w after reset table 3-5. special function registers (2/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0ffeceh interrupt request control register 14 ic14 r/w ?? 43h 0ffed0h interrupt request control register 16 ic16 r/w ?? 43h 0ffed1h interrupt request control register 17 ic17 r/w ?? 43h 0ffed2h interrupt request control register 18 ic18 r/w ?? 43h 0ffed3h interrupt request control register 19 ic19 r/w ?? 43h 0ffed4h interrupt request control register 20 ic20 r/w ?? 43h 0ffed5h interrupt request control register 21 ic21 r/w ?? 43h 0ffed6h interrupt request control register 22 ic22 r/w ?? 43h 0ffed7h interrupt request control register 23 ic23 r/w ?? 43h 0ffed8h interrupt request control register 24 ic24 r/w ?? 43h 0ffed9h interrupt request control register 25 ic25 r/w ?? 43h 0ffedah interrupt request control register 26 ic26 r/w ?? 43h 0ffedbh interrupt request control register 27 ic27 r/w ?? 43h 0ffedch interrupt request control register 28 ic28 r/w ?? 43h 0ffeddh interrupt request control register 29 ic29 r/w ?? 43h 0ffedeh interrupt request control register 30 ic30 r/w ?? 43h 0ffedfh interrupt request control register 31 ic31 r/w ?? 43h 0ffee0h interrupt request control register 32 ic32 r/w ?? 43h 0ffee4h interrupt request control register 36 ic36 r/w ?? 43h 0ffee5h interrupt request control register 37 ic37 r/w ?? 43h 0fff00h port 0 p0 r/w ?? undefined 0fff01h port 1 p1 r ?? undefined 0fff02h port 2 p2 r/w ?? undefined 0fff03h port 3 p3 r/w ?? undefined 29 m pd70433 address special function register name symbol r/w after reset table 3C5. special function registers (3/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0fff04h port 4 p4 r/w ?? undefined 0fff05h port 5 p5 r/w ?? undefined 0fff06h port 6 p6 r ?? undefined 0fff07h port 7 p7 r/w ?? undefined 0fff08h port 8 p8 r/w ?? undefined 0fff0ch port read control register prdc r/w ?? 00h 0fff0eh realCtime output port rtp r/w ?? undefined 0fff10h port 0 mode register pm0 r/w ?? ffh 0fff12h port 2 mode register pm2 r/w ?? ffh 0fff13h port 3 mode register pm3 r/w ?? ffh 0fff14h port 4 mode register pm4 r/w ?? ffh 0fff15h port 5 mode register pm5 r/w ?? ffh 0fff17h port 7 mode register pm7 r/w ?? ffh 0fff18h port 8 mode register pm8 r/w ?? ffh 0fff22h port 2 mode conrol register pmc2 r/w ?? 00h 0fff23h port 3 mode control register pmc3 r/w ?? 00h 0fff24h port 4 mode control register pmc4 r/w ?? 00h 0fff25h port 5 mode control register pmc5 r/w ?? 00h 0fff27h port 7 mode control register pmc7 r/w ?? 00h 0fff28h port 8 mode control register pmc8 r/w ?? 00h 0fff2ch realCtime output port control register rtpc r/w ?? 40h 0fff2dh realCtime output port delay specification register rtpd r/w ?? undefined 0fff2eh port 7 buffer (low) p7l r/w ?? undefined 0fff2fh port 7 buffer (high) p7h r/w ?? undefined 30 m pd70433 table 3-5. special function registers (4/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0fff30h timer control register 0 tmc0 r/w ?? ? 00h 0fff31h timer control register 1 tmc1 r/w ?? 00h 0fff32h timer output control register 0 toc0 r/w ?? ? 00h 0fff33h timer output control register 1 toc1 r/w ?? 00h 0fff34h external interrupt mode register 0 intm0 r/w ?? ? 00h 0fff35h external interrupt mode register 1 intm1 r/w ?? 00h 0fff40h timer register 0 tm0 r/w ? 00h 0fff42h timer register 1 tm1 r/w ? 00h 0fff44h timer register 2 tm2 r/w ? 00h 0fff46h timer register 3 tm3 r/w ? 00h 0fff48h timer capture register 00 ct00 r/w ? undefined 0fff4ah timer capture register 01 ct01 r/w ? undefined 0fff4ch timer compare register 00 cm00 r/w ? undefined 0fff4eh timer compare register 01 cm01 r/w ? undefined 0fff50h timer capture register 10 ct10 r/w ? undefined 0fff52h timer compare register 10 cm10 r/w ? undefined 0fff54h timer compare register 11 cm11 r/w ? undefined 0fff58h timer compare register 20 cm20 r/w ? undefined 0fff5ah timer compare register 21 cm21 r/w ? undefined 0fff5ch timer compare register 22 cm22 r/w ? undefined 0fff5eh timer compare register 23 cm23 r/w ? undefined 0fff60h watchdog timer mode register wdm r/w * ?? 00h 0fff64h timer compare register 30 cm30 r/w ? undefined address special function register name symbol r/w after reset intm * wdt can only be written to by the rstwdt instruction (8-bit unit only). 31 m pd70433 address special function register name symbol r/w after reset tc0 *1. some bits r, others r/w. 2. r or w in bit units. remark ( ): depends on the mode. table 3-5. special function registers (5/7) manipulable bit units 1 bits 8 bits 16 bits 32 bits 0fff66h timer compare register 31 cm31 r/w ? undefined 0fff6ch pwm register pwm r/w ?? 00h 0fff6dh pwm control register pwmc r/w ?? 00h 0fff70h transmit baud rate generator register 0 t x brg0 r/w ?? undefined 0fff71h receive baud rate generator register 0 r x brg0 r/w ?? undefined 0fff72h prescaler register 0 prs0 r/w ?? 00h 0fff73h uart mode register 0 / clocked serial interface mode register 0 uartm0/csim0 r/w ( ? ) ? 00h 0fff74h uart status register 0 / sbi control register 0 uarts0/sbic0 *1 / *2 ( ? ) ? 00h 0fff75h uart transmit buffer 0 / clocked serial i/o shift register 0 t x b0/sio0 w ? undefined 0fff76h receive buffer 0 r x b0 r ? undefined 0fff78h transmit baud rate generator register 1 t x brg1 r/w ?? undefined 0fff79h receive baud rate generator register 1 r x brg1 r/w ?? undefined 0fff7ah prescaler register 1 prs1 r/w ?? 00h 0fff7bh uart mode register 1 / clocked serial interface mode register 1 uartm1/csim1 r/w ( ? ) ? 00h 0fff7ch uart status register 1 uarts1 *1 / *2 ( ? ) ? 00h 0fff7dh uart transmit buffer 1 / clocked serial i/o shift register 1 t x b1/sio1 w ? undefined 0fff7eh receive buffer 1 r x b1 r ? undefined 0fff7fh protocol selection register asp r/w ?? 00h 0fff80h terminal counter 0 (low) tc0l r/w ? ? undefined 0fff82h terminal counter 0 (high) tc0h r/w ?? undefined 32 m pd70433 address special function register name symbol r/w after reset tc1 tcm1 udc1 dcm1 mar1 tcm0 udc0 dcm0 mar0 dptc0 * bit clear operation possible. table 3-5. special function registers (6/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0fff84h terminal counter modulo register 0 (low) tcm0l r/w ? ? undefined 0fff86h terminal counter modulo register 0 (high) tcm0h r/w ?? undefined 0fff88h dma up/down counter 0 (low) udc0l r/w ? ? undefined 0fff8ah dma up/down counter 0 (high) udc0h r/w ?? undefined 0fff8ch dma compare register 0 (low) dcm0l r/w ? ? undefined 0fff8eh dma compare register 0 (high) dcm0h r/w ?? undefined 0fff90h dma memory address register 0 (low) mar0l r/w ? ? undefined 0fff92h dma memory address register 0 (high) mar0h r/w ?? undefined 0fff94h dma read/write pointer 0 (low) dptc0l r/w ? ? undefined 0fff96h dma read/write pointer 0 (high) dptc0h r/w ?? undefined 0fff9ch dma mode register 0 dmam0 r/w ?? e0h 0fff9dh dma control register 0 dmac0 r/w ?? 00h 0fff9eh dma status register dmas r/w ? * ? 00h 0fffa0h terminal counter 1 (low) tc1l r/w ? ? undefined 0fffa2h terminal counter 1 (high) tc1h r/w ?? undefined 0fffa4h terminal counter modulo register 1 (low) tcm1l r/w ? ? undefined 0fffa6h terminal counter modulo register 1 (high) tcm1h r/w ?? undefined 0fffa8h dma up/down counter 1 (low) udc1l r/w ? ? undefined 0fffaah dma up/down counter 1 (high) udc1h r/w ?? undefined 0fffach dma compare register 1 (low) dcm1l r/w ? ? undefined 0fffaeh dma compare register 1 (high) dcm1h r/w ?? undefined 0fffb0h dma memory address register 1 (low) mar1l r/w ? ? undefined 0fffb2h dma memory address register 1 (high) mar1h r/w ?? undefined 33 m pd70433 address special function register name symbol r/w after reset dptc1 *1 the sfb bit of the standby control register can be set (1) by instruction, but cannot be cleared (0). (only '1' can be written .) *2 after power-on reset: 00h, otherwise: no change table 3-5. special function registers (7/7) manipulable bit units 1 bit 8 bits 16 bits 32 bits 0fffb4h dma read/write pointer 1 (low) dptc1l r/w ? ? undefined 0fffb6h dma read/write pointer 1 (high) dptc1h r/w ?? undefined 0fffbch dma mode register 1 dmam1 r/w ?? e0h 0fffbdh dma control register 1 dmac1 r/w ?? 00h 0fffe0h software timer/counter stc r ? undefined 0fffe2h software timer/counter compare register stmc r/w ? ffffh 0fffe8h programmable wait control register 0 pwc0 r/w ?? eah 0fffe9h programmable wait control register 1 pwc1 r/w ?? aah 0fffeah memory block control register mbc r/w ?? fch 0fffech refresh mode register rfm r/w ?? 77h 0fffeeh standby control register stbc r/w *1 ?? undefined *2 0fffefh processor control register prc r/w ?? eeh 34 m pd70433 3.5.4 vector table area the 1kCbyte area 00000h to 003ffh in the memory space holds 256 vectors (4 bytes used per vector) for the start addresses of interrupt routines initiated by interrupt requests, break instructions, etc. in the initial state, vectors 0 to 47 are reserved as v55pi family dedicated on-chip peripheral and software interrupt vectors. for vectors 8 to 47, the vector address of hardware interrupts except nmi can be changed by means of bits v0 and v1 of the interrupt mode control register (imc). vector 0 (00000h) : divide error vector 1 (00004h) : single step vector 2 (00008h) : nmi instruction vector 3 (0000ch) : brk 3 instruction vector 4 (00010h) : brkv instruction vector 5 (00014h) : chkind instruction vector 6 (00018h) : input/output instruction vector 7 (0001ch) : fpo instruction/exception trap when v1 = v0 = 0 : vector 8 (00020h) : intwdt vector 9 (00024h) : intp0 vector 10 (00028h) : intp1 vector 11 (0002ch) : intp2 vector 12 (00030h) : intp3 vector 13 (00034h) : intp4 vector 14 (00038h) : intp5 vector 15 (0003ch) : system reserved vector 16 (00040h) : intcm00 vector 17 (00044h) : intcm01 vector 18 (00048h) : intcm10 vector 19 (0004ch) : intcm11 vector 20 (00050h) : intcm21 vector 21 (00054h) : intcm31 vector 22 (00058h) : intd0 dma#0_main vector 23 (0005ch) : intd0s dma#0_sub vector 24 (00060h) : intd1 dma#1_main vector 25 (00064h) : intd1s dma#1_sub vector 26 (00068h) : intser0 vector 27 (0006ch) : intser1 vector 28 (00070h) : intsr0/intcsi0 vector 29 (00074h) : intsr1/intcsi1 vector 30 (00078h) : intst0 vector 31 (0007ch) : intst1 vector 32 (00080h) : intsit vector 33 (00084h) : system reserved vector 34 (00088h) : system reserved vector 35 (0008ch) : system reserved vector 36 (00090h) : intpai vector 37 (00094h) : intad vector 38 (00098h) : system reserved vector 39 (0009ch) : system reserved 35 m pd70433 vector 40 (000a0h) : system reserved vector 41 (000a4h) : system reserved vector 42 (000a8h) : system reserved vector 43 (000ach) : system reserved vector 44 (000b0h) : system reserved vector 45 (000b4h) : system reserved vector 46 (000b8h) : system reserved vector 47 (000bch) : system reserved when v1 = 0, v0 = 1 : vector 72 (00120h) : intwdt vector 73 (00124h) : intp0 ?? ? ?? ? ?? ? vector 110 (001b8h) : system reserved vector 111 (001bch) : system reserved when v1 = 1, v0 = 0 : vector 136 (00220h) : intwdt vector 137 (00224h) : intp0 ?? ? ?? ? ?? ? vector 174 (002b8h) : system reserved vector 175 (002bch) : system reserved when v1 = 1, v0 = 1 : vector 200 (00320h) : intwdt vector 201 (00324h) : intp0 ?? ? ?? ? ?? ? vector 238 (003b8h) : system reserved vector 239 (003bch) : system reserved 36 m pd70433 3.6 register file space the register file space is shown in figure 3-5. the size of the register file space is 512 bytes, and a maximum 16-bank register set can be set. the register file space is separate from the memory space, and in addition to accesses using a register manipulation instruction as with the v25 and v35, the register file space can be accessed as data memory by adding a special prefix instruction (iram:) to a memory manipulation instruction. (access is performed asynchronously independently of the external bus cycle. when the iram: prefix instruction is added to a memory manipulation instruction, the cpu performs a data access with the lowCorder 9 bits of the memory address offset value as the register file address. in this case, segment register and physical address addition is not performed, and an external bus cycle is not initiated. example label1: mov iram : [0024h], aw ..... <1> mov [0056h], bw ..... <2> <1> this shows the case where data is transferred to the register file space using an "iram:" prefix instruction. the aw register value is stored in address 24h of the register file. <2> this shows the case where an instruction for data transfer to the memory space is used. if the iram prefix instruction is added to the primitive block transfer instruction and bcd operation instruction, which specify the source block and destination block, it becomes effective for the destination block. also, the macro service conrol word area (008h to 03fh), the macro service work area (000h to 007h), and the area used by the macro service channel (008h to 0ffh) are allocated in overlapping fashion in the file space. if a specific macro service which requires work area (rtoptrn) is not used, these work areas can be used as data space. 37 m pd70433 figure 3-5. register file space register bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 15 87 0 ds2 vector pc/ds3 psw save pc save ds0 ss ps ds1 iy ix bp sp bw dw cw aw bh dh ch ah bl dl cl al +02h +04h +06h +08h +0ah +0ch +0eh +10h +12h +14h +16h +18h +1ah +1ch +1eh 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 1ffh ( offset from the startin g address of each re g ister bank ) 0 2 4 6 8 a c e 0 2 4 6 8 a c e 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 macro service work area macro service control word area macro service channel area 000h 008h 03fh 0ffh +00h 38 m pd70433 3.7 i/o space the v55pi has a 64k-byte i/o space. the i/o space map is shown in figure 3-6. the i/o space is accessed using address bus/data bus and control signals (iord, iowr, etc). 0 is output from the unused high-order 8 bits of the address bus. wait cycles can be inserted in an i/o cycle by software and the ready pin. the area ff80h to ffffh of the i/o space is a reserved area, in which two v55pi on-chip peripheral dma input/output read/write pointers (iop) are allocated. the address of iop0 is ff94h, and the address of iop1 is ffb4h. when the cpu executes an input/output instruction with an iop address as an operand, the dma controller performs a read/write of data in the dma controller transfer buffer, with the iop contents as the address value, and increments (or decrements) the iop value automatically in accordance with the contents of the dma control register. therefore, data written by the dma controller can be referenced by an input/output instruction, and conversely, data written by an input/output instruction can be transferred by the dma controller. figure 3-6. i/o map (64k bytes) remark iopn corresponds to the dma read/write pointer (dptcn). 0000h ff80h ff94h ffb4h ffffh reserved area iop 0 iop 1 : : 39 m pd70433 4. bus control functions with the v55pi pin, refer to 1.1.2 (1) "pin function for bus control" . as regards pins which have an alternate function as port pins, when that function is used, the corresponding function must be selected by means of the port mode control register (pmcn). 4.1 wait function the v55pi divides the basic memory space (000000h to 0fffffh) into a maximum of 4 blocks with a variable memory size, divides the uppermost extended memory space area (100000h to ffffffh) into two areas with a variable memory size, and performs wait control for each block. the memory size of each block in the basic memory space is specified by the memory block control register (mbc). figure 4-1 shows the memory block configuration when a9h has been set for the mbc register value. figure 4-1. partitioned memory control mb31 00 00 11 00 01 11 00 01 10 11 main memory space mbc block 0 block 1 block 2 block 3 block 4 128k bytes 256k bytes 512k bytes 640k bytes 768k bytes 896k bytes 1m bytes 2m bytes 4m bytes 6m bytes 8m bytes 10 01 10 01 10 11 block 5 16m b y tes 1 mb30 0 mb21 1 mb20 0 mb11 1 mb10 1 mb01 0 mb00 1 40 m pd70433 figure 4-2. memory wait control 76543210 (block3) (block2) (block1) (block0) pwc1 dw31 dw30 dw21 dw20 dw11 dw10 dw01 dw00 76543210 (block4) (block1) (i/o space) (block5) (block4) pwc0 aw1 aw0 iow1 iow0 dw51 dw50 dw41 dw40 data wait (dw, iow) dwn1/iow1 dwn0/iow0 wait state 000 *1 011 *2 102 *2 113 *2 *1. ready signal is ignored. 2. additional control by means of ready signal is also possible. address wait (aw) awn wait state 0 not inserted (block 1) aw0 1 inserted (block 1) 0 not inserted (block 4) aw1 1 inserted (block 4) 41 m pd70433 4.2 refresh function the following functions are provided to refresh dram and pseudo-sram. ? function to insert periodically a refresh cycle in a series of bus cycles ? refresh address output function to refresh dram and pseudo-sram ? function to generate a refresh cycle in hold mode and halt mode. ? function to insert a wait state in a refresh cycle 4.2.1 refresh mode register (rfm) the rfm register is an 8-bit register to control refresh operation. a refresh cycle can be selected from the time base counter output tap. while a refresh request is held by another bus cycle if the next refresh request is generated, only the latter is valid. the rfm register value after a reset is 77h. 4.2.2 wait control in refresh cycle a wait state can be inserted in a refresh cycle. the specified number of wait states is inserted for memory block 4 by the programmable wait control register (pwc0) or ready pin. 4.2.3 refresh address bus pins ad0 to ad15 and a16 to a19 are activated in a refresh cycle. for each refresh cycle, the count is performed in one-address increments from x00000 to x1fffff in the case of the external 8-bit bus width, and in two-address increments from x00001h to xfffff in the case of the external 16-bit bus width (the minimum address is returned to after the maximum address). after initialization by a reset, count-up is started from x00000h in the case of the external 8-bit bus width and x00001h in the case of the external 16-bit bus width. in the case of the external 16-bit bus width, the refresh address minimum address bit (a0) is fixed at 1 and the dex pin output is also fixed at 1. a20 to a23 are undefined in a refresh cycle. 42 m pd70433 5. interrupt functions the v55pi incorporates a powerful interrupt controller (intc) which controls multiple-interrupt servicing for a total of 25 maskable hardware interrupt requests: 19 internal and 6 external. the interrupt controller controls multiple-interrupt servicing based on programmable priority. the following functions are provided as interrupt servicing modes: vectored interrupt function, macro service function, register bank switching function. 5.1 features v55pi interrupt functions offer the following features: comprehensive servicing states for interrupt requests ? vectored interrupt function : branch to interrupt service routine specified by vector table ? register bank switching function : high-speed interrupt response by automatic register bank switching ? macro service function : high-speed interrupt servicing by microprogram (firmware) 4-level programmable priority order control interrupt multiprocessing control according to the priority rich variety of macro service functions (following 7 modes) closely tied to v55pi on-chip peripheral hardware evtcnt : event count processing blktrs : data transfer between special function register and external memory buffer blktrs-c : data transfer between special function register and external memory buffer (with transfer data detection function) dtacmp : special function register status detection dtadif : time measurement by timer capture function rtoptrn : automatic control of real-time output port dtacmp-m : data transfer between external i/o and memory 7 external interrupt request inputs (nmi, intp0 to intp5) maskable interrupt requests are individually maskable. a list of interrupt sources is given in table 5-1. 43 m pd70433 interrupt register macro service request bank control word signal switching address interrupt request control register table 5-1. interrupt sources (1/2) interrupt source default interrupt default vector vectored macro classification priority generating generating table address service source unit number 1 nmi nmi pin input CCC 2 00008h no no nonmaskable CC CC 2 wdt watchdog timer overflow wdt 8 00 20h no no 3 intp0 ic9 intp0 pin input 9 00 24h yes yes 012h 4 intp1 ic10 intp1 pin input 10 00 28h yes yes 014h 5 intp2 ic11 intp2 pin input 11 00 2ch yes yes 016h external 6 intp3 ic12 intp3 pin input 12 00 30h yes yes 018h 7 intp4 ic13 intp4 pininput 13 00 34h yes yes 01ah 8 intp5 ic14 intp5 pin input 14 00 38h yes yes 01ch 9 intcm00 ic16 cm00 match detection 16 00 40h yes yes 020h 10 intcm01 ic17 cm01 match detection 17 00 44h yes yes 022h maskable 11 intcm10 ic18 cm10 match detection 18 00 48h yes yes 024h timer 12 intcm11 ic19 cm11 match detection 19 00 4ch yes yes 026h 13 intcm21 ic20 cm21 match detection 20 00 50h yes yes 028h 14 intcm31 ic21 cm31 match detection 21 00 54h yes yes 02ah 15 intd0 ic22 dma channel 0_main 22 00 58h yes yes 02ch 16 intd0s ic23 dma channel 0_sub 23 00 5ch yes yes 02eh dma 17 intd1 ic24 dma channel 1_main 24 00 60h yes yes 030h 18 intd1s ic25 dma channel 1_sub 25 00 64h yes yes 032h 44 m pd70433 * indicates that the value is variable in the range 0 to 255 (0 to ffh). remarks " " indicates that the value is determined by the v0 and v1 bits of the imc register . interrupt register macro service request bank control word signal switching address interrupt request control register table 5-1. interrupt sources (2/2) interrupt sourse default interrupt default vector vectored macro classification priority generating generating table address service source unit number 19 intser0 ic26 uart reception error (ch0) 26 00 68h no yes 034h 20 intser1 ic27 uart reception error (ch1) 27 00 6ch no yes 036h intsr0/ uart reception (ch0)/ yes yes 21 ic28 28 00 70h 038h intcsi0 serial transmission/reception (ch0) yes yes serial i/f intsr1/ uart reception (ch1)/ yes yes 22 ic29 29 00 74h 03ah maskable intcsi1 ldma channel 5 yes yes 23 intst0 ic30 uart transmission (ch0) 30 00 78h yes yes 03ch 24 intst1 ic31 uart transmission (ch1) 31 00 7ch yes yes 03eh 25 intsit ic32 stm match detection sit 32 00 80h no yes CC 26 intpai ic36 parallel i/f parallel i/f 36 00 90h yes yes CC 27 intad ic37 a/d converter a/d converter 37 00 94h yes yes 008h divide error 0 00000h no no brk flag (single-step) 1 00004h no no brk3 instruction 3 0000ch no no brkv instruction 4 00010h no no software chkind instruction 5 00014h no no CC CC CC CC CC input/output instruction (ibrk flag) 6 00018h no no brk imm8 * 00 * hno no brkcs instruction CC CC no yes fp0 instruction/ exception 7 0001ch no no trap exception trap 45 m pd70433 5.2 interrupt response methods the v55pi has three interrupt response methods: a vectored interrupt function, register bank switching function, and macro service function. in the case of a maskable interrupt request, one of these functions can be selected by means of the interrupt request control register (ic ) for each interrupt source according to the purpose of the interrupt. the on-chip interrupt controller handles interrupt requests according to the set response method. 5.2.1 vectored interrupts a vectored interrupt can only be acknowledged in the interrupt enabled state (ei state). when a vectored interrupt is acknowledged, the cpu enters the interrupt disabled state (di state), and the current psw contents and pc and ps contents are saved to the stack. then the corresponding vector is selected from the vector table, and the interrupt service routine is started at the address indicated by that vector. vector numbers are fixed for each interrupt source. in the di state, interr upts are held pending, and are acknowledged when the ei state is set again. the return from the interrupt is performed by an reti instruction. in the case of a hardware interrupt other than a non- maskable interrupt, an fint instruction must be executed before the return instruction. when a return is made from an interrupt, the pc, ps and psw are restored from the stack. figure 5-1. interrupt acknowledge operation (performed in sequence <1> ? <4>) psw ps pc vector table stack sp ?6 sp ?4 sp ?2 n: vector number n 4 n 4 + 2 <4> <2> sp ? sp ?6 <1> <3> ie = 0 brk = 0 46 m pd70433 5.2.2 register bank switching function in the v55pi, general register sets are mapped onto on-chip ram, and register sets can be held in up to 16 banks. interrupt servicing is performed by automatically switching the register bank when a brkcs or tsksw instruction is executed or when an interrupt is responded to. because saving of registers to the stack previously performed by software is not required, high-speed switching of the program execution environment is possible. the register bank switching sequence is performed as follows (see figure 5-2 ). <1> the contents of psw is saved to temporary register. <2> the register bank is switched. <3> ie and brk are set to 0. <4> the contents of psw which is saved to the pc and the temporary register are saved to the saving area, respectively. <5> the interrupt service routine start address offset value is loaded from the vector pc area in the register bank to pc. figure 5-2. register bank switching sequence (in case of register bank switching by interrupt) old register bank aw cw dw bw sp bp ix iy ds1 ps ss ds0 pc save psw save vector pc/ds3 ds2 new register bank for interrupt servicing aw cw dw bw sp bp ix iy ds1 ps ss ds0 pc save psw save vector pc/ds3 ds2 psw pc temporary register <2> register bank switching <3> ie = 0, brk = 0 <1> <5> <4> <4> 47 m pd70433 5.2.3 macro service function the macro service function performs processing of simple data transfers, etc., by means of a microprogram (cpu internal dedicated firmware) started by generation of an interrupt request. the simple, standardized interrupt servicing which was coded and executed by a user program is performed automatically. macro service processing is caused by an interrupt request and is performed. macro service is designed to minimize as far as possible the frequency of generation of interrupts consisting mainly of software processing, hold down the software overhead due to a series of processes used in an interrupt (register saving, initialization, register restoration, return from the interrupt routine), and improve the cpu efficiency. processing performed by the macro service is transparent in terms of software, and it is possible to process as a single mass of data what was previously processed by software byte by byte, allowing more efficient programming. the v55pi macro service supports not only the simple data transfers used in the v25 and v35, but also various operating modes closely linked to the on-chip v55pi peripheral hardware, as shown below. (a) evtcnt (event counter) the counter is updated each time the macro service are generated, and when the counter reaches 0 the macro service for the corresponding interrupt source is terminated and a vectored interrupt or a register bank switching is generated. (b) dtacmp (data compare) the interrupt source specific sfr and preset byte data are compared, and if they match, the macro service for the corresponding interrupt source is terminated and a vectored interrupt or register bank switching is generated. (c) dtadif (data difference) the difference in using the timer/counter unit capture register is calculated. this is initiated by a timer interrupt: the value of the capture register latched last time is subtracted from the value of the capture register latched this time, and the result is stored in the previously specified memory buffer. when processing has been performed the previously set number of times, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (d) blktrs (block transfer) a data transfer is performed between the previously specified memory buffer and sfr. when the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (e) blktrsCc (block transfer with character search) a data transfer is performed between the previously specified memory buffer and sfr. when the previously set number of data transfers have been completed, or when the transfer data matches the previously set character data, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (f) rtoprtn (rtop transfer) data to be output to the real-time output port is transferred to the port 7 buffer (p7h, p7l), and data which specifies interval for output to the real-time output port is transferred to the timer compare register (cm00, cm01). (g) dtacmp-m (data compare with character mask) the logical product of the status data read from the external i/o and the previously set mask data is performed. the previously set byte data is compared with the result. if it matches, a data transfer is performed between the external i/ o and memory. if it does not match, or if the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. 48 m pd70433 6. dma function (dma controller) the v55pi incorporates a 2-channel dma controller which controls execution of memory-to-i/o or memory-to-memory dma transfers on the basis of dma requests generated by an on-chip peripheral hardware (serial interface, parallel interface, or timer), the external dmarq pin or a software trigger. each channel of the dma controller further comprises a main channel and a sub-channel: the operating mode determines whether the main channel and sub-channel are used as a single channel or as separate channels. when used as separate channels, function for a maximum of 4 channels can be constructed. 6.1 features two independent dma channels (max. 4-channel configuration possible) four transfer modes ? single transfer mode ... one dma transfer cycle is executed in response to one dma request. ? demand release mode ... consecutive dma transfer cycles are executed while dma request is active. ? single-step mode ... dma transfer cycles and cpu bus cycles are executed alternately after dma request generation. ? burst mode ... for each dma request, the specified number of dma transfer cycles are executed consecutively. five operating modes ? intelligent dma modeC1 (ring buffer system) ... dma transfers to ring buffer are controlled. ? intelligent dma modeC2 (counter control system) ... transfer data is transferred consecutively, divided into an arbitrary number of bytes. ? next address specification mode ... consecutive transfers are possible between different transfer buffers. ? 2-channel operating mode ... main channel and subchannel are used as independent channels. ? memory-to-memory transfer mode ... two bus cycles are started for one dma transfer cycle, and memory-to-memory transfer is executed. 3 clocks/1 bus cycle (no wait case) transfer objects ? external i/o ?? memory ... 1 dma transfer cycle/1 bus cycle ? sfr (internal i/o) ?? memory ... 1 dma transfer cycle/1 bus cycle ? memory ?? memory (memory includes sfr) ... 1 dma transfer cycle/2 bus cycles byte transfer/word transfer selectable transfer address increment/decrement/non-update selectable dma transfer end signal (tce0, tce1) output 24-bit dma memory address registers (mar0, mar1) 21-bit terminal counters (tc0, tc1) external dma request signal input pins (dmarq0, dmarq1: alternate function as port p80 and p81 pins) external dma acknowledge signal output pins (dmaak0, dmaak1) 49 m pd70433 table 6-1. transfer modes dma start source transfer mode onCchip software peripheral trigger single transfer available available available mode stops when the dmarq pin is not acknowledged driven low during the transfer. during transfer. reset of edma bit of dmamn acknowledged at register other times. single step available * available available mode burst none (stop disabled during the mode transfer) * the dma start source is an on-chip timer interrupt, and transfer is possible only when the transfer i/o specification is external. table 6-2. correspondence between operating modes and transfer modes possible transfer modes* operating mode transfer type <1> <2> <3> <4> intelligent dma modeC1 i/o (sfr) ? memory yes yes no no (ring buffer method) intelligent dma modeC2 memory ? i/o (sfr) no no yes yes (counter control method) next address specification mode i/o (sfr) ?? memory yes yes no no (stop at end) i/o ?? memory yes yes yes yes (repetition) i/o ?? memory yes yes yes no (stop at end) memory ?? memory yes no yes yes (repetition) memory ?? memory yes no yes no * transfer modes <1> single transfer mode <2> demand release mode <3> single step mode <4> burst mode not available not available available available * available available 2Cchannel operating mode memoryCmemory transfer mode demand release mode reset of edma bit of dmamn register reset of edma bit of dmamn acknowledged register not acknowledged acknowledged stop method interrupt dmarq pin 50 m pd70433 7. serial interface functions the v55pi is equipped with a 2-channel serial interface unit (ch0, ch1). the two communication protocols supported by the v55pi are as follows: (1) asynchronous uart (2) clocked csi sbi: 2-wire serial bus interface ioe: i/o expansion 3-wire serial interface 7.1 features two communication protocols supported two serial channels wake-up function on-chip dedicated baud rate generator dma request generated by completion of transmission/reception (transmit/receive data dma transfer is capable) 7.2 protocols the uart is an asynchronous serial interface which achieves data synchronization by means of start/stop bits, and is functionally enhanced uart functions compared with previous single-chip microcontroller. the csi (clocked serial interface) is a clocked serial interface which achieves synchronization by transmission/reception of a clock. the csi is a subset of the standard serial bus interface specification for nec single-chip microcontrollers, and i 2 c functions are not supported. the wake-up release function is implemented by using macro service. table 7-1. supported protocols supported protocols serial interface unit clocked (csi) asynchronous sbi ioe (uart) channel 0 yes yes yes channel 1 no yes yes the uart function or csi function can be programmably selected for each channel. protocol selection is performed by means of the protocol selection register (asp). 51 m pd70433 intsr n r b intst n uartm r d n shift register uarts shift register t d n cts transmission control parity addition reception control parity check external clock control intser n erp erf ero as t c* t b transmit serial clock receive serial clock 7.3 uart 7.3.1 features transfer rate: 95 to 390 kbps (with 12.5 mhz system clock f ) 123 to 500 kbps (with 16 mhz system clock f ) full-duplex operation capability on-chip dedicated (transmission and reception) baud rate generators wake-up function zero parity function parity error detection framing error detection overrun error detection three dedicated uart interrupt sources ? uart receive error interrupts (intser0, intser1) ? uart reception interrupts (intsr0, intsr1) ? uart transmisstion interrupts (intst0, intst1) macro service function ? uart reception interrupts (intsr0, intsr1) ? uart transmission interrupts (intst0, intst1) figure 7C1. uart block diagram * channel 0 only 52 m pd70433 7.4 clocked serial interface (csi) 7.4.1 features transfer speed: max. 3.125 mbps (with 12.5 mhz system clock f ) max. 4.0 mbps (with 16 mhz system clock f ) half-duplex communication data length: 8-bit unit external/internal clock selection function data msb-first/lsb-first selection function sbi mode (2-wire nec type serial bus) ... ch0 only ? address/command/data identification function ? function for chip selection by address ? wake-up function ? acknowledge signal (ack) control function ? busy signal (busy) control function the v55pi clocked serial interface has the following two operating modes. (1) 3Cwire serial i/o mode (ioe mode) in this mode, 8-bit data transfer is performed using three lines: the serial clock (sck), and serial data input and output (si, so). this mode is useful when connecting an i/o device, display controller, etc., which incorporates a conventional clocked serial interface. the functions of the v25 and v25+ ? have been enhanced, and data msb-first/lsb-first selection is possible. (2) serial bus interface mode (sbi mode) in the sbi mode, communication is performed with multiple devices by means of two lines: the serial clock (sck) and the serial bus interface (sb0 or sb1). this mode conforms to the nec serial bus format. in the sbi mode, the sender can output to the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. thus there is no need for the line for handshaking required when multiple devices are connected with a conventional clocked serial interface, allowing input/output ports to be used efficiently. in addition, wake-up release is performed using macro service. 53 m pd70433 8. parallel interface functions the v55pi incorporates a parallel interface unit for data input on a centronics specification interface, and general data input/output. 8.1 features the following features are provided as parallel interface functions: centronics specification interface compatibility input/output mode switchable by software busy signal manipulable by software busy signal and ack signal output timing settable initialization by external interrupt dedicated parallel interface interrupt source ? parallel interface interrupt (intpai) dma request signal generation in parallel transmission/reception ? intpai functions as a dma start trigger. signal pin input/output characteristic is ttl level (centronics specification interface) 54 m pd70433 internal bus internal bus input data latch ack control circuit dma request ack timing control busy control circuit pai timer counter ibsy s r data rd reset ibf s r q mb0, 1 oe pd0?d7 datastb busy ack intp5 output data latch pai timer counter pd0?d7 datastb busy ack wr data wr dma request intpai request int/ dma request control figure 8-1. parallel interface block diagram (a) input mode (b) output mode 55 m pd70433 9. timer function the v55pi timer unit can be used as an interval timer, free-running timer and event counter. it is also possible to manipulate p7 as a real-time output port, synchronized with interrupt requests generated by the timer. the normal timer function and real-time output port function are described here. 9.1 features the timer function offers the following features. 16-bit timer 4 two count clock sources are selectable ? system clock scaled output selectable ( f /8, f /32: system clock f ) ? external input pulses from ti pin external count output signal (ton output) three 16-bit capture registers on chip (external interrupt input signals intp0 to intp2 as triggers) six dedicated timer unit interrupt source (intcm00, intcm01, intcm10, intcm11, intcm21, intcm31) real-time output port function synchronized with timer interrupts 9.2 timer unit configuration the timer unit configuration is shown in figure 9-1, and the function of each timer in table 9-1. table 9-1. timer functions timer 0 timer 1 timer 2 timer 3 count function available available available available capture function available available not available not available compare function available available available available function toggle available not available available not available timer output output function set/reset not available not available available available output cascading not available not available available 56 m pd70433 figure 9-1. timer unit block diagram timer 0 16?it free running timer (tm0) capture register (ct00) capture register (ct01) compare register (cm00) compare register (cm01) intp0 intp1 f /8 ovf t t intcm00 intcm01 to00 to01 to real?ime output port timer 2 16?it timer register 2 (tm2) compare register (cm20) compare register (cm21) compare register (cm22) compare register (cm23) f /8 f /32 clear s r q s r q t intcm21 to dma controller to20 to21 timer 1 16?it timer register/event counter 1 (tm1) capture register (ct10) compare register (cm10) compare register (cm11) f /8 ovf ti intp2 clear intcm10 intcm11 timer 3 16?it timer register 3 (tm3) compare register (cm30) compare register (cm31) f /8 f /32 s r q to30 intcm31 clear, count enable clear 57 m pd70433 9.3 real-time output port function port 7 of the v55pi incorporates a real-time output port function, and can output the contents of the port 7 buffer (p7h, p7l) at programmable intervals from timer 0 bit-wise. 9.3.1 real-time output port configuration the real-time output port configuration is shown in figure 9-2. it comprises the following buffer registers, output and control registers. (1) port 7 buffer (p7h, p7l) the buffer registers hold the data to be output next when port 7 is set to the real-time output port mode. the port 7 buffer contents are not affected by reset input. (2) real-time output port (rtp) real-time output port output data is held in this port after being taken from the port 7 buffer, and output from the pins. rtp can be read or written to by an 8-bit or single-bit manipulation instruction (unlike the port 7 output port). (3) real-time output port delay specification regiser (rtpd) and delay counter this register is set and used when using the mode in which a delay time is inserted in the timing for output from the real-time output port (rtp) to the output pins. if the p7l bit is set to "0", "0" is output to the corresponding output pin bit after the elapse of the delay time equivalent to the count clock cycle time set in the real-time output port delay specification register after the time at which the transfe r trigger is generated. the delay time in this case is counted by the delay counter. (4) real-time output port control register (rtpc) rtpc specifies the operating mode of the real-time output port. it is possible to specify whether or not a delay is to be inserted when data is output, the timing for transferring data to the port 7 buffer, the transfer timing trigger, and so on. 58 m pd70433 figure 9C2. realCtime output port operation real?ime output port control register rtpc trg, byte dly 8 internal bus p7h port 7 buffer p7l port 7 buffer output latch rtp bit 3 output latches rtp7 to rtp4 p77 p76 p75 p74 p73 p72 p71 p70 control output signals to port 7 r s q no delay delay bor- row preset delay counter delay specification register selector intcm00 (timer 0) intcm01 (timer 1) /2 rtpd f 59 m pd70433 9.3.2 real-time output port operation real-time output port specification is performed bit-wise by the port 7 mode control register (pcm7). port 7 (p7), the port 7 buffer (p7h, p7l) and the real-time output port can be accessed as real-time output ports. data output is performed as described below. when output data is written in the port 7 buffer (p7h, p7l), the port 7 buffer contents are transferred to the real-time output port (rtp) and output to the pins in synchronization with the timing of an interrupt request from timer 0 (intcm00, intcm01), or a write to the trg bit in the control register (rtpc). an example of the direct control of the output pattern for a real-time output port and the output interval is shown in figure 9-3. update data is transferred from the two data storage areas set beforehand in the external memory space to the real- time output function buffer registers (p7h, p7l) and compare registers (cm00, cm01). figure 9-3. real-time output port stepping motor control output data area output timing data area external memory space d1 d2 d3 d4 t1 t2 t3 t4 register file space output data pointer buffer register address compare register address output timing data pointer rc initial value real?ime output counter (rc) macro service counter mode register channel pointer macro service control word +1 ? ? internal bus real-time output port transfer transfer or addition compare register cm00 or cm01 timer 0 free running timer tm0 match interrupt request f clk /8 real-time output trigger/ macro service activation intcm00 or intcm01 macro service processing buffer register p7h, p7l rtp stepping motor output latch 60 m pd70433 in particular, it is possible to insert a delay time in the timing for output by setting the real-time output port delay specification register (rtpd) pins. if the p7l bit is changed from "1" to "0", it is possible to perform output after inserting a delay time of 2 the system clock set in the rtpd from the timing at which the transfer trigger is generated. in this case, "0" is output from the corresponding output pin. this delay is counted by the delay counter. 61 m pd70433 10. pwm unit the v55pi is provided with an 8-bit precision pwm (pulse width modulation) signal output function. pwm output can be used as a digital-to-analog conversion output by connecting a low-pass filter, etc., externally. this is ideal for the actuator control signal for motors, etc. 10.1 features the pwm unit offers the following features: pwm output pulse active level selectable frequency: 25 mhz (with 12.5 mhz system clock f ) ? pwm cycle: 40.96 m s : 32 mhz (with 16 mhz system clock f ) ? pwm cycle: 32.00 m s output pulse width (duty): 0, 1/256, ....., 255/256 ? resolution: 160 ns (with 12.5 mhz system clock f ) 125 ns (with 16 mhz system clock f ) 10.2 pwm unit configuration the configuration of the pwm unit is shown in figure 10-1. the pwm unit consists of the pwm register (pwm) and pwm control register (pwmc), and an 8-bit counter. the pwm register controls the pulse width (duty) in the pwm output mode. the 8Cbit counter is set to 00h by reset input. the pwm register is not affected by reset input. 62 m pd70433 8-bit counter comparator pwm slave latch pwm register internal bus preset match detection signal overflow s r active level control q q pwm control register pwm output 000000ce alv figure 10-1. pwm unit block diagram 63 m pd70433 f *1 f f f /2 /2 /2 9 11 13 frequency divider watchdog timer (8 bits) clear wdtclr reset stop *2 overflow wdtout active timer (5 bits) intwdt oscillation stabilizing time control circuit ovf wdtout sq r 11. watchdog timer function the watchdog timer is a function for preventing inadvertent program looping and deadlocks. 11.1 features three overflow times settable (8.1, 32.7, 131.0 [ms]: system clock f = 16 mhz) (10.4, 41.9, 167.7 [ms]: system clock f = 12.5 mhz) output pin provided (wdtout pin) which can be directly connected to the reset pin 11.2 watchdog timer configuration and operation non-generation of a watchdog timer interrupt enables normal operation of the program or system to be confirmed. to use the watchdog function, an instruction (rstwdt) to clear the watchdog timer (start the count) must be included in at fixed intervals in the program execution time, at the start of a subroutine, etc. if the instruction which clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (intwdt) is generated and the low-level signal is output to the wdtout pin to report a program error. the watchdog timer configuration is shown in figure 11-1. figure 11-1. watchdog timer configuration diagram *1. f : system clock 2. wdtclr: watchdog timer clearance by instruction 64 m pd70433 12. a/d converter function the v55pi incorporates a high-speed, high-precision 8-bit analog/digital (a/d) converter with four analog inputs (ani0 to ani3). the a/d converter uses the successive approximation method, and is provided with four a/d conversion result registers (adcr0 to adcr3) which hold the conversion results. 12.1 features the a/d converter offers the following features: incorporates four 8-bit a/d conversion result registers. four analog input pins (ani0 to ani3) two a/d converter conversion operating modes ? scan mode : performs conversion by selecting multiple analog inputs in sequence. ? select mode : performs continuous conversion with only one pin used as the analog input. two conversion start methods ? hardware start : started by trigger input (intp4) ? software start : started by a/d converter mode register (adm) bit setting generation of conversion end interrupt request (intad) 65 m pd70433 input circuit ani0 ani1 ani2 ani3 p15/intp4 external trigger a/d converter mode register (adm) sample & hold circuit 8 internal bus control internal bus 8 8 successive approxi- mation register (sar) a/d conversion result register 0 (adcr0) comparator a/d conversion result register 1 (adcr1) a/d conversion result register 2 (adcr2) a/d conversion result register 3 (adcr3) intad av dd av ss av ref series resistance string r/2 r r/2 tap decoder figure 12-1. a/d converter block diagram 66 m pd70433 change accordng to dmac operating status data retention release method 13. standby functions the v55pi has two methods for controlling the operating clock as standby functions designed to reduce power dissipation. transition to either of these standby modes is possible by means of a dedicated instruction. table 13-1. halt/stop mode operating status parameter halt mode stop mode clock generator operating internal system clock stopped 16Cbit timer watchdog timer hold circuit stopped serial interface operating parallel interface a/d converter interrupt request controller dma controller iord, iowr high level high level ad0 to ad15 bus lines retained a16 to a23 r/w output high level high level refresh operation operating stopped all internal data retained (cpu status, all internal data retained (cpu status, ram contents, etc.) ram contents, etc.) ? nmi ? intwdt ? nmi ? maskable interrupt request ? reset input ? reset input 13.1 halt mode in this mode, the cpu operating clock is halted. setting the cpu idle time to the halt mode enables overall system power dissipation to be reduced. the halt mode is entered by executing the halt instruction. in the halt mode the cpu clock and program execution are stopped, and all register and on-chip ram contents immediately prior to the stoppage are retained. the status of each hardware unit is shown in table 13-1. when the halt instruction is executed during a dma transfer, transition to the halt mode is deferred until the transfer bus cycle for one dma request is completed. 67 m pd70433 13.2 stop mode in this mode, clock oscillation is stopped. this is effective when the entire application system is stopped, and offers extremely low power dissipation. the stop mode is entered by executing the stop instruction. in this mode all clocks are stopped. program execution is stopped, and all register and on-chip ram contents immediately prior to the stoppage are retained. the status of each hardware unit is shown in table 13-1. when the stop instruction is executed during a dma transfer, transition to the stop mode is deferred until the transfer bus cycle for one dma request is completed. if there is contention between a refresh cycle and stop instruction execution, transition to the stop mode is deferred until the refresh cycle is completed. 68 m pd70433 14. clock generator the clock generator supplies various clocks to the cpu and peripheral hardware, and controls the cpu operating mode. 14.1 clock generator configuration and operation the clock generator is configured as shown in figure 14-1. the clock generator clock is generated by a crystal resonator or ceramic resonator connected to the x1 and x2 pins. the clock generator output is subjected to waveform shaping (dividing frequency by 2) and selection of the scaling factor by means of the processor control register (prc), and is then used as the system clock f . the system clock f scaling factor is specified by the pck1 and pck0 bits of the prc register, and can be selected as 1/2, 1/4, 1/8 or 1/16 the oscillator frequency (f xx ). selecting a low-speed system clock f reduces the current consumption of internal circuit, allowing extended operation of a battery-driven system even when the voltage drops. an external clock can be input. in this case, the clock signal should be input to the x1 pin, and leave the x2 pin open. figure 14-1. clock generator clock oscillator x1 x2 1/2 1/2 1/2 1/2 f xx waveform shaping 1 8 f xx 1 4 f xx 1 2 f xx (=f x ) f time base counter baud rate generator watchdog timer system clock clkout selector internal bus 8 prc pck0 pck1 tb0 tb1 0 enclk 1 1 frequency dividers 1 16 f xx software interval timer refresh cycle generator pwm f xx : oscillator frequency f : system clock prc : processor control register 69 m pd70433 in the v55pi, the frequency divider (time base counter: tbc) which divides the internal system clock f is shared by each timer unit. the tbc cannot be read or written to by an instruction. the tbc tap output (divide-by-2 n clock) is supplied to the units shown below as a count clock. (1) refresh cycle generator (2) software interval timer (3) pwm unit (4) baud rate generator the tbc is cleared to 00h only by reset input, after which it is constantly incremented. tbc operation is stopped in the stop mode. the configuration of the tbc is shown in figure 14-2. figure 14-2. frequency divider (time base counter, tbc) configuration tbc baud rate generator refresh cycle generator software interval timer pwm /2 to /2 9 /2 to /2 8 3 /2 to /2 9 2 /2 and /2 7 f f f f f f f f f 70 m pd70433 15. software interval timer function the v55pi incorporates a 16-bit software interval timer as a timer for software timer functions and watch functions. 15.1 software interval timer configuration the configuration of the software interval timer is shown in figure 15-1. figure 15-1. software interval timer configuration f /4 /128 f software timer counter (stc) software timer counter compare register (stmc) clear intsit match detection 71 m pd70433 16. codec instructions the v55pi has 9 codec instructions. using these special instructions on the v55pi enables not only image information mh encoding but also mr encoding which previously required the use of a special device such as an acee (advanced compression/expansion engine) to be implemented by means of a small-scale, high-speed codec. 16.1 features the v55pi has the following 9 codec instructions (4 for compression, 5 for expansion): compression instructions (1) change point table creation instruction: coltrp (2) data transmission instruction (transmission of eol *1 , fill, rtc *2 , etc.): albit (3) mh encoding instruction: mhenc (4) mr encoding instruction: mrenc expansion instructions (5) eol detection instruction: scheol (6) 1-bit (tag) detection instruction: getbit (7) mh decoding change point table creation instruction: mhdec (8) mr decoding change point table creation instruction: mrdec (9) pixel data creation instruction: cnvtrp mh/mr encoding and mh/mr decoding using these instructions are performed as shown in figures 16-1 and 16-2. *1. eol: end of line 2. rtc: return to control note when compression/expansion processing is performed using the v55pi codec instructions, the following should be specified as preconditions. ? compression/expansion is to be performed line by line. ? consideration must be given to task switching and interrupt generation during compression processing. ? the number of bits processed per line must not be changed during processing of one page. ? the segment value must be changed for data over 64 kbytes that straddles segments during processing. 72 m pd70433 figure 16-1. mh/mr encoding processing flow start k = 0 k = 0 l = number of lines no yes data transmission instruction (eol + tag bit "1" transmission) data transmission instruction (eol + tag bit "0" transmission) change point table creation instruction change point table creation instruction mh encoding instruction mr encoding instruction k = k factor ?1 k = k ?1 data transmission instruction (fill transmission) l = l ?1 l = 0 no yes data transmission instruction (rtc transmission) end 73 m pd70433 * rtc is detected by two eols. figure 16-2. mh and mr decoding processing flow start eol detection instruction error detection to error processing yes no 1?it detection instruction (tag bit detection) tag = 1 no yes mh decoding instruction mr decoding instruction eol detection at start eol detection at start error detection yes no yes no end error detection end no yes pixel data creation instruction pixel data creation instruction no yes to error processing * 74 m pd70433 16.2 memory map the data memory areas required by the v55pi's codec instructions are shown below. (1) register file space this is the register bank for parameter setting. (2) user ram encoding line change point table : storage area for change point information required for performing encoding in the case of n bit/lines, a maximum area of 2n + 4 bytes is required. reference line table : reference line change point information storage area image data buffer : storage area for pixel data read from scanner in encoding, or encoding data received from modem in decoding transmit/receive buffer : buffer for transferring encoded data to modem/scanner print buffer : buffer for transferring decoded pixel data to recording system (3) user rom encoding conversion table : conversion table for mh/mr encoding decoding conversion table : conversion table for mh/mr decoding (4) access to expanded memory space the 16-mbyte expanded memory space can be accessed by using the expanded segment override prefix instruction (ds2: or ds3:). however, the segment registers ds2 and ds3 that are used during instruction execution are ds2 and ds3 in the parameter setting register banks of each instruction. table 16-1. instructions to which expanded segment override prefix can be attached ds2: ds3: codec instruction yes yes coltrp yes no mhenc yes yes mhdec yes no mrenc yes yes mrdec yes no scheol yes no getbit yes yes cnvtrp example ds2 : ds3 : coltrp ds2 : scheol the relationship between encoding instructions and data in memory is shown in figure 16-3, and the relationship between decoding instruction and data in memory is shown in figure 16-4. 75 m pd70433 figure 16-3. encoding instructions and data in memory * in case of mh/mr decoding instructions * in case of mh/mr encoding instructions figure 16-4. decoding instruction and data in memory dma image data (1 line) register file parameter frame encoding conversion table (512 bytes) * user rom software user ram data output instruction change point table creation instruction mh/mr encoding instruction work (change points) coding data (1 line) dma coding data register file parameter frame decoding conversion table (2304 bytes) * user rom software user ram eol detection instruction mh/mr decoding instruction work (change points) image data (1 line) 1?it detection instruction image data creation instruction 76 m pd70433 16.3 processing flow the instructions shown in 16.1 "features" are used in the order shown in figures 16-5 and 16-6 in encoding/decoding procesing. figure 16-5. processing flow for encoding of one line ..... ..... start data transmission instruction (albit) transmission of eol and tag change point table creation instruction (coltrp) change point information for 1 line created, and stored in prescribed storage area (change point table) mh/mr encoding instruction (mhenc/mrenc) mh/mr encoding for 1 line fill transmission end (pixel data) (change point table) input output input 1 word 02113116 white black white black white black white black encoded data ? transmision buffer 77 m pd70433 figure 16-6. processing flow for decoding of one line ..... ..... (change point table) input 1 word 02113116 white black white black white black white black encoded data ? printer buffer output (pixel data) input output start eol detection instruction (scheol) eol (000000000001) is detected tag (1 bit) is detected 1 bit detection instruction (getbit) mh/mr decoding instruction (mhdec/mrdec) pixel data creation instruction (cnvtrp) pixel data for 1 line is created end mh/mr decoding change point information for 1 line is generated and stored in specified area (change point table) 78 m pd70433 17. instruction set the v55pi instruction set is upward compatible with the v20/v30 (native mode) and v25/v35 instruction sets. 17.1 instructions newly added to v20/v30 and v25/v35 instructions which have been added to the v20/v30 and v25/v35 instruction sets, and instructions whose application range has been extended, are shown below. (1) instructions added to v20/v30. mnemonic operand instruction group brkcs reg 16 tsksw reg 16 movspa none movspb reg 16 btclr sfr, imm3, short-label conditional branch instruction retrbi none fint none stop none cpu control instruction register bank switching instruction data transfer instruction interrupt instruction 79 m pd70433 stack manipulation instruction (2) instructions added to v25/v35. mnemonic operand instruction group iram none register file space access override prefix instrution ds2 none ds3 none ds2, reg16, mem32 ds3, reg16, mem32 xsreg, reg16 xsreg, mem16 reg16, xsreg mem16, xsreg ds2 ds3/vpc ds2 ds3/vpc rstwdt imm8, imm8 watchdog timer manipulation instruction btclrl sfrl, imm3, short-label conditional branch instruction reg8 mem8 reg16 mem16 qhout imm16 qout imm16 queue manipulation instruction qtin imm16 albit none coltrp none mhenc none mrenc none scheol none dedicated fax instruction getbit none mhdec none mrdec none cnvtrp none bit manipulation instruction extended segment override prefix instruction data transfer instruction remark vpc: vector pc mov push bsch pop 80 m pd70433 17.2 instruction set operations table 17-1. operand type legend identifier description reg, 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) reg source register in an instruction using two 8/16-bit general registers reg8, 8-bit general register (destination register in an instruction using two 8-bit general registers) reg8' source register in an instruction using two 8-bit general registers reg16, 16-bit general register (destination register in an instruction using two 16-bit general registers) reg16' source register in an instruction using two 16-bit general registers mem 8/16-bit memory address mem8 8-bit memory address mem16 16-bit memory address mem32 32-bit memory address sfr special function register location: fff00h to fffefh sfrl special function register location: ffe00h to ffeffh dmem 16-bit direct memory address imm 8/16-bit immediate data imm3 3-bit immediate data imm4 4-bit immediate data imm8 8-bit immediate data imm8' 8-bit immediate date (1s compliment of imm8) imm16 16-bit immediate data acc accumulator aw or al sreg segment register xsreg extended segment register src-table name of 256-byte conversion table src-block name of source block addressed by register ix dst-block name of destination block addressed by register iy src-string name of source string addressed by register ix dst-string name of destination string addressed by register iy near-proc procedure start address in current program segment far-proc procedure start address in a different program segment near-label absolute address in current program segment short-label relative address of memory in range C128 to +127 bytes from end of instruction far-label absolute address in a different program segment regptr16 16-bit general register holding call address offset in current program segment memptr16 16-bit memory address holding call address offset in current program segment memptr32 32-bit memory address holding call address offset and segment data in a different program segment pop-value number of bytes removed from stack (0 to 64k, normally an even number) fp-op immediate value which identifies external floating point operation coprocessor operation code repeat repeat prefix instruction iram : register file space access override prefix instruction r register set (aw, bw, cw, dw, sp, bp, ix, iy) ( ) omissible or, / or 81 m pd70433 table 17-2. operation code legend identifier description w word/byte specification bit (1: word, 0: byte). however, when s = 1, sign extension byte data is specified as 16-bit operand even if w = 1. reg, reg 8/16-bit general register specification bits (000 to 111) mod, mem memory addressing specification bits (mod: 00 to 10, mem: 000 to 111) (disp-low) optional 16-bit displacement low byte (disp-high) optional 16-bit displacement high byte disp-low 16-bit displacement low byte for pc relative addition disp-high 16-bit displacement high byte for pc relative addition imm3 3-bit immediate data imm4 4-bit immediate data imm8 8-bit immediate data imm8' 8-bit immediate data (1's complement of imm8) imm16-low 16-bit immediate data low byte imm16-high 16-bit immediate data high byte addr-low 16-bit direct address low byte addr-high 16-bit direct address high byte sreg segment register specification bits (00 to 11) xsreg extended segment register specification bits (10 to 11) s sign extension specification bit (1: sign extension, 0: no sign extension) offset-low low byte of 16-bit offset data to be loaded in pc offset-high high byte of 16-bit offset data to be loaded in pc seg-low low byte of 16-bit segment data to be loaded in ps seg-high high byte of 16-bit segment data to be loaded in ps pop-value-low low byte of 16-bit data which specifies number of bytes to be removed from stack pop-value-high high byte of 16-bit data which specifies number of bytes to be removed from stack disp8 8-bit displacement for relative addition to pc x xxx yyy zzz operation code of an external floating point operation coprocessor ? y ? t 82 m pd70433 table 17-3. operation description legend identifier description aw accumulator (16 bits) ah accumulator (high byte) al accumulator (low byte) bw register bw (16 bits) cw register cw (16 bits) cl register cl (low byte) dw register dw sp stack pointer (16 bits) bp base pointer (16 bits) pc program counter (16 bits) psw program status word (16 bits) ix index register (source) (16 bits) iy index register (destination) (16 bits) ps program segment register (16 bits) ds3 extended data segment 3 register (16 bits) ds2 extended data segment 2 register (16 bits) ds1 data segment 1 register (16 bits) ds0 data segment 0 register (16 bits) ss stack segment register (16 bits) ac auxiliary carry flag cy carry flag p parity flag s sign flag z direction flag ie interrupt enable flag v overflow flag ibrk i/o break flag brk break flag rb0 register bank 0 flag rb1 register bank 1 flag rb2 register bank 2 flag rb3 register bank 3 flag vpc vector pc (...) contents of memory indicated by contents of in parenthesis disp displacement (8/16-bit) temp temporary register (8/16/32 bits) extCdisp8 16 bits with 8-bit displacement sign-extended seg immediate segment data (16 bits) offset immediate offset data (16 bits) ? transfer direction + addition - subtraction multiplication ? division % modulo logical product (and) logical sum (or) v exclusive logical sum (exclusive or) h 2-digit hexadecimal number h 4-digit hexadecimal number / alternate function, or 83 m pd70433 table 17-4. flag operation legend identifier description (blank) no change 0 cleared to 0 1 set to 1 set or cleared depending on result u undefined r previously saved value is restored table 17-5. memory addressing mem mod 00 01 10 000 bw + ix bw + ix + disp8 bw + ix + disp16 001 bw + iy bw + iy + disp8 bw + iy + disp16 010 bp + ix bp + ix + disp8 bp + ix + disp16 011 bp + iy bp + iy + disp8 bp + iy + disp16 100 ix ix + disp8 ix + disp16 101 iy iy + disp8 iy + disp16 110 direct address bp + disp8 bp + disp16 111 bw bw + disp8 bw + disp16 note when bp is used in memory addressing other than in a primitive instruction, the default segment register is ss. when bp is not used, the default segment register is ds0. in primitive instruction memory addressing, the destination block default segment register is ds1. in memory addressing, the source block default segment register is ds0. table 17-6. 8/16-bit general register selection table 17-7. segment register selection reg w = 0 w = 1 sreg 000 al aw 00 ds1 001 cl cw 01 ps 010 dl dw 10 ss 011 bl bw 11 ds0 100 ah sp 101 ch bp 110 dh ix 111 bh iy xsreg 10 ds3/vpc 11 ds2 table 17-8. extended segment register selection 84 m pd70433 number of clock cycles in the case of a memory operand the number of clock cycles depends on the addressing mode. the following numbers should be used for ea in table 17-9 number of clock cycles . mod 00 clock 01 clock 10 clock mem cycles cycles cycles 000 bw + ix 3 bw + ix + disp8 3 bw + ix + disp16 3 001 bw + iy 3 bw + iy + disp8 3 bw + iy + disp16 3 010 bp + ix 3 bp + ix + disp8 3 bp + ix + disp16 3 011 bp + iy 3 bp + iy + disp8 3 bp + iy + disp16 3 100 ix 2 ix + disp8 2 ix + disp16 2 101 iy 2 iy + disp8 2 iy + disp16 2 110 direct address 2 bp + disp8 2 bp + disp16 2 111 bw 2 bw + disp8 2 bw + disp16 2 t indicates the number of wait states. any number of wait states from "0" (no wait) up can be used. 85 m pd70433 table 17-9. number of clock cycles (1/20) byte processing word processing on-chip other on-chip other ram access access ram access access reg, reg' CC 2 2 2 2 mem, reg CC ea + 2 ea + 3 ea + 2 ea + 3 8 ea + 8 + 2t reg, mem ea + 2 ea + 5 + t ea + 2 16 ea + 5 + t mem, imm CC ea + 2 ea + 3 ea + 2 ea + 3 reg, imm CC 2 2 2 2 8 10 + 2t acc, dmem 4 7 + t 4 16 7 + t dmem, acc CC 4 5 4 5 sreg, reg16 CC CC CC 2 2 8 CC CC 2 2 16 8 ea + 8 + 2t mov sreg, mem16 CC CC ea + 2 16 ea + 5 + t 8 ea + 8 + 2t CC CC ea + 2 16 ea + 5 + t reg16, sreg CC CC CC 2 2 8 CC CC 2 2 16 mem16, sreg CC CC CC ea + 2 ea + 3 8 CC CC ea + 2 ea + 3 16 8 ea + 17 + 4t CC CC ea + 5 16 ea + 11 + 2t 8 ea + 17 + 4t CC CC ea + 5 16 ea + 11 + 2t 8 ea + 17 + 4t CC CC ea + 5 16 ea + 11 + 2t 8 ea + 17 + 4t CC CC ea + 5 16 ea + 11 + 2t mnemonic operands xsreg, reg16 vpc, reg16 xsreg,mem16/ vpc, mem16 reg16, xsreg/ reg16, vpc mem16, xsreg/ mem16, vpc ds0, reg16, mem32 ds2, reg16, mem32 ds1, reg16, mem32 ds3, reg16, mem32 data transfer instructions instruction group bus width * * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 86 m pd70433 table 17-9. number of clock cycles (2/20) byte processing word processing on-chip other on-chip other ram access access ram access access ah, psw CC 2 2 CC CC mov 8 3 3 psw, ah CC CC 16 2 2 ldea reg16, mem16 CC CC CC ea + 2 ea + 2 src-table CC 6 9 + t CC CC reg, reg' CC 4 4 4 4 ea + 10 + 2t ea + 4 ea + 7 + t ea + 4 ea + 7 + t CC CC CC 4 4 movspa CC CC CC 8 8 movspb reg16 CC CC CC 9 9 repc CC 0 to 1 0 to 1 0 to 1 0 to 1 repnc CC 0 to 1 0 to 1 0 to 1 0 to 1 rep/ repe/ CC 0 to 1 0 to 1 0 to 1 0 to 1 repz CC 0 to 1 0 to 1 0 to 1 0 to 1 21 + 2t 22 + 2t 18 + t 19 + t 8 9 + (14 + 2t)n 9 + (18 + 4t)n 55 9 + (11 + t)n 9 + (12 + 2t)n 18 + t 19 + t 16 9 + (11 + t)n 9 + (12 + 2t)n 55 23 + 2t 28 + 4t 20 + t 22 + 2t 8 9 + (16 + 2t)n 9 + (21 + 4t)n 55 9 + (13 + t)n 9 + (15 + 2t)n 20 + t 22 + 2t 16 9 + (13 + t)n 9 + (15 + 2t)n 55 trans/ transb repne/ repnz aw, reg16/ reg16, aw mem, reg/ reg, mem mnemonic operands data transfer instructions (rep cw = 0) 55 (rep cw = 0) 55 (rep) movbk dst-block, src-block (rep) cmpbk primitive block transfer instructions repeat prefixes instruction group src-block, dst-block bus width * * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark n: number of repetitions xch movbkb/ movbkw cmpbkb/ cmpbkw 87 m pd70433 table 17-9. number of clock cycles (3/20) byte processing word processing on-chip other on-chip other ram access access ram access access cmpm dst-block 20 + t 15 17 + t 15 8 10 + (12 + 2t)n 5 10 + 7n 10 + (9 + t)n 10 + 7n 17 + t 16 10 + (9 + t)n 5 ldm src-block 16 + t 10 13 + t 10 8 9 + (9 + 2t)n 5 9 + 3n 9 + (6 + t)n 9 + 3n 13 + t 16 9 + (6 + t)n 5 stm dst-block 13 12 13 12 8 9 + (9 + 2t)n 5 9 + 5n 9 + (6 + t)n 9 + 5n 13 16 9 + (6 + t)n 5 8 31 to 72 reg8, reg8' CC CC 22 to 63 16 23 to 64 8 31 to 72 reg8, imm4 CC CC 22 to 63 16 23 to 64 8 19 + 2t to 48 + 4t reg8, reg8' CC CC 19 to 41 16 19 to 42 + 2t 8 19 + 2t to 48 + 4t reg8, imm4 CC CC 19 to 41 16 19 to 42 + 2t mnemonic operands (rep cw = 0) 555 (rep) primitive block transfer instructions (rep cw = 0) 555 (rep) (rep cw = 0) 555 (rep) bit field manipulation instructions instruction group bus width * * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark n: number of repetitions cmpmb/ cmpmw ldmb/ ldmw stmb/ stmw ins ext 88 m pd70433 table 17-9. number of clock cycles (4/20) byte processing word processing on-chip other on-chip other ram access access ram access access acc8, imm8 8 10 + 2t CC 7 + t CC 16 7 + t 8 10 + 2t CC 7 + t CC 16 7 + t 8 CC 5 CC 5 16 8 CC 5 CC 5 16 20 + 2t 21 + 2t 17 + t 18 + t 8 9 + (13 + 2t)n 9 + (17 + 4t)n 55 9 + (10 + t)n 9 + (11 + 2t)n 17 + t 18 + t 16 9 + (10 + t)n 9 + (11 + 2t)n 55 17 + 2t 23 + 4t 14 + t 17 + 2t 8 9 + (10 + 2t)n 9 + (16 + 4t)n 55 9 + (7 + t)n 9 + (10 + 2t)n 14 + t 17 + 2t 16 9 + (7 + t)n 9 + (10 + 2t)n 55 mnemonic operands bus width *1 (rep) (rep) instruction group (rep cw = 0) 55 * 1. 8 : 8-bit width 16 : 16-bit width 2. when ibrk = 1. as shown in the next page when ibrk = 0. remark n: number of repetitions (rep cw = 0) 55 primitive input/output instructions input/output instructions acc, dw imm8, acc dw, acc dst-block, dw dw, src-block outm *2 inm *2 out *2 in *2 89 m pd70433 table 17-9. number of clock cycles (5/20) bus width * byte processing word processing on-chip other on-chip other ram access access ram access access 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t 8 60 + 10t 60 + 10t CC CC 16 40 + 5t 40 + 5t mnemonic operands primitive input/ output instructions * 8 : 8-bit width 16 : 16-bit width instruction group input/output instructions in acc8, imm8 out imm8, acc dst-block, dw inm dw, src-block outm dw, acc acc, dw 90 m pd70433 table 17-9. number of clock cycles (6/20) byte processing word processing on-chip other on-chip other ram access access ram access access reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 mnemonic operands * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width addition/subtraction instructions instruction group bus width * add addc sub 91 m pd70433 table 17-9. number of clock cycles (7/20) byte processing word processing on-chip other on-chip other ram access access ram access access reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 8 6 + (15 + t)n 6 + (19 + 3t)n CC CC 16 8 6 + (16 + t)n 6 + (20 + 3t)n CC CC 16 8 6 + (15 + t)n 6 + (18 + 2t)n CC CC 16 reg8 8 5 5 CC CC mem8 16 ea + 5 ea + 8 + t CC CC reg8 8 5 5 CC CC mem8 16 ea + 5 ea + 8 + t CC CC reg8 CC 2 2 CC CC 8 ea + 10 + 2t mem ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg16 CC CC CC 2 2 reg8 CC 2 2 CC CC 8 ea + 10 + 2t mem ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg16 CC CC CC 2 2 mnemonic operands * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark n: half of number of bcd digits dst-string, src-string dst-string, src-string dst-string, src-string instruction group increment/decrement instructions bcd operation instructions addition/subtraction instructions bus width * subc add4s sub4s cmp4s rol4 ror4 inc dec 92 m pd70433 table 17-9. number of clock cycles (8/20) byte processing word processing on-chip other on-chip other ram access access ram access access reg8 CC 11 11 15 15 8 ea + 21 + 2t mem8 ea + 12 ea + 14 + t ea + 16 16 ea + 18 + t reg16 CC 11 11 15 15 8 ea + 21 + 2t mem16 ea + 12 ea + 14 + t ea + 16 16 ea + 18 + t reg8 CC 10 10 14 14 8 ea + 20 + 2t mem8 ea + 11 ea + 13 + t ea + 15 16 ea + 17 + t reg16 CC 10 10 14 14 8 ea + 20 + 2t mem16 ea + 11 ea + 13 + t ea + 15 16 ea + 17 + t reg16, reg16', imm8/reg16, CC CC CC 14 14 imm8 reg16, 8 ea + 20 + 2t mem16, CC CC ea + 15 imm8 16 ea + 17 + t reg16, reg16', imm16/reg16, CC CC CC 14 14 imm16 reg16, 8 ea + 20 + 2t mem16, CC CC ea + 15 imm1616 ea + 17 + t mnemonic operands multiplication instructions * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width bus width * instruction group mulu mul 93 m pd70433 table 17-9. number of clock cycles (9/20) byte processing word processing on-chip other on-chip other ram access access ram access access 8 15/62 + 10t 15/62 + 10t 23/57 + 10t 23/57 + 10t reg8 16 15/42 + 5t 15/42 + 5t 23/42 + 5t 23/42 + 5t 8 ea + 16/63 + 10t ea + 18 + t/63 + 10t ea + 24/58 + 10t ea + 30 + 2t/58 + 10t mem8 16 ea + 16/43 + 5t ea + 18 + t/63 + 5t ea + 24/43 + 5t ea + 26 + t/43 + 5t 8 15/62 + 10t 15/62 + 10t 23/57 + 10t 23/57 + 10t reg16 16 15/42 + 5t 15/42 + 5t 23/42 + 5t 23/42 + 5t 8 ea + 16/63 + 10t ea + 18 + t/63 + 10t ea + 24/58 + 10t ea + 30 + 2t/58 + 10t mem16 16 ea + 16/43 + 5t ea + 18 + t/43 + 5t ea + 24/43 + 5t ea + 26 + t/43 + 5t 8 17/64 + 10t 17/64 + 10t 25/59 + 10t 25/59 + 10t reg8 16 17/44 + 5t 17/44 + 5t 25/44 + 5t 25/44 + 5t 8 ea + 18/65 + 10t ea + 20 + t/65 + 10t ea + 26/60 + 10t ea + 31 + 2t/60 + 10t mem8 16 ea + 18/45 + 5t ea + 20 + t/45 + 5t ea + 26/45 + 5t ea + 28 + t/45 + 5t 8 17/64 + 10t 17/64 + 10t 25/59 + 10t 25/59 + 10t reg16 16 17/44 + 5t 17/44 + 5t 25/44 + 5t 25/44 + 5t 8 ea + 18/65 + 10t ea + 20 + t/65 + 10t ea + 26/60 + 10t ea + 31 + 2t/60 + 10t mem16 16 ea + 18/45 + 5t ea + 20 + t/45 + 5t ea + 26/45 + 5t ea + 28 + t/45 + 5t 86 9CCCC 16 9 adj4a CC 3 3 CC CC 86 6 CC CC 16 9 9 adj4s CC 3 3 CC CC cvtbd CC 18 18 CC CC cvtdb CC 8 8 CC CC cvtbw CC 3 3 CC CC cvtwl CC CC CC 3 3 mnemonic operands bus width * division instructions * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark figures on right of / (slash) apply in case of a divide error. bcd adjustment instructions instruction group data conversion instructions divu div adjba adjbs 94 m pd70433 mem, reg/ reg, mem table 17-9. number of clock cycles (10/20) byte processing word processing on-chip other on-chip other ram access access ram access access reg, reg' CC 3 3 3 3 8 ea + 9 + 2t mem, reg ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 9 + 2t mem, imm ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t acc, imm CC 2 2 2 2 reg CC 2 2 2 2 8 ea + 10 + 2t mem ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg CC 2 2 2 2 8 ea + 10 + 2t mem ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, reg' CC 3 3 3 3 8 ea + 9 + 2t ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 9 + 2t mem, imm ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t acc, imm CC 2 2 2 2 reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 mnemonic operands complement operation instructions instruction group comparison instructions logical operation instructions bus width * cmp not neg test and * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 95 m pd70433 byte processing word processing on-chip other on-chip other ram access access ram access access reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 or 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 reg, reg' CC 3 3 3 3 8 ea + 10 + 2t mem, reg ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t 8 ea + 9 + 2t reg, mem ea + 2 ea + 6 + t ea + 2 xor 16 ea + 6 + t reg, imm CC 2 2 2 2 8 ea + 10 + 2t mem, imm ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t acc, imm CC 2 2 2 2 reg8, cl CC 3 3 3 3 8 ea + 9 + 2t mem8, cl ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t reg16, cl CC 3 3 3 3 8 ea + 9 + 2t mem16, cl ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t test1 reg8, imm3 CC 2 2 2 2 8 ea + 9 + 2t mem8, imm3 ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t reg16, imm4 CC 2 2 2 2 8 ea + 9 + 2t mem16, imm4 ea + 4 ea + 6 + t ea + 4 16 ea + 6 + t mnemonic operands logical operation instructions bit manipulation instructions bus width * instruction group table 17-9. number of clock cycles (11/20) * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 96 m pd70433 byte processing word processing on-chip other on-chip other ram access access ram access access reg8, cl CC 3 3 3 3 8 ea + 10 + 2t mem8, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, cl CC 3 3 3 3 8 ea + 10 + 2t mem16, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t not1 reg8, imm3 CC 2 2 2 2 8 ea + 10 + 2t mem8, imm3 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, imm4 CC 2 2 2 2 8 ea + 10 + 2t mem16, imm4 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t cyCC2222 reg8, cl CC 3 3 3 3 8 ea + 10 + 2t mem8, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, cl CC 3 3 3 3 8 ea + 10 + 2t mem16, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t clr1 reg8, imm3 CC 2 2 2 2 8 ea + 10 + 2t mem8, imm3 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, imm4 CC 2 2 2 2 8 ea + 10 + 2t mem16, imm4 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t cyCC2222 dir CC 2 2 2 2 mnemonic operands * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width bit manipulation instructions bus width * instruction group table 17-9. number of clock cycles (12/20) 97 m pd70433 byte processing word processing on-chip other on-chip other ram access access ram access access reg8, cl CC 3 3 3 3 8 ea + 10 + 2t mem8, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, cl CC 3 3 3 3 8 ea + 10 + 2t mem16, cl ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg8, imm3 CC 2 2 2 2 set1 8 ea + 10 + 2t mem8, imm3 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t reg16, imm4 CC 2 2 2 2 8 ea + 10 + 2t mem16, imm4 ea + 4 ea + 7 + t ea + 4 16 ea + 7 + t cyCC2222 dir CC 2 2 2 2 8 ea + 8 + 3n + t ea + 8 + 3n + t ea + 11 + 3n + 2t ea + 11 + 3n + 2t mem bsch 16 ea + 8 + 3n + t ea + 8 + 3n + t ea + 8 + 3n + t ea + 8 + 3n + t reg CC 4 + 3n 4 + 3n 4 + 3n 4 + 3n reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n shl 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n mnemonic operands bit manipulation instructions shift instructions * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark number of shifts (n in a bit manipulation instruction indicates the bit number searched for) bus width * instruction group table 17-9. number of clock cycles (13/20) 98 m pd70433 * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark number of shifts (n in a bit manipulation instruction indicates the bit number searched for) byte processing word processing on-chip other on-chip other ram access access ram access access reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n shr 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n shra 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n rol 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n mnemonic operands shift instructions rotate instructions bus width * instruction group table 17-9. number of clock cycles (14/20) 99 m pd70433 * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width remark number of shifts byte processing word processing on-chip other on-chip other ram access access ram access access reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n ror 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n rolc 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, 1 CC 3 3 3 3 8 ea + 10 + 2t mem, 1 ea + 3 ea + 7 + t ea + 3 16 ea + 7 + t reg, cl CC 5 + n 5 + n 5 + n 5 + n rorc 8 ea + 11 + 2t + n mem, cl ea + 5 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n reg, imm8 CC 5 + n 5 + n 5 + n 5 + n 8 ea + 11 + 2t + n mem, imm8 ea + 6 + n ea + 8 + t + n ea + 6 + n 16 ea + 8 + t + n mnemonic operands rotate instructions bus width * instruction group table 17-9. number of clock cycles (15/20) 100 m pd70433 byte processing word processing on-chip other on-chip other ram access access ram access access 8 19 + 2t near-proc CC CC CC 16 16 + t 8 18 + 2t regptr16 CC CC CC 16 15 + t 8 ea + 19 + 2t ea + 24 + 4t call memptr16 CC CC 16 ea + 16 + t ea + 18 + 2t 8 29 + 4t far-proc CC CC CC 16 23 + 2t 8 ea + 32 + 4t ea + 44 + 8t memptr32 CC CC 16 ea + 26 + 2t ea + 32 + 4t 8 18 + 2t CC CC CC 16 15 + t 8 19 + 2t pop-value CC CC CC 16 16 + t ret 8 26 + 4t *2 CC CC CC 16 20 + 2t 8 27 + 4t pop-value *2 CC CC CC 16 21 + 2t 8 ea + 13 + 2t mem16 CC CC ea + 7 16 ea + 10 + t reg16 CC CC CC CC 7 sreg CC CC CC CC 7 xsreg/vpc CC CC CC CC 7 push psw CC CC CC CC 6 8 57 + 14t rCCCCCC 16 36 + 7t imm8 CC CC CC CC 6 imm16 CC CC CC CC 6 mnemonic operands *1. 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 2. segment-external remark n: number of shifts subroutine control instructions stack manipulation instructions instruction group bus width *1 table 17-9. number of clock cycles (16/20) 101 m pd70433 table 17-9. number of clock cycles (17/20) byte processing word processing on-chip other on-chip other ram access access ram access access 8 ea + 13 + 2t ea + 14 + 2t mem16 CC CC 16 ea + 10 + t ea + 11 + t 8 10 + 2t reg16 CC CC CC 16 7 + t 8 10 + 2t sreg CC CC CC 16 7 + t pop 8 10 + 2t xsreg/vpc CC CC CC 16 7 + t 8 11 + 2t psw CC CC CC 16 8 + t 8 76 + 16t rCCCCCC 16 52 + 8t prepare *2 imm16, imm8 CC C- CC CC 9 8 10 + 2t dispose CC CC CC 16 7 + t near-label CC CC CC CC 9 short-label CC CC CC CC 9 regptr16 CC CC CC CC 8 8 ea + 14 + 2t br memptr16 CC CC ea + 9 16 ea + 11 + t far-label CC CC CC CC 9 8 ea + 24 + 4t memptr32 CC CC ea + 12 16 ea + 18 + 2t 8 15+2t+(16+4t)n prepare imm16, imm8 CC CC CC 16 14 + (12 + t)n mnemonic operands *1. 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 2. when imm8 = 0. as shown below when imm8 3 1. stack manipulation instructions branch instructions instruction group n : imm8 bus width *1 102 m pd70433 byte processing word processing on-chip other on-chip other ram access access ram access access bv short-label CC CC CC 9/3 9/3 bnv short-label CC CC CC 9/3 9/3 bc/bl short-label CC CC CC 9/3 9/3 bnc/bnl short-label CC CC CC 9/3 9/3 be/bz short-label CC CC CC 9/3 9/3 bne/bnz short-label CC CC CC 9/3 9/3 bnh short-label CC CC CC 9/3 9/3 bh short-label CC CC CC 9/3 9/3 bn short-label CC CC CC 9/3 9/3 bp short-label CC CC CC 9/3 9/3 bpe short-label CC CC CC 9/3 9/3 bpo short-label CC CC CC 9/3 9/3 blt short-label CC CC CC 9/3 9/3 bge short-label CC CC CC 9/3 9/3 ble short-label CC CC CC 9/3 9/3 bgt short-label CC CC CC 9/3 9/3 dbnzne short-label CC CC CC 10/5 10/5 dbnze short-label CC CC CC 10/5 10/5 dbnz short-label CC CC CC 10/5 10/5 bcwz short-label CC CC CC 10/5 10/5 8 btclr CC 21/14 CC CC 16 8 btclrl CC 20/13 CC CC 16 table 17-9. number of clock cycles (18/20) mnemonic operands sfr, imm3 short-label sfrl, imm3 short-label * 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width conditional branch instructions instruction group bus width * 103 m pd70433 table 17-9. number of clock cycles (19/20) byte processing word processing on-chip other on-chip other ram access access ram access access 8 50 + 10t 3CCCCCC 16 36 + 4t + t brk *2 8 52 + 10t imm8 ( 1 3) CC CC C- 16 38 + 4t + t 8 51 + 10 t brkv *2 CC CC CC 16 37 + 4t + t 8 28 + 4t reti CC CC CC 16 22 + 2t retrbi CC CC CC CC 9 fint 3 3 3 3 8 ea + 21 + 4t chkind *3 CC CC ea + 11 16 ea + 15 + 2t brkcs reg16 CC CC CC 12 12 *4 tsksw reg16 CC CC CC 13 13 halt CC CC CC CC CC stop CC CC CC CC CC idle CC CC CC CC CC poll CC CC CC CC CC di CC 3 3 3 3 ei CC3333 buslock CC 0 to 1 0 to 1 0 to 1 0 to 1 mnemonic operands interrupt instructions cpu control instructions *1. 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 2. when brk = 1, add 50 + 10t in case of 8-bit bus width, and 34 + 4t in case of 16-bit bus. 3. when (mem32) > reg16 or (mem32 + 2) < reg16, add 50 + 10t in case of 8-bit bus width, and 34 + 4t + t in case of 16-bit bus width. 4. register bank switching instructions remarks when t 3 2, t = t C 1 instruction group bus width *1 104 m pd70433 table 17-9. number of clock cycles (20/20) byte processing word processing on-chip other on-chip other ram access access ram access access 8 50 + 10t fp-op CC CC 16 36 + 4t + t fpo1 8 ea + 50 + 10 t fp-op, mem CC CC CC 16 ea + 36 + 4t + t 8 50 + 10t fp-op CC CC 16 36 + 4t + t fpo2 8 ea + 50 + 10 t fp-op, mem CC CC CC 16 ea + 36 + 4t + t nop CC 4 4 4 4 8 9/54 + 10t *3 *2 rstwdt imm8, imm8' CC CC CC 16 9/40 + 4t + t *3 *4 CC 0 to 1 0 to 1 0 to 1 0 to 1 qhout imm16 CC CC CC CC qout imm16 CC CC CC CC qtin imm16 CC CC CC CC CC albit CC CC CC CC CC coltrp CC CC CC CC CC mhenc CC CC CC CC CC mrenc CC CC CC CC CC scheol CC CC CC CC CC getbit CC CC CC CC CC mhdec CC CC CC CC CC mrdec CC CC CC CC CC cnvtrp CC CC CC CC CC mnemonic operands cpu control instructions instruction group bus width *1 *1. 8 : 8-bit width 16 : 16-bit width CC : both 8-bit and 16-bit bus width 2. watchdog timer manipulation instruction 3. figure after / (slash) applies when word processing is performed during data error. when t 3 2, t = t C 1 4. segment override prefix instructions (ds0:, ds1:, ps:, ss:) extended segment override prefix instructions (ds2: ds3:) register file space access override prefix instruction (iram) dedicated fax instructions queue manipula- tion instructions m pd70433 105 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z reg, reg' 1 0 0 0 1 0 1 w 1 1 reg reg' 2 reg ? reg' mem, reg 1 0 0 0 1 0 0 w mod reg mem 2 to 4 (mem) ? reg reg, mem 1 0 0 0 1 0 1 w mod reg mem 2 to 4 reg ? (mem) mem, imm 1 1 0 0 0 1 1 w mod0 0 0 mem 3 to 6 (mem) ? imm reg, imm 1 0 1 1 w reg 2 to 3 reg ? imm if w = 0, al ? (dmem) if w = 1, ah ? (dmem + 1), al ? (dmem) if w = 0, (dmem) ? al if w = 1, (dmem + 1) ? ah, (dmem) ? al sreg, reg16 1 0 0 0 1 1 1 0 1 1 0 sreg reg 2 sreg ? reg16 sreg : ss, ds0, ds1 xsreg, reg16 * 1 0 0 0 1 1 1 0 1 1 1 xsreg reg 2 xsreg ? reg16 xsreg : ds2, ds3 sreg, mem16 1 0 0 0 1 1 1 0 mod 0 sreg mem 2 to 4 sreg ? (mem16) sreg : ss, ds0, ds1 mov xsreg, mem16 * 1 0 0 0 1 1 1 0 mod 1 xsreg mem 2 to 4 xsreg ? (mem16) reg16, sreg 1 0 0 0 1 1 0 0 1 1 0 sreg reg 2 reg16 ? sreg reg16, xsreg * 1 0 0 0 1 1 0 0 1 1 1 xsreg reg 2 reg16 ? xsreg mem16, sreg 1 0 0 0 1 1 0 0 mod 0 sreg mem 2 to 4 (mem16) ? sreg mem16, xsreg * 1 0 0 0 1 1 0 0 mod 1 xsreg mem 2 to 4 (mem16) ? xsreg 1 1 0 0 0 1 0 1 mod reg mem 2 to 4 1 1 0 0 0 1 0 0 mod reg mem 2 to 4 00001111 00111110 3 to 5 mod reg mem 00001111 00110110 3 to 5 mod reg mem 17.3 instruction set table acc, dmem 1 010000w 3 ds1, reg16, reg16 ? (mem32) mem32 ds1 ? (mem32 + 2) ds2, reg16 * , reg16 ? (mem32) mem32 ds2 ? (mem32 + 2) ds3, reg16 * , reg16 ? (mem32) mem32 ds3 ? (mem32 + 2) * this instruction is newly added to the v25 or v35. data transfer instructions instruction group ds0, reg16, reg16 ? (mem32) mem32 ds0 ? (mem32 + 2) dmem, acc 1 010001w 3 m pd70433 106 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z ah, psw 10011111 1 ah ? s, z, f1, ac, f0, p, ibrk, cy mov psw, ah 10011110 1 s, z, f1, ac, f0, p, ibrk, cy ? ah ldea reg16, mem16 10001101 modreg mem 2 to 4 reg16 ? mem16 src-table 11010111 1 al ? (bw + al) reg, reg' 1000011w 11 reg reg' 2 reg ? reg' xch 1000011w modreg mem 2 to 4 (mem) ? reg 10010 reg 1 aw ? reg16 movspa *2 00001111 00100101 2 new register bank ss, sp ? old register bank ss, sp 00001111 10010101 movspb *2 reg16 3 11111 reg while cw 1 0, the following byte primitive block transfer instruction is executed and cw is decremented repc 01100101 1 (C1). if there is a pending interrupt, it is serviced. if cy 1 1, the loop is exited. same as above. if cy 1 0, the loop is exited. while cw 1 0, the following byte primitive block transfer instruction is executed and cw is decremented (C1). if there is a pending interupt, it is serviced. if the primitive block transfer instruction is cmpbk or cmpm, and z 1 1, the loop is exited. repne same as above. repnz if z 1 0, the loop is exited. rep repe 11110011 1 repz *1. the operand can be omitted in the case of the trans instruction. the transb instruction has no operand. 2. this instruction is newly added to the v20 or v30. repnc 01100100 1 11110010 1 trans transb *1 aw, reg16 reg16, aw repeat prefixes data transfer instructions instruction group mem, reg reg, mem ss, sp of register bank indicated by reg16 ? current register bank ss, sp m pd70433 107 dst-block, src-block src-block, dst-block primitive block transfer instructions instruction group operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z if w = 0, (iy) ? (ix) dir = 0: ix ? ix + 1, iy ? iy + 1 movbk dir = 1: ix ? ix C 1, iy ? iy C 1 movbkb 1 0 10010w 1 movbkw if w = 1, (iy + 1, iy) ? (ix + 1, ix) dir = 0: ix ? ix + 2, iy ? iy + 2 dir = 1: ix ? ix C 2, iy ? iy C 2 if w = 0, (ix) C (iy) dir = 0: ix ? ix + 1, iy ? iy + 1 cmpbk dir = 1: ix ? ix C 1, iy ? iy C 1 cmpbkb 1 0 10011w 1 cmpbkw if w = 1, (ix + 1, ix) C (iy + 1, iy) dir = 0: ix ? ix + 2, iy ? iy + 2 dir = 1: ix ? ix C 2, iy ? iy C 2 if w = 0, al C (iy) cmpm dir = 0: iy ? iy + 1 ; dir = 1: iy ? iy C 1 cmpmb dst-block 1 0 10111w 1 cmpmw if w = 1, aw C (iy + 1, iy) dir = 0: iy ? iy + 2 ; dir = 1: iy ? iy C 2 if w = 0, al ? (ix) ldm dir = 0: ix ? ix + 1 ; dir = 1: ix ? ix C 1 ldmb src-block 1 0 10110w 1 ldmw if w = 1, aw + (ix + 1, ix) dir = 0: ix + 2 ; dir = 1: ix ? ix C 2 if w = 0, (iy) ? al stm dir = 0: iy ? iy + 1 ; dir = 1: iy ? iy C 1 stmb dst-block 1 0 10101w 1 stmw if w = 1, aw C (iy + 1, iy) ? aw dir = 0: iy ? iy + 2 ; dir = 1: iy ? iy C 2 m pd70433 108 dw, src-block * when ibrk = 0, a software interrupt is generated automatically and the instruction is not executed. acc, dw 1 1 1 0 1 1 0 w 1 dw, acc 1 1 1 0 1 1 1 w 1 imm8, acc 1 1 1 0 0 1 1 w 2 instruction group operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z 00001111 00110001 reg8, reg8' 3 16-bit field ? aw 1 1 reg' reg ins 00001111 00111001 reg8, imm4 4 16-bit field ? aw 11000 reg 00001111 00110011 reg8, reg8' 3 aw ? 16-bit field 1 1 reg' reg ext 00001111 00111011 reg8, imm4 4 aw ? 16-bit field 11000 reg if w = 0, al ? (imm8) if w = 1, ah ? (imm8 + 1), al ? (imm8) in * if w = 0, al ? (dw) if w = 1, ah ? (dw + 1), al ? (dw) if w = 0, (imm8) ? al if w = 1, (imm8 + 1) ? ah, (imm8) ? al out * if w = 0, (dw) ? al if w = 1, (dw + 1) ? ah, (dw) ? al if w = 0, (iy) ? (dw) dir = 0: iy ? iy + 1 ; dir = 1: iy ? iy C 1 inm * 0110110w 1 if w = 1, (iy + 1, iy) ? (dw + 1, dw) dir = 0: iy ? iy + 2 ; dir = 1: iy ? iy C 2 if w = 0, (dw) ? (ix) dir = 0: ix ? ix + 1 ; dir = 1: ix ? ix C 1 outm * 0110111w 1 if w = 1, (dw + 1, dw) ? (ix + 1, ix) dir = 0: ix ? ix + 2 ; dir = 1: ix ? ix C 2 primitive input input/output bit field manipulation /output instructions instructions instructions acc, imm8 1 110010w 2 dst-block, dw m pd70433 109 acc, imm 0 0 0 1 1 1 0 w 2 to 3 acc, imm 0000010w 2 to 3 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z reg, reg' 0 0 0 0 0 0 1 w 1 1 reg reg' 2 reg ? reg + reg' mem, reg 0 0 0 0 0 0 0 w mod reg mem 2 to 4 (mem) ? (mem) + reg reg, mem 0 0 0 0 0 0 1 w mod reg mem 2 to 4 reg ? reg + (mem) add reg, imm 1 0 0 0 0 0 s w 11000 reg 3 to 4 reg ? reg + imm mem, imm 1 0 0 0 0 0 s w mod 0 0 0 mem 3 to 6 (mem) ? (mem) + imm if w = 0, al ? al + imm if w = 1, aw ? aw + imm reg, reg' 0 0 0 1 0 0 1 w 1 1 reg reg' 2 reg ? reg + reg' + cy mem, reg 0 0 0 1 0 0 0 w mod reg mem 2 to 4 (mem) ? (mem) + reg + cy reg, mem 0 0 0 1 0 0 1 w mod reg mem 2 to 4 reg ? reg + (mem) + cy addc reg, imm 1 0 0 0 0 0 s w 11010 reg 3 to 4 reg ? reg + imm + cy mem, imm 1 0 0 0 0 0 s w mod 0 1 0 mem 3 to 6 (mem) ? (mem) + imm + cy if w = 0, al ? al + imm + cy if w = 1, aw ? aw + imm + cy reg, reg' 0 0 1 0 1 0 1 w 1 1 reg reg' 2 reg ? reg C reg' mem, reg 0 0 1 0 1 0 0 w mod reg mem 2 to 4 (mem) ? (mem) C reg reg, mem 0 0 1 0 1 0 1 w mod reg mem 2 to 4 reg ? reg C (mem) sub reg, imm 1 0 0 0 0 0 s w 11101 reg 3 to 4 reg ? reg C imm mem, imm 1 0 0 0 0 0 s w mod 1 0 1 mem 3 to 6 (mem) ? (mem) C imm if w = 0, al ? al C imm if w = 1, aw ? aw C imm reg, reg' 0 0 0 1 1 0 1 w 1 1 reg reg' 2 reg ? reg C reg' C cy mem, reg 0 0 0 1 1 0 0 w mod reg mem 2 to 4 (mem) ? (mem) C reg C cy reg, mem 0 0 0 1 1 0 1 w mod reg mem 2 to 4 reg ? reg C (mem) C cy subc reg, imm 1 0 0 0 0 0 s w 11011 reg 3 to 4 reg ? reg C imm C cy mem, imm 1 0 0 0 0 0 s w mod 0 1 1 mem 3 to 6 (mem) ? (mem) C imm C cy if w = 0, al ? al C imm C cy if w = 1, aw ? aw C imm C cy acc, imm 0 0 1 0 1 1 0 w 2 to 3 acc, imm 0 0 0 1 0 1 0 w 2 to 3 addition/subtraction instructions instruction group m pd70433 110 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z (dst-string, src-string) (dst-string, src-string) (dst-string, src-string) reg8 0 0001111 00101000 3 11000 reg rol4 mem8 0 0001111 00101000 3 to 5 mod 0 0 0 mem reg8 0 0001111 00101010 3 11000 reg ror4 mem8 0 0001111 00101010 3 to 5 mod 0 0 0 mem reg8 1 1111110 11000 reg 2 reg8 ? reg8 + 1 inc mem 1111111w mod000 mem 2 to 4 (mem) ? (mem) + 1 reg16 0 1000 reg 1 reg16 ? reg16 + 1 reg8 1 1111110 11001 reg 2 reg8 ? reg8 C 1 dec mem 1111111w mod001 mem 2 to 4 (mem) ? (mem) C 1 reg16 0 1001 reg 1 reg16 ? reg16 C 1 add4s *1 00001111 00100000 2 dst bcd string ? dst bcd string + src bcd string *2 u uuu sub4s *1 00001111 00100010 2 dst bcd string ? dst bcd string C src bcd string *2 u uuu cmp4s *1 00001111 00100110 2 dst bcd string C src bcd string *2 u uuu *1. the operand can be omitted. 2. the number of bcd digits is given by the cl register: a value between 1 and 254 can be set. increment/decrement bcd operation instructions instructions instruction group al l al l al l al l reg mem reg mem high- order low- order high- order low- order high- order low- order high- order low- order m pd70433 111 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z aw ? al reg8 reg8 11110110 11100 reg 2 ah = 0: cy ? 0, v ? 0u uuu ah 1 0: cy ? 1, v ? 1 aw ? al (mem8) mem8 11110110 mod100 mem 2 to 4 ah = 0: cy ? 0, v ? 0u uuu ah 1 0: cy ? 1, v ? 1 mulu dw, aw ? aw reg16 reg16 11110111 11100 reg 2 dw = 0: cy ? 0, v ? 0u uuu dw 1 0: cy ? 1, v ? 1 dw, aw ? aw (mem16) mem16 11110111 mod100 mem 2 to 4 dw = 0: cy ? 0, v ? 0u uuu dw 1 0: cy ? 1, v ? 1 aw ? al reg8 reg8 11110110 11101 reg 2 ah = al sign extension: cy ? 0, v ? 0u uuu ah 1 al sign extension: cy ? 1, v ? 1 aw ? al (mem8) mem8 11110110 mod101 mem 2 to 4 ah = al sign extension: cy ? 0, v ? 0u uuu ah 1 al sign extension: cy ? 1, v ? 1 dw, aw ? aw reg16 reg16 11110111 11101 reg 2 dw = aw sign extension: cy ? 0, v ? 0u uuu dw 1 aw sign extension: cy ? 1, v ? 1 dw, aw ? aw (mem16) mem16 11110111 mod101 mem 2 to 4 dw = aw sign extension: cy ? 0, v ? 0u uuu dw 1 aw sign extension: cy ? 1, v ? 1 mul reg16, reg16 ? reg16' imm8 (reg16',) * 01101011 11 reg reg' 3 product 16 bits: cy ? 0, v ? 0u uuu imm8 product > 16 bits: cy ? 1, v ? 1 reg16, reg16 ? (mem16) imm8 mem16, 01101011 modreg mem 3 to 5 product 16 bits: cy ? 0, v ? 0u uuu imm8 product > 16 bits: cy ? 1, v ? 1 reg16, reg16 ? reg16' imm16 (reg16',) * 01101001 11 reg reg' 4 product 16 bits: cy ? 0, v ? 0u uuu imm16 product > 16 bits: cy ? 1, v ? 1 reg16, reg16 ? (mem16) imm16 mem16, 01101001 modreg mem 4 to 6 product 16 bits: cy ? 0, v ? 0u uuu imm16 product > 16 bits: cy ? 1, v ? 1 multiplication instructions * the 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified. instruction group m pd70433 112 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z temp ? aw if temp ? reg8 ffh ah ? temp%reg8, al ? temp ? reg8 reg8 1 1 1 1 0 1 1 0 11110 reg 2 if temp ? reg8 > ffh uuuuuu (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? aw if temp ? (mem8) ffh ah ? temp%(mem8), al ? temp ? (mem8) mem8 1 1 1 1 0 1 1 0 mod 1 1 0 mem 2 to 4 if temp ? (mem8) > ffh uuuuuu (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) divu temp ? dw, aw if temp ? reg16 ffffh dw ? temp%reg16, aw ? temp ? reg16 reg16 1 1 1 1 0 1 1 1 11110 reg 2 if temp ? reg16 > ffffh uuuuuu (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw if temp ? (mem16) ffffh dw ? temp%(mem16), aw ? temp ? (mem16) mem16 1 1 1 1 0 1 1 1 mod 1 1 0 mem 2 to 4 if temp ? (mem16) > ffffh uuuuuu (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) unsigned division instructions instruction group m pd70433 113 signed division instructions instruction group operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z temp ? aw if temp ? reg8 > 0 and temp ? reg8 7fh; or if temp ? reg8 < 0 and temp ? reg8 > 0 C 7fh C 1 ah ? temp%reg8, al ? temp ? reg8 reg8 11110110 11111 reg 2 if temp ? reg8 > 0 and temp ? reg8 > 7fh; or uuuuuu if temp ? reg8 < 0 and temp ? reg8 0 C 7fh C 1 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? aw if temp ? (mem8) > 0 and temp ? (mem8) 7fh; or if temp ? (mem8) < 0 and temp ? (mem8) > 0 C 7fh C 1 ah ? temp%(mem8), al ? temp ? (mem8) mem8 11110110 mod111 mem 2 to 4 if temp ? (mem8) > 0 and temp ? (mem8) > 7fh; or uuuuuu if temp ? (mem8) < 0 and temp ? (mem8) 0 C 7fh C 1 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) div temp ? dw, aw if temp ? reg16 > 0 and temp ? reg16 7fffh; or if temp ? reg16 < 0 and temp ? reg16 > 0 C 7fffh C 1 dw ? temp%reg16, aw ? temp ? reg16 reg16 11110111 11111 reg 2 if temp ? reg16 > 0 and temp ? reg16 > 7fffh; or uuuuuu if temp ? reg16 < 0 and temp ? reg16 0 C 7fffh C 1 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw if temp ? (mem16) > 0 and temp ? (mem16) 7fffh; or if temp ? (mem16) < 0 and temp ? (mem16) > 0 C 7fffh C 1 ah ? temp%(mem16), aw ? temp ? (mem16) mem16 11110111 mod111 mem 2 to 4 if temp ? (mem16) > 0 and temp ? (mem16) > 7fffh; or uuuuuu if temp ? (mem16) < 0 and temp ? (mem16) 0 C 7fffh C 1 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) m pd70433 114 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z adjba 00110111 1 if al 0fh > 9 or ac = 1: al ? al + 6 uuuu ah ? ah + 1, ac ? 1, cy ? ac, al ? al 0fh if al 0fh > 9 or ac = 1: adj4a 00100111 1 al ? al + 6, ac ? 1 u if al > 9fh or cy = 1: al ? al + 60h, cy ? 1 if al 0fh > 9 or ac = 1: adjbs 00111111 1 al ? al C 6, ac ? 1 uuuu cy ? ac, al ? al 0fh if al 0fh > 9 or ac = 1: adj4s 00101111 1 al ? al C 6, cy ? cy ac, ac ? 1 u if al > 9fh or cy = 1: al ? al C 60h, cy ? 1 cvtbd 11010100 00001010 2 ah ? ah ? 0ah, al ? al%0ah u u u cvtdb 11010101 00001010 2 al ? ah 0ah + al, ah ? 0uuu cvtbw 10011000 1 if al < 80h: ah ? 0, otherwise: ah ? ffh cvtwl 10011001 1 if aw < 8000h: dw ? 0, otherwise: dw ? ffffh reg, reg' 0011101w 11 reg reg' 2 reg C reg' mem, reg 0011100w mod reg mem 2 to 4 (mem)C reg reg, mem 0011101w mod reg mem 2 to 4 reg C (mem) cmp reg, imm 100000sw 11111 reg 3 to 4 reg C imm mem, imm 100000sw mod111 mem 3 to 6 (mem) C imm acc, imm 0011110w 2 to 3 if w = 0, al C imm if w = 1, aw C imm reg 1111011w 11010 reg 2 reg ? reg not mem 1111011w mod010 mem 2 to 4 (mem) C (mem) * reg 1111011w 11011 reg 2 reg ? reg + 1 neg mem 1111011w mod011mem 2 to 4 (mem) ? (mem) + 1 * complement operation instructions instruction group data conversion instructions comparison bcd adjustment instructions instruction m pd70433 115 logical operation instructions instruction group operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z reg, reg' 1 000010w 11 reg' reg 2 reg reg' u 0 0 mem, reg 1000010w modreg mem 2 to 4 (mem) reg u 0 0 reg, mem test reg, imm 1 111011w 11000 reg 3 to 4 reg imm u 0 0 mem, imm 1 111011w mod000 mem 3 to 6 (mem) imm u 0 0 acc, imm 1 010100w 2 to 3 if w = 0, al imm8 u00 if w = 1, aw imm16 reg, reg' 0 010001w 11 reg reg' 2 reg ? reg reg' u 0 0 mem, reg 0 010000w modreg mem 2 to 4 (mem) ? (mem) reg u 0 0 reg, mem 0 010001w modreg mem 2 to 4 reg ? reg (mem) u 0 0 and reg, imm 1 000000w 11100 reg 3 to 4 reg ? reg imm u 0 0 mem, imm 1 000000w mod100 mem 3 to 6 (mem) ? (mem) imm u 0 0 acc, imm 010010w 2 to 3 if w = 0, al ? al imm8 u00 if w = 1, aw ? aw imm16 reg, reg' 0 000101w 11 reg reg' 2 reg ? reg reg' u 0 0 mem, reg 0 000100w modreg mem 2 to 4 (mem) ? (mem) reg u 0 0 reg, mem 0 000101w modreg mem 2 to 4 reg ? reg (mem) u 0 0 or reg, imm 1 000000w 11001 reg 3 to 4 reg ? reg imm u 0 0 mem, imm 1 000000w mod001 mem 3 to 6 (mem) ? (mem) imm u 0 0 acc, imm 0 000110w 2 to 3 if w = 0, al ? al imm8 u00 if w = 1, aw ? aw imm16 reg, reg' 0 011001w 11 reg reg' 2 reg ? reg v reg' u 0 0 mem, reg 0 011000w modreg mem 2 to 4 (mem) ? (mem) v reg' u 0 0 reg, mem 0 011001w modreg mem 2 to 4 reg ? reg v (mem) u 0 0 xor reg, imm 1 000000w 11110 reg 3 to 4 reg ? reg v imm u 0 0 mem, imm 1 000000w mod110 mem 3 to 6 (mem) ? (mem) v imm u 0 0 acc, imm 0 011010w 2 to 3 if w = 0, al ? al v imm8 u00 if w = 1, aw ? aw v imm16 m pd70433 116 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z reg8, cl 00010000 11000 reg 3 reg8 bit no.cl = 0 : z ? 1 u00uu reg8 bit no.cl = 1 : z ? 0 mem8, cl 0 0 0 0 mod 0 0 0 mem 3 to 5 (mem)8 bit no.cl = 0 : z ? 1 u00uu (mem)8 bit no.cl = 1 : z ? 0 reg16, cl 0 0 0 1 1 1 0 0 0 reg 3 reg16 bit no.cl = 0 : z ? 1 u00uu reg16 bit no.cl = 1 : z ? 0 mem16, cl 0 0 0 1 mod 0 0 0 mem 3 to 5 (mem16) bit no.cl = 0 : z ? 1 u00uu (mem16) bit no.cl = 1 : z ? 0 test1 reg8, imm3 1 0 0 0 1 1 0 0 0 reg 4 reg8 bit no.imm3 = 0 : z ? 1 u00uu reg8 bit no.imm3 = 1 : z ? 0 mem8, imm3 1 0 0 0 mod 0 0 0 mem 4 to 6 (mem8) bit no.imm3 = 0 : z ? 1 u00uu (mem8) bit no.imm3 = 1 : z ? 0 reg16, imm4 1 0 0 1 1 1 0 0 0 reg 4 reg16 bit no.imm4 = 0 : z ? 1 u00uu reg16 bit no.imm4 = 1 : z ? 0 mem16, imm4 1 0 0 0 mod 0 0 0 mem 4 to 6 (mem16) bit no.imm4 = 0 : z ? 1 u00uu (mem16) bit no.imm4 = 1 : z ? 0 reg8, cl 0 1 1 0 1 1 0 0 0 reg 3 reg8 bit no.cl ? reg8 bit no.cl mem8, cl 0 1 1 0 mod 0 0 0 mem 3 to 5 (mem8) bit no.cl ? (mem8) bit no.cl reg16, cl 0 1 1 1 1 1 0 0 0 reg 3 reg16 bit no.cl ? reg16 bit no.cl mem16, cl 0 1 1 1 mod 0 0 0 mem 3 to 5 (mem16) bit no.cl ? (mem16) bit no.cl not1 reg8, imm3 1 1 1 0 1 1 0 0 0 reg 4 reg8 bit no.imm3 ? reg8 bit no.imm3 mem8, imm3 1 1 1 0 mod 0 0 0 mem 4 to 6 (mem8) bit no.imm3 ? (mem8) bit no.imm3 reg16, imm4 1 1 1 1 1 1 0 0 0 reg 4 reg16 bit no.imm4 ? reg16 bit no.imm4 mem16, imm4 1 1 1 1 mod 0 0 0 mem 4 to 6 (mem16) bit no.imm4 ? (mem16) bit no.imm4 bit manipulation instructions 2nd byte * 3rd byte * * 1st byte = 0fh not1 cy 1 1 1 1 0 1 0 1 1 cy ? cy instruction group m pd70433 117 cy 11111000 1 cy ? 00 clr1 dir 1 1 1 1 1 1 0 0 1 dir ? 0 cy 11111001 1 cy ? 11 set1 dir 1 1 1 1 1 1 0 1 1 dir ? 0 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z reg8, cl 0 0 0 1 0 0 1 0 11000 reg 3 reg8 bit no.cl ? 0 mem8, cl 0 0 1 0 mod 0 0 0 mem 3 to 5 (mem8) bit no.cl ? 0 reg16, cl 0 0 1 1 11000 reg 3 reg16 bit no.cl ? 0 mem16, cl 0 0 1 1 mod 0 0 0 mem 3 to 5 (mem16) bit no.cl ? 0 clr1 reg8, imm3 1 0 1 0 11000 reg 4 reg8 bit no.imm3 ? 0 mem8, imm3 1 0 1 0 mod 0 0 0 mem 4 to 6 (mem8) bit no.imm3 ? 0 reg16, imm4 1 0 1 1 11000 reg 4 reg16 bi no.imm4 ? 0 mem16, imm4 1 0 1 1 mod 0 0 0 mem 4 to 6 (mem16) bit no.imm4 ? 0 reg8, cl 0 1 0 0 11000 reg 3 reg8 bit no.cl ? 1 mem8, cl 0 1 0 0 mod 0 0 0 mem 3 to 5 (mem8) bit no.cl ? 1 reg16, cl 0 1 0 1 11000 reg 3 reg16 bit no.cl ? 1 mem16, cl 0 1 0 1 mod 0 0 0 mem 3 to 5 (mem16) bit no.cl ? 1 set1 reg8, imm3 1 1 0 0 11000 reg 4 reg8 bit no.imm3 ? 1 mem8, imm3 1 1 0 0 mod 0 0 0 mem 4 to 6 (mem8) bit no.imm3 ? 1 reg16, imm4 1 1 0 1 11000 reg 4 reg16 bi no.imm4 ? 1 mem16, imm4 1 1 0 1 mod 0 0 0 mem 4 to 6 (mem16) bit no.imm4 ? 1 instruction group 2nd byte * 3rd byte * * 1st byte = 0fh bit manipulation instructions m pd70433 118 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z 00001111 00111100 reg8 3 uuuuu 11000 reg 00001111 00111100 mem8 3 to 5 uuuuu mod 0 0 0 mem bsch * 00001111 00111101 reg16 3 uuuuu 11000 reg 00001111 00111101 mem16 3 to 5 uuuuu mod 0 0 0 mem qhout * imm16 00001111 01110000 4 removes block queued at head of queue and stores its uuuuu segment address in p2. qout * imm16 00001111 01110001 4 removes queue block indicated by p2. uuuuu qtin * imm16 00001111 01110010 4 queues block indicated by p2 at end of queue. bit manipulation instruction queue manipu- lation instructions instruction group * this instruction is newly added to the v25 or v35. remarks p2: parameter table (in register file) <1> cl ? 0 <2> [when reg8 bit no.cl=0] if cl<7, re-executed from cl ? cl+1, <2> if cl=7 z ? 1 [when reg8 bit no.cl=1] z ? 0 <1> cl ? 0 <2> [when mem8 bit no.cl=0] if cl<7, re-executed from cl ? cl+1, <2> if cl=7 z ? 1 [when mem8 bit no.cl=1] z ? 0 <1> cl ? 0 <2> [when reg16 bit no.cl=0] if cl<15, re-executed from cl ? cl+1, <2> if cl=15 z ? 1 [when reg16 bit no.cl=1] z ? 0 <1> cl ? 0 <2> [when mem16 bit no.cl=0] if cl<15, re-executed from cl ? cl+1, <2> if cl=15 z ? 1 [when mem16 bit no.cl=1] z ? 0 m pd70433 119 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z cy ? reg msb, reg ? reg 2 reg, 1 1101000w 11100 reg 2 if reg msb 1 cy, v ? 1u if reg msb = cy, v ? 0 cy ? (mem) msb, (mem) ? (mem) 2 mem, 1 1101000w mod100 mem 2 to 4 if (mem) msb 1 cy, v ? 1u if (mem) msb = cy, v ? 0 temp ? cl, while temp 1 0, the following operations are reg, cl 1101001w 11100 reg 2 repeated: cy ? reg msb, reg ? reg 2u u temp ? temp C 1 shl temp ? cl, while temp 1 0, the following operations are mem, cl 1101001w mod100 mem 2 to 4 repeated: cy ? (mem) msb, (mem) ? (mem) 2u u temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are reg, imm8 1100000w 11100 reg 3 repeated: cy ? reg msb, reg ? reg 2u u temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are mem, imm8 1100000w mod100 mem 3 to 5 repeated: cy ? (mem) msb, (mem) ? (mem) 2u u temp ? temp C 1 cy ? reg lsb, reg ? reg ? 2 reg, 1 1101000w 11101 reg 2 if reg msb 1 bit after reg msb: v ? 1u if reg msb = bit after reg msb: v ? 0 cy ? (mem) lsb, (mem) ? (mem) ? 2 mem, 1 1101000w mod101 mem 2 to 4 if (mem) msb 1 bit after (mem) msb: v ? 1u if (mem) msb = bit after (mem) msb: v ? 0 temp ? cl, while temp 1 0, the following operations are reg, cl 1101001w 11101 reg 2 repeated: cy ? reg lsb, reg ? reg ? 2u u temp ? temp C 1 shr temp ? cl, while temp 1 0, the following operations are mem, cl 1101001w mod101 mem 2 to 4 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2u u temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are reg, imm8 1100000w 11101 reg 3 repeated: cy ? reg lsb, reg ? reg ? 2u u temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are mem, imm8 1100000w mod101 mem 3 to 5 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2u u temp ? temp C 1 instruction group shift instructions m pd70433 120 instruction group operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z cy ? reg lsb, reg ? reg ? 2, v ? 0 reg, 1 1101000w 11111 reg 2 msb of operand is unchanged. u 0 cy ? (mem) lsb, (mem) ? (mem) ? 2, v ? 0 mem, 1 1101000w mod111 mem 2 to 4 msb of operand is unchanged. u 0 temp ? cl, while temp 1 0, the following operations are reg, cl 1101001w 11111 reg 2 repeated: cy ? reg lsb, reg ? reg ? 2u u temp ? temp C 1, msb of operand is unchanged. shra temp ? cl, while temp 1 0, the following operations are mem, cl 1101001w mod111 mem 2 to 4 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2u u temp ? temp C 1, msb of operand is unchanged. temp ? imm8, while temp 1 0, the following operations are reg, imm8 1100000w 11111 reg 3 repeated: cy ? reg lsb, reg ? reg ? 2u u temp ? temp C 1, msb of operand is unchanged. temp ? imm8, while temp 1 0, the following operations are mem, imm8 1100000w mod111 mem 3 to 5 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2u u temp ? temp C 1, msb of operand is unchanged. cy ? reg msb, reg ? reg 2 + cy reg, 1 1101000w 11000 reg 2 reg msb 1 cy: v ? 1 reg msb = cy: v ? 0 cy ? (mem) msb, (mem) ? (mem) 2 + cy mem, 1 1101000w mod000 mem 2 to 4 (mem) msb 1 cy: v ? 1 (mem) msb = cy: v ? 0 temp ? cl, while temp 1 0, the following instructions are reg, cl 1101001w 11000 reg 2 repeated: cy ? reg msb, reg ? reg 2 + cy u temp ? temp C 1 rol temp ? cl, while temp 1 0, the following instructions are mem, cl 1101001w mod000 mem 2 to 4 repeated: cy ? (mem) msb, (mem) ? (mem) 2 + cy u temp ? temp C 1 temp ? imm8, while temp 1 0, the following instructions are reg, imm8 1100000w 11000 reg 3 repeated: cy ? reg msb, reg ? reg 2 + cy u temp ? temp C 1 temp ? imm8, while temp 1 0, the following instructions are mem, imm8 1100000w mod000 mem 3 to 5 repeated: cy ? (mem) msb, (mem) ? (mem) 2 + cy u temp ? temp C 1 rotate instruction shift instruction m pd70433 121 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z cy ? reg lsb, reg ? reg ? 2 reg, 1 1101000w 11001 reg 2 reg msb ? cy reg msb 1 bit after reg msb: v ? 1 reg msb = bit after reg msb: v ? 0 cy ? (mem) lsb, (mem) ? (mem) ? 2 mem, 1 1101000w mod001 mem 2 to 4 (mem) msb ? cy (mem) msb 1 bit after (mem) msb: v ? 1 (mem) msb = bit after (mem) msb: v ? 0 temp ? cl, while temp 1 0, the following operations are reg, cl 1101001w 11001 reg 2 repeated: cy ? reg lsb, reg ? reg ? 2 u reg msb ? cy temp ? temp C 1 ror temp ? cl, while temp 1 0, the following operations are mem, cl 1101001w mod001 mem 2 to 4 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2 u (mem) msb ? cy temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are reg, imm8 1100000w 11001 reg 3 repeated: cy ? reg lsb, reg ? reg ? 2 u reg msb ? cy temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are mem, imm8 1100000w mod001 mem 3 to 5 repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2 u (mem) msb ? cy temp ? temp C 1 tmpcy ? cy, cy ? reg msb reg, 1 1101000w 11010 reg 2 reg ? reg 2 + tmpcy reg msb 1 cy: v ? 1 reg msb = cy: v ? 0 tmpcy ? cy, cy ? (mem) msb mem, 1 1101000w mod010 mem 2 to 4 (mem) ? (mem) 2 + tmpcy (mem) msb 1 cy: v ? 1 (mem) msb = cy: v ? 0 rolc temp ? cl, while temp 1 0, the following operations are reg, cl 1101001w 11010 reg 2 repeated: tmpcy ? cy, cy ? reg msb u reg ? reg 2 + tmpcy temp ? temp C 1 temp ? cl, while temp 1 0, the following operations are mem, cl 1101001w mod010 mem 2 to 4 repeated: tmpcy ? cy, cy ? (mem) msb u (mem) ? (mem) 2 + tmpcy temp ? temp C 1 rotate instructions instruction group m pd70433 122 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z temp ? imm8, while temp 1 0, the following instructions reg, imm8 1100000w 11010 reg 3 are repeated: tmpcy ? cy, cy ? reg msb u reg ? reg 2 + tmpcy temp ? temp C 1 rolc temp ? imm8, while temp 1 0, the following instructions mem, imm8 1100000w mod010 mem 3 to 5 are repeated: tmpcy ? cy, cy ? (mem) msb u (mem) ? (mem) 2 + tmpcy temp ? temp C 1 tmpcy ? cy, cy ? reg lsb reg ? reg ? 2 reg, 1 1101000w 11011 reg 2 reg msb ? tmpcy reg msb 1 bit after reg msb: v ? 1 reg msb = bit after reg msb: v ? 0 tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) ? 2 mem, 1 1101000w mod011 mem 2 to 4 (mem) msb ? tmpcy (mem) msb 1 bit after (mem) msb: v ? 1 (mem) msb = bit after (mem) msb: v ? 0 temp ? cl, while temp 1 0, the following operations are repeated: tmpcy ? cy, cy ? reg lsb reg, cl 1101001w 11011 reg 2 reg ? reg ? 2 u reg msb ? tmpcy temp ? temp C 1 rorc temp ? cl, while temp 1 0, the following operations are repeated: tmpcy ? cy, cy ? (mem) lsb mem, cl 1101001w mod011 mem 2 to 4 (mem) ? (mem) ? 2 u (mem) msb ? tmpcy temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are repeated: tmpcy ? cy, cy ? reg lsb reg, imm8 1100000w 11011 reg 3 reg ? reg ? 2 u reg msb ? tmpcy temp ? temp C 1 temp ? imm8, while temp 1 0, the following operations are repeated: tmpcy ? cy, cy ? (mem) lsb mem, imm8 1100000w mod011 mem 3 to 5 (mem) ? (mem) ? 2 u (mem) msb ? tmpcy temp ? temp C 1 rotate instructions instruction group m pd70433 123 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z near-proc 1 1 1 0 1 0 0 0 3 (sp C 1, sp C 2) ? pc, sp ? sp C 2 pc ? pc + disp regptr16 1 1 1 1 1 1 1 1 11010 reg 2 (sp C 1, sp C 2) ? pc, sp ? regptr16 sp ? sp C 2 call memptr16 1 1 1 1 1 1 1 1 mod 0 1 0 mem 2 to 4 (sp C 1, sp C 2) ? pc, sp ? sp C 2 pc ? (memptr16) (sp C 1, sp C 2) ? ps, (sp C 3, sp C 4) ? pc far-proc 1 0 0 1 1 0 1 0 5 sp ? sp C 4 pc ? seg, pc ? offset (sp C 1, sp C 2) ? ps, (sp C 3, sp C 4) ? pc memptr32 1 1 1 1 1 1 1 1 mod 0 1 1 mem 2 to 4 sp ? sp C 4 pc ? (memptr32 + 2), pc ? (memptr32) 11000011 1 pc ? (sp + 1, sp) sp ? sp + 2 pop-value 1 1 0 0 0 0 1 0 3 pc ? (sp + 1, sp) sp ? sp + 2, sp ? sp + pop-value ret pc ? (sp + 1, sp) 11001011 1 ps ? (sp + 3, sp + 2) sp ? sp + 4 pc ? (sp + 1, sp) pop-value 1 1 0 0 1 0 1 0 3 ps ? (sp + 3, sp + 2) sp ? sp + 4, sp ? sp + pop-value mem16 1 1 1 1 1 1 1 1 mod 1 1 0 mem 2 to 4 (sp C 1, sp C 2) ? (mem16) sp ? sp C 2 reg16 0 1 0 1 0 reg 1 (sp C 1, sp C 2) ? reg16 sp ? sp C 2 sreg 0 0 0 sreg 1 1 0 1 (sp C 1, sp C 2) ? sreg sp ? sp C 2 psw 10011100 1 (sp C 1, sp C 2) ? psw push sp ? sp C 2 r 0 1 1 0 0 0 0 0 1 push registers on the stack imm8 0 1 1 0 1 0 1 0 2 (sp C 1, sp C 2) ? imm8 sign extension sp ? sp C 2 imm16 0 1 1 0 1 0 0 0 3 (sp C 1, sp C 2) ? imm16 sp ? sp C 2 ds2 * 00001111 00111110 2 (sp C 1, sp C 2) ? ds2 sp ? sp C 2 instruction group stack manipulation instruction subroutine control instructions * this instruction is newly added to the v25 or v35. m pd70433 124 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z push ds3/vpc * 00001111 00110110 2 (sp C 1, sp C 2) ? ds3/vpc sp ? sp C 2 mem16 10001111 mod000 mem 2 to 4 sp ? sp + 2 (mem16) ? (sp C 1, sp C 2) reg16 01011 reg 1 sp ? sp + 2 reg16 ? (sp C 1, sp C 2) sreg 0 0 0 sreg 1 1 1 1 sp ? sp + 2 sreg : ss, ds0, ds1 sreg16 ? (sp C 1, sp C 2) pop psw 10011101 1 sp ? sp + 2 rrrrrr psw ? (sp C 1, sp C 2) r 01100001 1 pop registers from the stack ds2 * 00001111 00111111 2 sp ? sp + 2 ds2 ? (sp C 1, sp C 2) ds3/vpc * 00001111 00110111 2 sp ? sp + 2 ds3/vpc ? (sp C 1, sp C 2) prepare imm16, imm8 11001000 4 prepare new stack frame dispose 11001001 1 dispose of stack frame near-label 11101001 3 pc ? pc + disp short-label 11101011 2 pc ? pc + ext-disp8 regptr16 11111111 11100 reg 2 pc ? regptr16 br memptr16 11111111 mod100 mem 2 to 4 pc ? (memptr16) far-label 11101010 5 ps ? seg pc ? offset memptr32 11111111 mod101 mem 2 to 4 ps ? (memptr32 + 2) pc ? (memptr32) instruction group branch instruction stack manipulation instructions * this instruction is newly added to the v25 or v35. m pd70433 125 instruction group conditional branch instructions *1. this instruction is newly added to the v20 or v30. 2. this instruction is newly added to the v25 or v35. operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z bv short-label 0 1 1 1 0 0 0 0 2 if v = 1 pc ? pc + ext-disp8 bnv short-label 0 0 0 1 2 if v = 0 pc ? pc + ext-disp8 bc short-label 0 0 1 0 2 if cy = 1 pc ? pc + ext-disp8 bl bnc short-label 0 0 1 1 2 if cy = 0 pc ? pc + ext-disp8 bnl be short-label 0 1 0 0 2 if z = 1 pc ? pc + ext-disp8 bz bne short-label 0 1 0 1 2 if z = 0 pc ? pc + ext-disp8 bnz bnh short-label 0 1 1 0 2 if cy z = 1 pc ? pc + ext-disp8 bh short-label 0 1 1 1 2 if cy z = 0 pc ? pc + ext-disp8 bn short-label 1 0 0 0 2 if s = 1 pc ? pc + ext-disp8 bp short-label 1 0 0 1 2 if s = 0 pc ? pc + ext-disp8 bpe short-label 1 0 1 0 2 if p = 1 pc ? pc + ext-disp8 bpo short-label 1 0 1 1 2 if p = 0 pc ? pc + ext-disp8 blt short-label 1 1 0 0 2 if s v = 1 pc ? pc + ext-disp8 bge short-label 1 1 0 1 2 if s v = 0 pc ? pc + ext-disp8 ble short-label 1 1 1 0 2 if (s z) z = 1 pc ? pc + ext-disp8 bgt short-label 1 1 1 1 2 if (s v) z = 0 pc ? pc + ext-disp8 dbnzne short-label 1 1 1 0 0 0 0 0 2 cw = cw C 1 pc ? pc + ext-disp8 if z = 0 and cw 1 0 dbnze short-label 0 0 0 1 2 cw = cw C 1 pc ? pc + ext-disp8 if z = 1 and cw 1 0 dbnz short-label 0 0 1 0 2 cw = cw C 1 pc ? pc + ext-disp8 if cw 1 0 bcwz short-label 0 0 1 1 2 if cw = 0 pc ? pc + ext-disp8 btclr *1 sfr, imm3, 00001111 10011100 5 if (sfr) bit no. imm3 = 1: short-label pc ? pc + ext-disp8, (sfr) bit no.imm3 ? 0 btclrl *2 sfrl, imm3, 00001111 10011101 5 if (sfrl) bit no. imm3 = 1: short-label pc ? pc + ext-disp8, (sfrl) bit no.imm3 ? 0 m pd70433 126 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps 3 11001100 1 (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0 ps ? (15, 14), pc ? (13, 12) brk (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps imm8 11001101 2 (sp C 5, sp C 6) ? pc, sp ? sp C 6 ( 1 3) ie ? 0, brk ? 0 ps ? (n 4 + 3, n 4 + 2), pc ? (n 4 + 1, n 4) n = imm8 if v = 1: (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps brkv 11001110 1 (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0 ps ? (19, 18), pc ? (17, 16) reti 11001111 1 pc ? (sp + 1, sp), ps ? (sp + 3, sp + 2) rrrrrr psw ? (sp + 5, sp + 4), sp ? sp + 6 retrbi * 00001111 10010001 2 pc ? value of pc save area in currently selected bank r r rrrr register, psw ? value of psw save area in currently selected bank register fint * 00001111 10010010 2 indicates to interrupt controller incorporated in cpu that interrupt servicing has ended. if (mem32) > reg16 or (mem32 + 2) < reg16 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps chkind reg, mem32 01100010 mod reg mem 2 to 4 (sp C 5, sp C 6) ? pc, sp ? sp C 6 ie ? 0, brk ? 0 ps ? (23, 22), pc ? (21, 20) 00001111 00101101 brkcs * reg16 3 11000 reg 00001111 10010100 psw save area in currently selected register bank ? psw pc save area in currently selected register bank ? pc tsksw * reg16 3 rb3-0 ? reg16 low-order 4 bits 11111 reg psw ? value of psw save area in newly selected register bank pc ? value of pc save area in newly selected register bank if ch + cl 3 16: bw, dw ? ds1:iy output to transmit albit 00001111 10011010 2 buffer if ch + cl < 16: ch + cl ? ch, bw, dw ? bw u uuu part exceeding 16 bits: ch+clC16 ? ch, bw, dw ? bw stores 1 line pixel data change point information in coltrp 00001111 10011011 2 change point table (start white run length). mhenc 00001111 10010011 2 generates mh code from change point table. u uuu mrenc 00001111 10010111 2 generates mr code from change point table. u uuu instruction group interrupt instructions temp ? psw rb3 to 0 ? reg16 lowCorder 4 bits, ie ? 0, brk ? 0 psw save area in newly selected register bank ? temp pc save area in newly selected register bank ? pc * this instruction is newly added to the v20 or v30. dedicated fax instructions register bank switching instructions m pd70433 127 operation code flags mnemonic operand(s) bytes operation 76543210 76543210 ac cy v p s z scheol 00001111 01111000 2 "eol" detection in mh/mr code u uuu getbit 00001111 01111001 2 fetches pixel data start bit and sets it to cy flag. u uuu mhdec 00001111 01111100 2 generates change point table from mh code. u uuu mrdec 00001111 01111101 2 generates change point table from mr code. u uuu converts 1 line change point information in change cnvtrp 00001111 01111010 2 point table to pixel data. halt 11110100 1 cpu halt stop *1 00001111 10011110 2 cpu stop poll 10011011 1 poll and wait di 11111010 1 ie ? 0 ei 11111011 1 ie ? 1 buslock 11110000 1 bus lock prefix fp-op 11011xxx 11yyyzzz 2 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps fpo1 fp-op, mem 11011xxx modyyy mem 2 to 4 (sp C 5, sp C 6) ? pc C x *6 , sp ? sp C 6 fp-op 0110011x 11yyyzzz 2 ie ? 0, brk ? 0 fpo2 fp-op, mem 0110011x modyyy mem 2 to 4 pc ? (01dh; 01ch), ps ? (01fh, 01eh) nop 10010000 1 no operation 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 rstwdt *2 imm8, imm8 4 imm8 imm8 *4 0 0 1 sreg 1 1 0 1 segment override prefix ds2: *2 01100011 1 extended segment override prefix ds3: *2 11010110 1 extended segment override prefix iram: *2 11110001 1 register file override prefix instruction group dedicated fax instruc tions *3 *5 *1. this instruction is newly added to the v20 or v30. 2. this instruction is newly added to the v25 or v35. 3. watchdog timer manipulation instruction 4. four kinds: ds0:, ds1:, ps:, ss: 5. register file space access override prefix instruction 6. x: number of instruction bytes + number of prefixes when imm8 = imm8 wdm register ? imm8 when imm8 1 imm8 (sp C 1, sp C 2) ? psw, (sp C 3, sp C 4) ? ps (sp C 5, sp C 6) ? pc C x *6 , sp ? sp C 6 ie ? 0, brk ? 0 pc ? (20h, 21h), ps ? (22h, 23h) cpu control instructions 128 m pd70433 18. electrical specifications this section shows the electrical specifications of the v55pi tm using the three categories below. m pd70433gd/r/gj-12: m pd70433-12 m pd70433gd/r/gj-16: m pd70433-16 absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit v dd C0.5 to +7.0 v av dd C0.5 to v dd + 0.5 v supply voltage av ss C0.5 to +0.5 v av ref C0.5 to av dd + 0.3 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v one pin 4.0 ma output current low i ol total of all pins 100 ma one pin C1.0 ma output current high i oh total of all pins C20 ma operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c notes 1. the ic product output (or input/output) pins should not be directly connected between v dd , v cc or gnd. however, direct connection between the open-drain pins or betwen the open collector pins is possible. direct connection is also possible for an external circuit via timing design that avoids collision of output at pins which become high impedance. 2. exceeding the absolute maximum ratings even in one of the parameters even for an instant may affect the product quality. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore avoid using the product close to the rated values. the specifications and conditions shown in the dc characteristics and ac characteristics comprise the normal operation and guaranteed quality range. 129 m pd70433 dc characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %) parameter symbol test conditions min. typ. max. unit input voltage low v il1 *1 0 0.8 v v il2 *2 0 0.2v dd v input voltage high v ih1 *1 2.2 v dd v v ih2 *2 0.8v dd v dd v schmitt-triggered input threshold voltage v t + *3 , rise 3.3 v v t C *3 , fall 1.6 v schmitt-triggered input hysteresis width v t + C v t C *3 0.5 v output voltage low v ol i ol = 2.0 ma 0.45 v output voltage high v oh i oh = C0.4 ma v dd C1.0 v input leakage current i li 0 v v i v dd 10 m a output leakage current i lo 0 v v o v dd 10 m a v dd supply current *4 i dd1 operating mode 5.4f x + 30 5.4f x + 50 ma i dd2 halt mode 3.7 f x 3.7f x + 20 ma i dd3 stop mode 10 50 m a av dd supply current ai dd1 operating mode 1.5 2.5 ma ai dd2 halt mode 0.6 1 ma ai dd3 stop mode 10 50 m a * 1. other than *2 2. reset, p10/nmi, x1, p11/intp0 to p16/intp5, p30/txd0/so0/sb0, p31/rxd0/sb1/si0, p32/txc/sck0, p33/cts0, p35/rxd1/si1, p36/sck1/cts1 3. reset, p10/nmi, p11/intp0 to p16/intp5 4. the unit for the constants 5.4 and 3.7 is ma/mhz. capacitance (t a = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf unmeasured pins are output capacitance c o returned to 0 v. 20 pf i/o capacitance c io 20 pf operating conditions part number int. clock frequency operating temperature (t a ) supply voltage (v dd ) m pd70433-12 0.25 mhz f x 12.5 mhz C40 to +85 c +5.0 v 10 % m pd70433-16 0.25 mhz f x 12.5 mhz 130 m pd70433 recommended oscillation circuit the circuit shown below is recommended for a clock input. (1) ceramic resonator connection (t a = C40 to +85 ?c 10 %, v dd = 5 v 10 %) oscillator recommended constants manufacturer frequency product name f xx [mhz] c1 [pf] c2 [pf] murata mfg. co., ltd. 25 csa25.00mxz040 5 5 32 csa32.00mxz040 3 3 notes 1. the oscillator should be located as close to the x1 and x2 pins as possible. 2. other signal lines should not cross the dotted area. 3. when matching the m pd70433 with a resonator, careful evaluation is required. (2) crystal resonator connection (a) basic-wave recommended condition (t a = C10 to +70 ?c, v dd = 5 v 10 %) oscillator recommended constants manufacturer frequency product name f xx [mhz] c1 [pf] c2 [pf] r [ w ] kinseki 25 hcC49/uCs 5 5 200 10 10 C notes 1. the oscillator should be located as close to the x1 and x2 pins as possible. 2. other signal lines should not cross the dotted area. 3. when matching the m pd70433 with a resonator, careful evaluation is required. x2 x1 c2 c1 x2 x1 c2 c1 r 131 m pd70433 (b) 3rd-overtone recommended condition (t a = C20 to +70 ?c, v dd = 5 v 10 %) oscillator recommended constants manufacturer frequency product name f xx [mhz] c1 [pf] c2 [pf] c3 [pf] l [ m h] r [ w ] kinseki 25 hcC49/u 15 15 1000 3.3 100 32 10 5 1000 3.3 100 notes 1. the oscillator should be located as close to the x1 and x2 pins as possible. 2. other signal lines should not cross the dotted area. 3. when matching the m pd70433 with a resonator, careful evaluation is required. (3) external clock input x2 x1 c1 c2 l c3 r x1 x2 open 132 m pd70433 ac characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %) (1) m pd70433-12 parameter symbol test conditions min. max. unit x1 input cycle time 1 t cyx 40 250 ns x1 input high-level width 2 t wxh 15 ns x1 input low-level width 3 t wxl 15 ns x1 input rise time 4 t xr 10 ns x1 input fall time 5 t xf 10 ns clkout output cycle time 6 t cyk 80 4000 ns clkout output high-level width 7 t wkh 0.5t C 5 ns clkout output low-level width 8 t wkl 0.5t C 5 ns clkout output rise time 9 t kr 7ns clkout output fall time 10 t kf 7ns 11 t ir1 *1 10 ns input rise time 12 t ir2 *2 20 ns 13 t if1 *1 10 ns input fall time 14 t if2 *2 20 ns output rise time 15 t or 10 ns output fall time 16 t of 10 ns clkout delay time from x1 - 118 t dxk x2: open 18 ns address delay time from clkout - 17 t dka 527ns 18 t hka1 0ns address hold time (from clkout - ) 19 t hka2 0ns address float delay time from clkout - 20 t fka t hka1 36 ns address setup time (to astb )21t sast (n + 0.5)t C 25 ns address hold time (from astb )22t hsta 0.5t C 15 ns astb delay time from clkout 23 t dkstl 022ns astb - delay time from clkout 24 t dksth 022ns astb high-level width 25 t wsth (n + 1)t C 15 ns rd delay time from clkout - 26 t dkrl 022ns rd - delay time from clkout - 27 t dkrh 022ns rd low-level width 28 t wrl (n + 1.5)t C 15 ns rd delay time from address float 29 t farl 0ns address delay time from rd - 30 t dra 0.5t ns n : number of address wait states n : number of data wait states t: t cyk *1. other than *2 2. reset, p10 nmi, x1, p11/intp0 to p16/intp5, p30/txd0/so0/sb0, p31/r x d0/sb1/si0, p32/t x c/sck0, p33/ cts0, p35/r x d1/si1, p36/sck1/cts1 remark numbers in the symbol column correspond to numbers in the timing charts. 133 m pd70433 parameter symbol test conditions min. max. unit astb - delay time from rd - , iord - 119 t drsth 0ns rd - , iord - delay time from wrl - , wrh - , iowr - 120 t dwrh 0ns dex delay time from clkout 31 t dkdx 027ns dex hold time (from clkout )32t hkdx 0ns data input setup time (to clkout )33t sdk 11 ns data input hold time (from clkout )34t hkdr 0ns wr delay time from clkout 35 t dkwl 022ns wr - delay time from clkout 36 t dkwh 022ns wr low-level width 37 t wwl (n + 1)t C 12 ns data output delay time from clkout - 38 t dkd 327ns data output hold time (from clkout )39t hkdw 0ns astb - delay time from wr - 40 t dwsth 0ns ras delay time from clkout - 41 t dkral nt nt + 22 ns ras - delay time from clkout - 42 t dkrah 022ns ras high-level width 43 t wrah (n + 1)t C 15 ns ras - delay time from wrh , wrl 121 t dwrah (n + 0.5)t C 10 ns address setup time (to ras ) 122 t saral nt C 12 ns ready setup time (to clkout )44t sryhk 18 ns ready hold time (from clkout )45t hkryl 12 ns ready setup time (to clkout )46t srylk 18 ns ready hold time (from clkout )47t hkryh 12 ns 48 t wrsl1 stop release/power-on reset 30 ms reset low-level width 49 t wrsl2 system reset 1000 + 2t ns nmi high-level width 50 t wnih 5 m s nmi low-level width 51 t wnil 5 m s intpm setup time (to clkout )52t siqk m = 0 to 5 25 ns intpm high-level width 53 t wiqh m = 0 to 5 10t ns intpm low-level width 54 t wiql m = 0 to 5 10t ns poll setup time (to clkout )55t splk 25 ns hldrq setup time (to clkout )56t shqk 25 ns hldak delay time from clkout - 57 t dkha 027ns hldak delay time from bus float 58 t fcha 0ns bus output delay time from hldak - 59 t dhac t C 22.5 ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 134 m pd70433 parameter symbol test conditions min. max. unit hldak - delay time from hldrq 60 t dhqha 0.5t C 15 3.5t + 35 ns bus output delay time from hldrq 61 t dhqc 0.5t + 45 ns hldrq low-level width 62 t whql 2t ns hldak low-level width 63 t whal 3t C 10 ns buslock delay time from clkout - 64 t dkbl 027ns dmarqm setup time (to clkout )65t sdqk except demand release 25 ns mode; m = 0, 1 dmarqm high-level width 66 t wdqh except demand release 2t ns mode; m = 0, 1 dmarqm low-level width 67 t wdql except demand release 2t ns mode; m = 0, 1 dmarqm setup time (to clkout - )68t skdq demand release mode; 5 ns m = 0 or 1 dmarqm low-level hold time 69 t hkdq demand release mode; 12 ns (from clkout ) m = 0 or 1 dmaakm delay time from clkout - 70 t dkda m = 0 or 1 0 27 ns dmaakm low-level width 71 t wdal m = 0 or 1 (3 + n + n)t C 10 ns tcem delay time from clkout - 72 t dkte m = 0 or 1 0 27 ns tcem low-level width 73 t wtcl m = 0 or 1 t C 10 ns tout high-level width 74 t wtoh 8t C 10 ns tout low-level width 75 t wtol 8t C 10 ns wdtout low-level width 76 t wwtl 32t C 10 ns input 8t ns sck cycle time 77 t cysk output 8t C 10 ns input 4t C 10 ns sck high-level width 78 t wskh output 4t C 10 ns input 4t C 10 ns sck low-level width 79 t wskl output 4t C 10 ns si, sb setup time (to sck - )80t sssk 50 ns si, sb hold time (from sck - )81t hsks 150 ns 82 t dsksb1 ioe mode (cmos push-pull 0 90 ns output) so, sb delay time from sck 83 t dsksb2 sbi mode (open-drain 0 190 ns output, rl = 1 k w ) sb high-level hold time (from sck - )84t hsksb 4t ns sbi mode sb low-level setup time (to sck )85t ssbsk 4t ns sb high-level width 86 t wsbh 4t ns sb low-level width 87 t wsbl 4t ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 135 m pd70433 parameter symbol test conditions min. max. unit cts high-level width 88 t wcth 2t ns cts low-level width 89 t wctl 2t ns transmit/receive data cycle 90 t cyd uart 32t ns t x c output clock cycle 91 t cyc 32t ns t x c output clock high-level width 92 t wch 16t C 10 ns t x c output clock low-level width 93 t wcl uart 16t C 10 ns t x d delay time from t x c 94 t dtctd 090ns t x d delay time from cts 95 t dcttd 2t cyc ns datastb setup time 96 t sdsk input mode 25 ns 97 t wdsl1 input mode 2t ns datastb low-level width 98 t wdsl2 output mode 2t C 10 512t ns pd setup time (to datastb )99t spdds1 input mode 45 ns (datastb latch mode) pd hold time (from datastb ) 100 t hdspd1 4t ns busy delay time from datastb 101 t ddsby1 4t ns pd setup time (to datastb - ) 102 t spdds2 input mode 45 ns (datastb - latch mode) pd hold time (from datastb - ) 103 t hdspd2 4t ns busy delay time from datastb - 104 t ddsby2 4t ns datastb delay time from pd 105 t dpddsl 2t C 30 512t ns datastb setup time (to ack ) 106 t sdsak 0ns ack input low-level width 107 t wakl output mode 2t ns datastb setup time (to busy - ) 108 t sdsby 0ns busy input high-level width 109 t wbyh 2t ns port output delay time (from clkout ) 123 t dkp 850ns port input setup time (to clkout ) 124 t spk 25 ns port input hold time (from clkout ) 125 t hkp 16 ns dmarqm high-level hold time 126 t hstdq demand release 0 ns (from astb ) mode; m = 0 or 1 refrq delay time from clkout - 127 t dkrel 025ns refrq - delay time from clkout - 128 t dkreh 025ns ras delay time from refrq 129 t drera nt C 5 ns rd delay time from astb 130 t dstlrl 0.5t C 5 ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 136 m pd70433 (2) m pd70433-16 parameter symbol test conditions min. max. unit x1 input cycle time 1 t cyx 31.25 250 ns x1 input high-level width 2 t wxh 12 ns x1 input low-level width 3 t wxl 12 ns x1 input rise time 4 t xr 5ns x1 input fall time 5 t xf 5ns clkout output cycle time 6 t cyk 62.5 4000 ns clkout output high-level width 7 t wkh 0.5t C 5 ns clkout output low-level width 8 t wkl 0.5t C 5 ns clkout output rise time 9 t kr 5ns clkout output fall time 10 t kf 5ns 11 t ir1 *1 10 ns input rise time 12 t ir2 *2 20 ns 13 t if1 *1 10 ns input fall time 14 t if2 *2 20 ns output rise time 15 t or 10 ns output fall time 16 t of 10 ns clkout delay time from x1 118 t dxk x2: open 18 ns address delay time from clkout - 17 t dka 527ns 18 t hka1 0ns address hold time (from clkout - ) 19 t hka2 0ns address float delay time from clkout - 20 t fka t hka1 36 ns address setup time (to astb )21t sast (n + 0.5)t C 25 ns address hold time (from astb )22t hsta 0.5t C 15 ns astb delay time from clkout 23 t dkstl 022ns astb - delay time from clkout 24 t dksth 022ns astb high-level width 25 t wsth (n + 1)t C 15 ns rd delay time from clkout - 26 t dkrl 022ns rd - delay time from clkout 27 t dkrh 022ns rd low-level width 28 t wrl (n + 1.5)t C 15 ns rd delay time from address float 29 t farl 0ns address delay time from rd - 30 t dra 0.5t ns n : number of address wait states n : number of data wait states t: t cyk *1. other than *2 2. reset, p10 nmi, x1, p11/intp0 to p16/intp5, p30/txd0/so0/sb0, p31/r x d0/sb1/si0, p32/t x c/skc0, p33/ cts0, p35/r x d1/si1, p36/sck1/cts1 remark numbers in the symbol column correspond to numbers in the timing charts. 137 m pd70433 parameter symbol test conditions min. max. unit astb - delay time from rd - , iord - 119 t drsth 0ns rd - , iord - delay time from wrl - , wrh - , iowr - 120 t dwrh 0ns dex delay time from clkout 31 t dkdx 027ns dex hold time (from clkout )32t hkdx 0ns data input setup time (to clkout )33t sdk 11 ns data input hold time (from clkout )34t hkdr 0ns wr delay time from clkout 35 t dkwl 022ns wr - delay time from clkout 36 t dkwh 022ns wr low-level width 37 t wwl (n + 1)t C 12 ns data output delay time from clkout - 38 t dkd 327ns data output hold time (from clkout )39t hkdw 0ns astb - delay time from wr - 40 t dwsth 0ns ras delay time from clkout - 41 t dkral nt nt + 22 ns ras - delay time from clkout - 42 t dkrah 022ns ras high-level width 43 t wrah (n + 1)t C 15 ns ras - delay time from wrh , wrl 121 t dwrah (n + 0.5)t C 10 ns address setup time (to ras ) 122 t saral nt C 12 ns ready setup time (to clkout )44t sryhk 18 ns ready hold time (from clkout )45t hkryl 12 ns ready setup time (to clkout )46t srylk 18 ns ready hold time (from clkout )47t hkryh 12 ns 48 t wrsl1 stop release/power-on reset 30 ms reset low-level width 49 t wrsl2 system reset 1000 + 2t ns nmi high-level width 50 t wnih 5 m s nmi low-level width 51 t wnil 5 m s intpm setup time (to clkout )52t siqk m = 0 to 5 25 ns intpm high-level width 53 t wiqh m = 0 to 5 10t ns intpm low-level width 54 t wiql m = 0 to 5 10t ns poll setup time (to clkout )55t splk 25 ns hldrq setup time (to clkout )56t shqk 25 ns hldak delay time from clkout - 57 t dkha 027ns hldak delay time from bus float 58 t fcha 0ns bus output delay time from hldak - 59 t dhac t C 22.5 ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 138 m pd70433 parameter symbol test conditions min. max. unit hldak - delay time from hldrq 60 t dhqha 0.5t C 15 3.5t + 35 ns bus output delay time from hldrq 61 t dhqc 0.5t + 45 ns hldrq low-level width 62 t whql 2t ns hldak low-level width 63 t whal 3t C 10 ns buslock delay time from clkout - 64 t dkbl 027ns dmarqm setup time (to clkout )65t sdqk except demand release 25 ns mode; m = 0 or 1 dmarqm high-level width 66 t wdqh except demand release 2t ns mode; m = 0 or 1 dmarqm low-level width 67 t wdql except demand release 2t ns mode; m = 0 or 1 dmarqm setup time (to clkout - )68t skdq demand release mode; 5 ns m = 0 or 1 dmarqm low-level hold time 69 t hkdq demand release mode; 12 ns (from clkout ) m = 0 or 1 dmaakm delay time from clkout - 70 t dkda m = 0 or 1 0 27 ns dmaakm low-level width 71 t wdal m = 0 or 1 (3 + n + n)t C 10 ns tcem delay time from clkout - 72 t dkte m = 0 or 1 0 27 ns tcem low-level width 73 t wtcl m = 0 or 1 t C 10 ns tout high-level width 74 t wtoh 8t C 10 ns tout low-level width 75 t wtol 8t C 10 ns wdtout low-level width 76 t wwtl 32t C 10 ns input 8t ns sck cycle time 77 t cysk output 8t C 10 ns input 4t C 10 ns sck high-level width 78 t wskh output 4t C 10 ns input 4t C 10 ns sck low-level width 79 t wskl output 4t C 10 ns si, sb setup time (to sck - )80t sssk 50 ns si, sb hold time (from sck - )81t hsks 150 ns 82 t dsksb1 ioe mode (cmos push-pull 0 90 ns output) so, sb delay time from sck 83 t dsksb2 sbi mode (open-drain 0 190 ns output, rl = 1 k w ) sb high-level hold time (from sck - )84t hsksb 4t ns sbi mode sb low-level setup time (to sck )85t ssbsk 4t ns sb high-level width 86 t wsbh 4t ns sb low-level width 87 t wsbl 4t ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 139 m pd70433 parameter symbol test conditions min. max. unit cts high-level width 88 t wcth 2t ns cts low-level width 89 t wctl 2t ns transmit/receive data cycle 90 t cyd uart 32t ns t x c output clock cycle 91 t cyc 32t ns t x c output clock high-level width 92 t wch 16t C 10 ns t x c output clock low-level width 93 t wcl uart 16t C 10 ns t x d delay time from t x c 94 t dtctd 090ns t x d delay time from cts 95 t dcttd 2t cyc ns datastb setup time 96 t sdsk input mode 25 ns 97 t wdsl1 input mode 2t ns datastb low-level width 98 t wdsl2 output mode 2t C 10 512t ns pd setup time (to datastb )99t spdds1 input mode 45 ns (datastb latch mode) pd hold time (from datastb ) 100 t hdspd1 4t ns busy delay time from datastb 101 t ddsby1 4t ns pd setup time (to datastb - ) 102 t spdds2 input mode 45 ns (datastb - latch mode) pd hold time (from datastb - ) 103 t hdspd2 4t ns busy delay time from datastb - 104 t ddsby2 4t ns datastb delay time from pd 105 t dpddsl 2t C 30 512t ns datastb setup time (to ack ) 106 t sdsak 0ns ack input low-level width 107 t wakl output mode 2t ns datastb setup time (to busy - ) 108 t sdsby 0ns busy input high-level width 109 t wbyh 2t ns port output delay time (from clkout ) 123 t dkp 850ns port input setup time (to clkout ) 124 t spk 25 ns port input hold time (from clkout ) 125 t hkp 16 ns dmarqm high-level hold time 126 t hstdq demand release 0 ns (from astb ) mode; m = 0 or 1 refrq delay time from clkout - 127 t dkrel 025ns refrq - delay time from clkout - 128 t dkreh 025ns ras delay time from refrq 129 t drera nt C 5 ns rd delay time from astb 130 t dstlrl 0.5t C 5 ns ti high-level width 131 t wtih 4t ns ti low-level width 132 t wtil 4t ns tom setup time (to clkout ) 133 t dkt m = 00, 01, 20, 21, 30 5 30 ns n : number of address wait states n : number of data wait states t: t cyk remark numbers in the symbol column correspond to numbers in the timing charts. 140 m pd70433 a/d converter characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %, av ss = 0 v, v dd C 0.5 v av dd v dd ) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error *1 3.4 v av ref av dd 0.8 % 4.5 v av ref av dd 0.6 % quantization error 1/2 lsb conversion time 80 ns t 125 ns (for m pd70433, 70433-12) 160t ns t conv 65 ns t 125 ns (for m pd70433-16) 125 ns t 250 ns 120t ns sampling time 80 ns t 125 ns (for m pd70433, 70433-12) 32t ns t samp 65 ns t 125 ns (for m pd70433-16) 125 ns t 250 ns 24t ns analog input voltage v ian C0.3 av ref + 0.3 v analog input impedance r an non-sampling 1000 m w sampling *2 reference voltage av ref 3.4 av dd v av ref current ai ref t = 80 ns 1.5 5.0 ma t: t cyk *1. excluding quantization error 2. analog input impedance is identical with the equivalent circuit shown below. (the values in the figure are not guaranteed, but are typ. values) data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. max. unit data retention supply voltage 115 v dddr 2.5 5.5 v supply voltage rise time 116 t rvd 200 m s supply voltage fall time 117 t fvd 200 m s remark numbers in the symbol column correspond to number in the timing chart. analog input pin 30 pf (input capacitance included) 5 pf 20 k w 141 m pd70433 0.8v dd 0.8 v 0.8v dd 0.8 v test points v dd 0.4 v 14 12 ac test input waveform *1 2.2 v 0.8 v 2.2 v 0.8 v test points 2.4 v 0.4 v 13 11 *1. except *2 ac test input waveform *2 *2. reset, p10/nmi, x1, p11/intp0 to p16/intp5, p30/txd0/so0/sb0, p31/rxd0/sb1/si0, p32/txc/sck0, p33/cts0, p35/r x d1/si1, p36/sck1/cts1 ac test output test points note if the load capacitance exceeds 100 pf due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pf or less by insertion of a buffer, etc. remark dut: measured device 2.2 v 0.8 v 2.2 v 0.8 v test points load conditions dut c l = 100 pf 142 m pd70433 clock input/output timing output waveform (except clkout) 2.2 v 0.8 v 2.2 v 0.8 v 16 15 1 2 3 4 5 9 118 10 7 8 6 x1 clkout 0.8 v dd 0.8 v 2.2 v 0.8 v 143 m pd70433 read timing *1. only activated when memory block 1 or 4 (set by the mbs register) is accessed. 2. only valid when the external bus width is 16 bits. remark the dotted line indicates high-impedance. clkout a16-a23, ad8-ad15 (with 8-bit external bus) ad0-ad7, ad8-ad15 (with 16-bit external bus) astb ras *1 rd, iord wrl, wrh, iowr dex *2 t1 t2 t3 address address data 17 20 19 18 29 33 34 21 22 24 25 30 23 42 43 122 130 41 26 119 27 28 31 30 32 144 m pd70433 write timing *1. only activated when memory block 1 or 4 (set by the mbc register) is accessed. 2. only valid when the external bus width is 16 bits. remark the dotted line indicates high-impedance. clkout a16-a23, ad8-ad15 (with 8-bit external bus) ad0-ad7, ad8-ad15 (with 16-bit external bus) astb ras *1 rd, iord wrl, wrh, iowr dex *2 t1 t2 t3 17 19 18 38 39 21 22 24 122 23 42 43 121 41 35 40 36 37 32 31 data 25 address address 145 m pd70433 refresh timing * only valid when the external bus width is 16 bits. remark the dotted line indicates high-impedance. clkout a16-a23, ad8-ad15 (with 8-bit external bus) ad0-ad7, ad8-ad15 (with 16-bit external bus) astb ras rd, iord wrl, wrh, iowr t1 t2 t3 17 19 18 21 22 122 23 42 43 41 36 address address 20 27 31 dex * 32 25 129 127 128 refrq 24 146 m pd70433 ready input timing (1) 1 data wait inserted 44 45 t1 t2 tw 1 t3 clkout ready (2) 2 data waits inserted 47 46 44 45 t1 t2 tw 1 tw 2 t3 clkout ready (3) n data waits inserted (n 3 3) remark the ready input becomes valid when the corresponding field of the pwcn register (n = 0 or 1) is other than "00" (binary). 47 46 44 45 t1 t2 tw n? tw n t3 clkout ready tw n? 147 m pd70433 dma timing (external memory ? external i/o) *1. only activated when a dma transfer is performed on memory block 1 or 4 (set by the mbc register). 2. the bus is activated at the last transfer in intelligent dma mode-2, 2-channel operating mode (stop in termina- tion), or memory-to-memory transfer mode (stop in termination). 3. only valid when the external bus width is 16 bits. remark the dotted line indicates high-impedance. t1 t2 t3 19 17 20 18 22 24 30 25 23 42 43 119 30 29 41 26 28 35 120 36 70 37 70 71 72 73 32 31 clkout a16-a23, ad8-ad15 (with 8-bit external bus) ad0-ad7, ad8-ad15 (with 16-bit external bus) astb ras *1 rd wrl, wrh, iord iowr dmaak0, dmaak1 tce0, *2 tce1 dex *3 address address 27 122 130 148 m pd70433 dma timing (external i/o ? external memory) t1 t2 t3 17 122 130 clkout a16-a23, ad8-ad15 (with 8-bit external bus) ad0-ad7, ad8-ad15 (with 16-bit external bus) astb ras *1 rd, iowr wrl, wrh iord dmaak0, dmaak1 tce0, *2 tce1 dex *3 20 19 address address 18 21 22 24 30 43 42 23 25 41 121 40 36 35 37 30 120 27 70 71 28 26 70 72 31 73 32 29 *1. only activated when a dma transfer is performed on memory block 1 or 4 (set by the mbc register). 2. the bus is activated at the last transfer in intelligent dma modeC2, 2Cchannel operating mode (stop in termina- tion), or memory-to-memory transfer mode (stop in termination). 3. only valid when the external bus width is 16 bits. remark the dotted line indicates high-impedance. 149 m pd70433 inrpm input timing (m = 0 to 5) nmi input timing poll input timing 52 clkout 53 54 52 intp0-intp5 clkout 50 51 nmi 55 clkout 55 poll 150 m pd70433 dmarqm input timing (m = 0 or 1) (1) in demand release mode (i/o-to-memory transfer) (a) address wait not inserted (b) address wait inserted (2) in the mode other than demand release mode clkout dmaak0, dmaak1 70 70 69 68 68 astb dmarq0, dmarq1 t1 t2 t3 t1 t2 t3 126 clkout dmaak0, dmaak1 70 70 69 68 68 astb dmarq0, dmarq1 taw t2 t3 126 t1 taw t2 t3 t1 65 clkout 66 67 65 dmarq0, dmarq1 151 m pd70433 timer output timing wdtout output timing buslock output timing data retention timing (stop mode) wdtout 76 v dd 115 117 116 clkout buslock 64 64 131 clkout to00, to01, to20 to21, to30 ti1 132 133 133 75 74 152 m pd70433 hold request/acknowledge timing (1) in normal mode * astb, rd, wrh, wrl, dex, ras, buslock, iord, iowr, ad0 to ad15, a16 to a23 (2) release of hold mode for refresh cycle insertion * astb, rd, wrh, wrl, dex, ras, buslock, iord, iowr, ad0 to ad15, a16 to a23 clkout hldrq bus control signal * hldak 56 56 57 62 hi-z 60 59 58 63 clkout 56 62 61 57 hldrq bus control signal * hldak hi-z 153 m pd70433 reset input timing (1) stop mode release/power-on reset (2) system reset ctsm input timing (m = 0 or 1) clkout reset 48 clkout reset 49 cts0, cts1 88 89 154 m pd70433 serial interface timing (1) 3-wire serial i/o mode (2) sbi mode bus release signal transfer timing command signal transfer timing 84 sck0 sb0, sb1 87 86 85 84 sck0 sb0, sb1 85 77 83 80 81 79 78 input/output data 79 78 77 82 80 81 sck0, sck1 si0, si1 so0, so1 output data input data 155 m pd70433 (3) uart mode transmit timing receive timing transmission enale timing 90 t c t d0 t d1 output data output data 90 94 91 92 93 90 r d0, r d1 input data 95 cts0, cts1 t d0, t d1 start bit 156 m pd70433 parallel interface timing (1) input mode (2) output mode 96 clkout datastb pd0?d7 busy input data 97 99 100 103 102 101 104 105 datastb pd0?d7 ack busy output data 98 106 107 108 109 157 m pd70433 port input/output timing 124 125 123 t2/ti t3 t1/ti clkout input port output port 158 m pd70433 (t a = 25 ?, v dd = 5.0 v) ?.0 ?.0 ?.0 0 0 0.2 0.4 0.6 high-level output current i oh [ma] supply voltage ?high-level output voltage v dd ?v oh [v] (t a = 25 ?, v dd = 5.0 v) 6.0 4.0 2.0 0 0 0.2 0.4 0.6 low-level output current i ol [ma] low-level output volta g e v ol [ v ] 19. characteristic curves (for reference only) i oh vs (v dd C v oh ) i ol vs v ol 159 m pd70433 20. package drawings n a m f b k l 120 pin plastic qfp ( 28) 120 1 31 d c p 30 91 60 90 61 detail of lead end s q 55 m i h j g p120gd-80-5bb-3 item millimeters inches a b c d f g h i j k l 32.0 0.4 28.0 0.2 2.4 0.35 0.10 0.15 28.0 0.2 1.260 0.016 0.094 0.094 0.006 0.031 (t.p.) 1.102 note m n 0.10 0.15 2.0 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.079 0.014 1.102 0.8 0.2 0.031 p 3.7 0.146 1.260 0.016 32.0 0.4 2.4 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 4.0 max. 0.157 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.009 ?.008 160 m pd70433 120 pin plastic qfp (fine pitch) ( 20) item millimeters inches a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 22.0?.2 0.866?.008 b 20.0?.2 0.787 +0.009 ?.008 c 20.0?.2 0.787 +0.009 ?.008 s120gj-50-3eb-2 s 3.0 max. 0.119 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 2.7 0.106 q 0.125?.075 0.005?.003 +0.03 ?.07 b c d j h i g f p n l k m q r r 55 55 detail of lead end d f 2.75 22.0?.2 0.866?.008 0.108 g 2.75 0.108 h 0.22 0.009?.002 i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) +0.05 ?.04 +0.001 ?.003 m 130 90 61 31 60 120 91 161 m pd70433 a d index mark orientation pin e m f m k l i h g j pnmlk jhgfedcba 14 13 12 11 10 9 8 7 6 5 4 3 2 1 f x132r-100a-1 item millimeters inches note each lead centerline is located within 0.5 mm ( 0.020 inch) of its true position (t.p.) at maximum material condition. a d e f g h i j k l m 35.56 0.3 35.56 0.3 1.27 2.54 (t.p.) 2.8 0.3 0.9 min. 2.95 4.57 max. 1.2 0.2 0.46 0.05 0.254 1.400 0.012 1.400 0.012 0.050 0.100 (t.p.) 0.110 0.012 0.035 min. 0.116 0.180 max. 0.047 0.018 0.002 0.010 f f f f f f 132 pin ceramic pga (bottom view) +0.009 ?.008 162 m pd70433 * for the storage period after dry-pack decompression, storage conditions are max. 25 c, 65 % rh. note use of more than one soldering method should be avoided (except in the case of partial heating method). (2) m pd70433gj-xx-3eb : 120-pin plastic qfp (fine pitch) (20 20 mm) 21. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, contact our sales personnel. table 21-1. surface mount type soldering conditions (1) m pd70433gd-xx-5bb : 120-pin plastic qfp (28 28 mm) soldering method soldering conditions recommended condition symbol package peak temperature: 235 c, duration: 30 sec. max. (at 210 c infrared reflow or above), number of times: within twice, time limit: 7 days* ir35-367-2 (thereafter 36 hours 125 c prebanking required) package peak temperature: 215 c, duration: 40 sec. max. (at 200 c vps or above), number of times: within twice, time limit: 7 days* vp15-367-2 (thereafter 36 hours 125 c prebanking required) solder bath temperature: 260 c or less, time: 10 sec. max., wave soldering number of times: once, time limit: 7 days* (thereafter 35 hours ws60-367-1 125 c prebanking required), preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or below, duration: 3 sec. max. (per pin row) CCC soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c ir35-00-2 or above), number of times: within twice vps package peak temperature: 215 c, duration: 40 sec. max. (at 200 c vp15-00-2 or above), number of times: within twice partial heating pin temperature: 300 c or below, duration: 3 sec. max. (per pin row) CCC note use of more than one soldering method should be avoided (except in the case of partial heating method). soldering method soldering conditions wave soldering solder temperature: 260 c or less, duration: 10 sec. max. (lead part only) partial heating pin temperature: 300 c or less, duration: 3 sec. max. (per pin row) table 21-2. insertion type soldering conditions m pd70433r-xx : 132-pin ceramic pga note wave soldering is used on the lead part only, and care must be taken to prevent solder from coming into direct contact with the body. 163 m pd70433 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 164 m pd70433 [memo] 165 m pd70433 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m pd70433 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 v20, v30, v25, v35, v25+, v55pi are trademarks of nec corporation. the documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. |
Price & Availability of UPD70433R-12
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |