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d a t a sh eet product specification supersedes data of 25th august 1999 2001 may 30 rev.3 discrete ceramics class 1, np0 50 v feedthrough surface-mount ceramic multilayer capacitors www.phycomp-components.com
2001 may 30 rev.3 2 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough features ? high capacitance per unit volume ? supplied in tape on reel or in bulk ? for high frequency applications ? nisn terminations. applications ? consumer electronics ? telecommunications ? automotive ? data processing. description the capacitor consists of a rectangular block of ceramic dielectric in which a number of interleaved precious metal electrodes are contained. this structure gives rise to a high capacitance per unit volume. the inner electrodes are connected to the four terminations, silver dipped with a barrier layer of plated nickel and finally covered with a layer of plated tin (nisn). a 3d diagram of the structure is shown in fig.1. quick reference data description value rated voltage u r (dc) 50 v (iec) capacitance range (e12 series) 47 pf to 1 nf tolerance on capacitance 10%; 5% test voltage (dc) for 1 minute 2.5 u r sectional specifications iec 60384-10, second edition 1989-04; also based on cecc 32 100 detailed specification based on cecc 32 101-801 climatic category (iec 60068) 55/125/56 handbook, halfpage electrodes terminations ccc033 fig.1 construction of a feedthrough capacitor.
2001 may 30 rev.3 3 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough mechanical data physical dimensions table 1 capacitor dimensions in millimetres table 2 dimensions of solder lands in millimetres case size l w t a b c p 1206 3.2 0.20 1.6 0.20 0.80 0.10 0.50 0.20 0.30 0.15 0.90 0.20 1.60 0.15 abcde f 4.45 0.20 1.65 0.20 1.00 0.15 0.90 0.20 1.00 0.15 0.70 0.10 fig.2 physical dimensions. for dimensions see tables 1 and 2. a b w b t l d d e c f a c p ccb960 a. outline. b. dimensions of solder lands.
2001 may 30 rev.3 4 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough selection chart thickness classification and packing quantities ordering information components may be ordered by using either a simple 15-digit clear text code or phycomp?s unique 12nc. clear text code e xample : 1206cg102j9b20f ordering code 12nc c (pf) last two digits of 12nc 50 v 1206 47 32 100 36 220 41 0.8 0.1 330 43 470 45 1000 49 thickness classification (mm) 8mm tape width quantity per reel ? 180 mm; 7" paper 0.8 0.1 4 000 size code temp. char. capacitance tol. voltage termination packing marking series 1206 cg = np0 102 = 1000 pf; the third digit signifies the multiplying factor: 0= 1 1= 10 2= 100 j= 5% k= 10% 9 = 50 v b = nisn 2 = 180 mm; 7" paper a = bulk 0 = no marking f = feedthrough (1) refer to chapter ?selection chart?. (2) quantity on reel depends on thickness classification, see section ?thickness classification and packing quantities?. handbook, full pagewidth 2 2 x x x x x x 1 x x x carrier type 55 paper rated voltage - termination 23 50 v; ni-barrier size 1 1206 feedthrough capacitance value (1) tolerance 5 6 5% 10% packaging (2) 1 0 reel: ? 180 mm; 7" bulk (loose in bag, 1000 units) ccc009
2001 may 30 rev.3 5 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough electrical characteristics class 1 capacitors; np0 dielectric; nisn terminations unless otherwise stated all electrical values apply at an ambient temperature of 23 3 c, an atmospheric pressure of 86 to 106 kpa, and a relative humidity of 63 to 67%. note 1. measured at 1 v, 1 mhz for c 1000 pf and 1 v, 1 khz for c > 1 000 pf, using a four-gauge method. description value capacitance range (e12 series) 47 pf to 1 nf tolerance on capacitance 10%; 5% rated voltage u r (dc) 50 v test voltage (dc) for 1 minute 2.5 u r tan ; note 1 10 10 ? 4 insulation resistance after 1 minute at u r (dc) r ins >10 5 m ? rated dc resistance 1 ? max.
2001 may 30 rev.3 6 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough fig.3 typical capacitance change with respect to the capacitance at 1 v as a function of dc voltage. handbook, halfpage 15 5 ? 5 ? 15 mea614 0102030 10 0 ? 10 40 50 v dc (v) ? c (%) c fig.4 typical tan as a function of temperature. mea608 7.5 5 2.5 0 ? 40 0 40 80 120 t ( c) o tan (x 10 ) ? 4 10 fig.5 typical capacitance change as a function of temperature. handbook, halfpage 40 40 40 mea607 20 0 20 0 40 80 120 t ( c) o tc (x10 /k) 6
2001 may 30 rev.3 7 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough fig.6 insertion loss characteristics. handbook, full pagewidth ? 80 20 0 10 4 ccb961 10 3 10 2 10 ? 60 ? 40 ? 20 attenuation (db) f (hz) ftc normal cmc
2001 may 30 rev.3 8 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough high frequency behaviour of multilayer chip capacitors multilayer chip capacitors (mlccs) are suitable for use at high frequencies. at frequencies below the series resonance frequency, the mlcc can be represented by an equivalent circuit as shown in fig.7. in general, the quantities c, esr and l are frequency dependent. for most applications, c and l can be regarded as frequency independent below 1 ghz. the equivalent series self-inductance l is: ? independent of the dielectric material. ? dependent on the size of the capacitor, it increases with increasing length and decreases with increasing width or thickness of the product. ? the value of l is approximately: ? 0.6 nh for case size 0603 ? 1 nh for case sizes 0805, 1206 and 1210 ? 1.5 nh for case sizes 1812 and 2220. these figures are accurate to within 20%. because of the inductance l, associated with the mlcc, there will be a frequency at which the inductive reactance will be equal to the reactance of the capacitor. this is known as the series resonance frequency (srf) and is given by: at the srf, the mlcc will appear as a small resistor. the transmission loss through the mlcc at this series resonance frequency will be low. using the values of c, l = 1 nh and the esr at a specific frequency (f), two often used quantities can be derived. the impedance (z) is given by: the quality factor (q) is given by: srf 1 2 lc ------------------- = z 1 2 f () 2 ? lc 2j fc ------------------------------------ esr + = q 12 f ) 2 lc ( ? 2 fesrc -------------------------------------- = fig.7 equivalent series representation of a mlcc. c = capacitance. esr = equivalent series resistance which is determined by the energy dissipation mechanisms (in the dielectric material as well as in the electrodes). l = equivalent series self-inductance. mea609 c esr l
2001 may 30 rev.3 9 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough figures 9 and 10 show the comparative inductance of a conventional mlcc and an ftc, when the capacitor is mounted on a substrate. the high frequency capability of the ftc is better than a conventional mlcc due to the inductance of an ftc being less than the mlcc. fig.8 impedance of ftc as a function of frequency. handbook, full pagewidth 10 ? 2 10 2 10 3 10 10 4 1 10 ? 1 ccb962 10 6 10 8 10 9 10 10 10 7 f (hz) z ( ? ) 47 pf 100 pf 220 pf 330 pf 470 pf 1 nf fig.9 inductance of lmcc. handbook, halfpage l3 l1 l2 c1 l3 ccb963 fig.10 inductance of ftc. handbook, halfpage l3 c1 l3 l1 l2 ccb964 the equivalent circuits show parasitic inductances l1, l2 and l3. the resonance frequency (f r ) can be determined as follows: (l g = inductance between signal through line and gen). the inductance of the ftc (l gftc = l3//l3 = ) is one quarter that of the mlcc (l gcmc =l3+l3=l3 2). f r 1 2 l g c1 ------------------------------- - = l3 2 ------ -
2001 may 30 rev.3 10 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough tests and requirements table 3 test procedures and requirements iec 60384-10/ cecc 32 100 clause iec 60068-2 test method test procedure requirements 4.4 mounting the capacitors may be mounted on printed-circuit boards or ceramic substrates by applying wave soldering, reflow soldering (including vapour phase soldering) or conductive adhesive no visible damage 4.5 visual inspection and dimension check any applicable method using 10 magnification in accordance with specification 4.6.1 capacitance f = 1 mhz; measuring voltage 1v rms at 20 c within specified tolerance measured 1000 hours after date of manufacture 4.6.2 tan f = 1 mhz; measuring voltage 1v rms at 20 c in accordance with specification 4.6.3 insulation resistance at u r (dc) for 1 minute in accordance with specification 4.6.4 voltage proof 2.5 u r for 1 minute no breakdown or flashover 4.7.1 temperature coefficient between minimum and maximum temperature in accordance with specification 4.8 adhesion a force of 5 n applied for 10 s to the line joining the terminations and in a plane parallel to the substrate no visible damage 4.9 bond strength of plating on end face mounted in accordance with cecc 32 100, paragraph 4.4 no visible damage conditions: bending 1 mm at a rate of 1 mm/s, radius jig 340 mm ? c/c: 10% 4.10 tb resistance to soldering heat; jig clamps to the second component along the longitudinal line 260 5 c for 10 0.5 s in a static solder bath the terminations shall be well tinned after recovery ? c/c: 0.5% or 0.5 pf whichever is greater resistance to leaching; jig clamps to the second component along the longitudinal line 260 5 c for 30 1s in a static solder bath using visual enlargement of 10, dissolution of the terminations shall not exceed 10%
2001 may 30 rev.3 11 www.phycomp-components.com phycomp product specification surface-mount ceramic multilayer capacitors class 1, np0 50 v feedthrough 4.11 ta solderability; jig clamps to the second component along the longitudinal line zero hour test, and test after storage (20 to 24 months) in original packing in normal atmosphere; unmounted chips completely immersed for 2 0.5 s in a solder bath at 235 5 c the terminations shall be well tinned 95% 4.12 na rapid change of temperature preconditioning, class 2 only; 5 cycles in the following sequence: 30 minutes at ? 55 c, change within 30 minutes to + 125 c no visible damage after 24 hours recovery: ? c/c: 1% or 1pf 4.14 ca damp heat preconditioning, class 2 only: 56 days at 40 c; 90 to 95% rh; u r applied; 30 minutes at ? 55 c, change within 30 minutes to + 125 c no visual damage after 1 to 2 hours recovery: ? c/c: 2% or 1pf, whichever is greater tan : 2 specified value r ins : 2500 m ? or r i c r 25 s, whichever is less 4.15 endurance preconditioning, class 2 only (thermal treatment): 1000 hours at 125 c and 2 u r applied no visual damage after 1 to 2 hours recovery: ? c/c: 2% or 1 pf, whichever is greater tan : 2 specified value r ins : 4000 m ? or r i c r 40 s, whichever is less iec 60384-10/ cecc 32 100 clause iec 60068-2 test method test procedure requirements

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