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products and specifications discussed herein are subject to change by micron without notice. pdf: 09005aef80a2e32f/source: 09005aef80a2e30d sd9c8_16_32x72g.fm - rev. b 2/05 en 1 ?2005 micron technology, inc. all rights reserved. 64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm synchronous dram module mt9lsdt872 ? 64mb mt9lsdt1672 ? 128mb mt9lsdt3272 ? 256mb for the latest data sheet, please refer to the micron ? web site: www.micron.com/products/modules features ? 168-pin, dual in-line memory module (dimm) pc100- and pc133-compliant registered inputs with one-clock delay phase-lock loop (pll) clock driver to reduce loading utilizes 125 mhz and 133 mhz sdram components supports ecc error detection and correction 64mb (8 meg x 72), 128mb (16 meg x 72), and 256mb (32 meg x 72) single +3.3v power supply fully synchronous; all signals registered on positive edge of pll clock internal pipelined operat ion; column address can be changed every clock cycle internal sdram banks for hiding row access/ precharge programmable burst lengths: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge; auto refresh mode self refresh mode: 64ms, 4,096-cycle refresh (64mb, 128mb); 8,192 cycle refresh (256mb) lvttl-compatible inputs and outputs serial presence-detect (spd) gold edge contacts figure 1: 168-pin dimm (mo-161) note: 1. conact micron for product availability. 2. registered mode will add one clock cycle to cl. table 1: timing parameters cl = cas (read) latency module marking clock frequency access time setup time hold time cl = 2 cl = 3 -13e 133 mhz 5.4ns ? 1.5ns 0.8ns -133 133 mhz ? 5.4ns 1.5ns 0.8ns -10e 100 mhz 6ns2 ? 2ns 1ns options marking package 168-pin dimm (standard) g 168-pin dimm (lead-free) y 1 frequency/cas latency 2 133 mhz (7.5ns) / cl = 2 -13e 133 mhz (7.5ns) / cl = 3 -133 100 mhz (8ns) / cl = 2 -10e pcb standard 1.50in. (38.10mm) see page 2 note low-profile 1.125in. (28.58mm) see page 2 note standard 1.50in. (38.10mm) low-profile 1.125 in. (28.58 mm) table 2: address table module density 64mb 128mb 256mb refresh count 4k 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 64mb (8 meg x 8) 128mb (16 meg x 8) 256mb (32 meg x 8) device row addressing 4k (a0?a11) 4k (a0?a11) 8k (a0?a12) device column addressing 512 (a0?a8) 1k (a0?a9) 1k (a0?a9) module ranks 1 (s0#, s2#) 1 (s0#, s2#) 1 (s0#, s2#)
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 2 ?2005 micron technology, inc. all rights reserved. note: all part numbers end with a two-place co de (not shown), designating component and pcb revisions. consult factory for current revision codes. ex ample: mt9lsdt1672g-133b1. table 3: part numbers partnumber module density configuration system bus speed mt9lsdt872g-13e__ 64mb 8 meg x 72 133mhz mt9lsdt872y-13e__ 64mb 8 meg x 72 133mhz mt9lsdt872g-133__ 64mb 8 meg x 72 133mhz mt9lsdt872y-133__ 64mb 8 meg x 72 133mhz mt9lsdt872g-10e__ 64mb 8 meg x 72 100mhz mt9lsdt872y-10e__ 64mb 8 meg x 72 100mhz mt9lsdt1672g-133__ 128mb 16 meg x 72 133mhz mt9lsdt1672y-133__ 128mb 16 meg x 72 133mhz mt9lsdt1672g-13e__ 128mb 16 meg x 72 133mhz mt9lsdt1672y-13e__ 128mb 16 meg x 72 133mhz mt9lsdt1672g-10e__ 128mb 16 meg x 72 100mhz mt9lsdt1672y-10e__ 128mb 16 meg x 72 100mhz mt9lsdt3272g-133__ 256mb 32 meg x 72 133mhz mt9lsdt3272y-133__ 256mb 32 meg x 72 133mhz mt9lsdt3272g-13e__ 256mb 32 meg x 72 133mhz mt9lsdt3272y-13e__ 256mb 32 meg x 72 133mhz mt9lsdt3272g-10e__ 256mb 32 meg x 72 100mhz mt9lsdt3272y-10e__ 256mb 32 meg x 72 100mhz
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 3 ?2005 micron technology, inc. all rights reserved. note: 1. pin 126 is nc (64mb and 128mb) or a12 (256mb). figure 2: 168-pin dimm pin locations table 4: pin assignment table 168-pin dimm (front) pin symbol pin symbol pin symbol pin symbol 1v ss 22 cb1 43 v ss 64 v ss 2dq0 23 v ss 44 dnu 65 dq21 3dq1 24 nc 45 s2# 66 dq22 4dq2 25 nc 46 dqmb2 67 dq23 5dq3 26 v dd 47 dqmb3 68 v ss 6v dd 27 we# 48 dnu 69 dq24 7dq4 28 dqmb0 49 v dd 70 dq25 8dq5 29 dqmb1 50 nc 71 dq26 9dq6 30 s0# 51 nc 72 dq27 10 dq7 31 dnu 52 cb2 73 v dd 11 dq8 32 v ss 53 cb3 74 dq28 12 v ss 33 a0 54 v ss 75 dq29 13 dq9 34 a2 55 dq16 76 dq30 14 dq10 35 a4 56 dq17 77 dq31 15 dq11 36 a6 57 dq18 78 v ss 16 dq12 37 a8 58 dq19 79 ck2 17 dq13 38 a10 59 v dd 80 nc 18 v dd 39 ba1 60 dq20 81 wp 19 dq14 40 v dd 61 nc 82 sda 20 dq15 41 v dd 62 nc 83 scl 21 cb0 42 ck0 63 nc 84 v dd table 5: pin assignment table 168-pin dimm (back) pin symbol pin symbol pin symbol pin symbol 85 v ss 106 cb5 127 v ss 148 v ss 86 dq32 107 v ss 128 cke0 149 dq53 87 dq33 108 nc 129 rfu (s3#) 150 dq54 88 dq34 109 nc 130 dqmb6 151 dq55 89 dq35 110 v dd 131 dqmb7 152 v ss 90 v dd 111cas#132 rfu (a13) 153 dq56 91 dq36 112 dqmb4 133 v dd 154 dq57 92 dq37 113 dqmb5 134 nc 155 dq58 93 dq38 114 nc 135 nc 156 dq59 94 dq39 115ras#136 cb6 157 v dd 95 dq40 116 v ss 137 cb7 158 dq60 96 v ss 117 a1 138 v ss 159 dq61 97 dq41 118 a3 139dq48160dq62 98 dq42 119 a5 140dq49161dq63 99 dq43 120 a7 141 dq50 162 v ss 100 dq44 121 a9 142 dq51 163 ck3 101 dq45 122 ba0 143 v dd 164 nc 102 v dd 123 a11 144 dq52 165 sa0 103 dq46 124 v dd 145 nc 166 sa1 104 dq47 125 ck1 146 nc 167 sa2 105 cb4 126 nc/ a12 1 147 rege 168 v dd u1 u2 u3 u4 u5 u6 u9 u7 u10 u11 u12 u13 u14 u1 u2 u5 u6 u7 u3 u4 u10 u11 u12 u13 u14 u9 indicates a v dd or v ddq pin indicates a v ss pin pin 1 pin 41 pin 84 pin 85 pin125 pin 168 pin 1 pin 41 pin 84 pin 85 pin125 pin 168 standard front view back view front view back view low-profile
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 4 ?2005 micron technology, inc. all rights reserved. table 6: pin descriptions pin numbers may not correlate with sy mbols; refer to pin assignment ta bles on page 3 for more information pin numbers symbol type description 27, 111, 115 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 42, 79, 125, 163 ck0?ck3 input clock: ck is driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and co ntrols the output registers. 128 cke0 input clock enable: cke activates (high) and deactivates (low) the ck signal. deactivating the cloc k provides precharge, power- down, and self refresh operation (a ll device banks idle), active power-down (row active in any device bank), or clock suspend operation (burst access in progress). cke is synchronous except after the device enters powe r-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including ck, are disabled during power- down and self refresh modes, providing low standby power. 30, 45 s0#, s2# input chip select: s# enable (registe red low) and disable (registered high) the command decoder. all commands are masked when s# are registered high. s# are considered part of the command code. 28-29, 46-47, 112-113, 130- 131 dqmb0? dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable sign al for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a hi gh-z state (two-clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba0, ba1 input bank address: ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. 33, 34, 35, 36, 37, 38, 117, 118, 119, 120, 121, 123, 126 (256mb) a0?a11 (64mb, 128mb) a0?a12 (256mb) input address inputs: sampled during the active command and read/ write command, with a10 defining auto precharge) to select one location out of the memory array in the respective device bank. a10 is sampled during a precha rge command to determine if both device banks are to precha rged (a10 high). the address inputs also provide the op-code during a load mode register command. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 165?167 sa0?sa2 input presence-detect address inputs: th ese pins are used to configure the presence-detect device. 147 rege input register enable. 2?5, 7?11, 13?17, 19?20, 55? 58, 60, 65?67, 69?72, 74?77, 86?89, 91?95, 97?101, 103? 104, 139?142, 144, 149?151, 153?156, 158?161 dq0?dq63 input/ output data i/os: data bus. 21?22, 52?53, 105?106, 136?137 cb0?cb7 input/ output check bits. 8 2 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence- detect portion of the module. 6, 18, 26, 40?41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 v dd supply power supply: +3.3v 0.3v.
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 5 ?2005 micron technology, inc. all rights reserved. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 v ss supply ground. 63, 81, 114, 126 (64mb, 128mb), 129, 132 nc ? reserved for future use: these pins are not connected on this module but are assigned pins on other sdram versions. 31, 44, 48 dnu ? do not use: these pins are not co nnected on this module but are assigned pins on the compatible dram version. table 6: pin descriptions pin numbers may not correlate with sy mbols; refer to pin assignment ta bles on page 3 for more information pin numbers symbol type description
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 6 ?2005 micron technology, inc. all rights reserved. figure 3: functional block diagram ? standard pcb a0 sa0 spd sda a1 sa1 a2 sa2 ras# cas# cke0 we# a0-a11 (64mb, 128mb) a0-a12 (256mb) ba0 ba1 s0#, s2# dqmb0-dqmb7 rras#: sdrams rcas#: sdrams rcke0: sdrams rwe#: sdrams ra0-ra11: sdrams ra0-ra12: sdrams rba0: sdrams rba1: sdrams rs0#, rs2# rdqmb0-rdqmb7 ck0 v dd v ss sdrams sdrams dqm cs# dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 rdqmb7 dqm cs# dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 rdqmb6 dqm cs# u13 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 rdqmb5 dqm cs# u14 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 rdqmb4 dqm cs# u6 u9 u8 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 rdqmb3 dqm cs# dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 rdqmb2 dqm cs# u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 rdqmb1 dqm cs# u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 rdqmb0 rs2# rs0# dqm cs# cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 rege v dd 10k r e g i s t e r wp pll sdram x 3 sdram x 3 sdram x 3 register x 2 ck0 12pf 12pf ck1-ck3 scl u12 u3 u11 u4 u10 u5, u7 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 24.9 24.9 20 15pf 6.8pf 30pf 30pf 15pf 30pf 15pf 30pf 30pf 30pf 30pf note: 1. all resisor values are 10 ? unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/ support/numbering.html . standard modules use the following sdram devices: mt48lc8m8a2tg (64mb); mt48l c16m8a2tg (128mb); and mt46lc32m8a2tg (256mb) lead-free modules use the following sdram devices: mt48lc8m8a2p (64mb); mt48lc16m8a2p (128mb); and mt46lc32m8a2p (256mb)
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 7 ?2005 micron technology, inc. all rights reserved. figure 4: functional bloc k diagram ? low-profile pcb dqm cs# dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 rdqmb7 dqm cs# dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 rdqmb6 dqm cs# u13 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 rdqmb5 dqm cs# u14 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 rdqmb4 dqm cs# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 rdqmb3 dqm cs# dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 rdqmb2 dqm cs# u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 rdqmb1 dqm cs# u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 rdqmb0 rs2# rs0# dqm cs# cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 u3 u5 u10 u6 u9 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 24.9 20 15pf 6.8pf 30pf 30pf 15pf 30pf 15pf 30pf 30pf 30pf 30pf a0 sa0 spd sda a1 sa1 a2 sa2 ras# cas# cke0 we# a0-a11 (64mb, 128mb) a0-a12 (256mb) ba0 ba1 s0#, s2# dqmb0-dqmb7 rras#: sdrams rcas#: sdrams rcke0: sdrams rwe#: sdrams ra0-ra11: sdrams ra0-ra12: sdrams rba0: sdrams rba1: sdrams rs0#, rs2# rdqmb0-rdqmb7 ck0 v dd v ss sdrams sdrams u4 u7 u8 rege v dd 10k r e g i s t e r wp pll sdram x 3 sdram x 3 sdram x 3 register x 2 ck0 12pf 12pf ck1-ck3 scl u11, u12 24.9 note: 1. all resisor values are 10 ? unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/ support/numbering.html . standard modules use the following sdram devices: mt48lc16m8a2tg (64mb); mt48lc32m8a2tg (128mb); and mt46lc64m8a2tg (256mb) lead-free modules use the following sdram devices: mt48lc16m8a2p (64mb); mt48lc32m8a2p (128mb); and mt46lc64m8a2p (256mb)
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 8 ?2005 micron technology, inc. all rights reserved. general description the micron mt9lsdt872, mt9lsdt1672, and mt9lsdt3272 are high-speed cmos, dynamic ran- dom-access, 64mb, 128mb, and 256mb modules orga- nized in a x72 configurat ion. sdram modules use internally configured quad -bank sdram devicess with a synchronous interface (all signals are registered on the positive edge of clock signals ck). read and write accesses to sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed [ba0, ba1 select the bank, a0?a11 (64mb and 128mb) or a0?a12 (256mb) select the row]. the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. sdram modules provide for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row pre- charge that is initiated at the end of the burst sequence. sdram modules use an internal pipelined architec- ture to achieve high-speed operation. this architec- ture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high- speed, random-access operation. sdram modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 64mb, 128mb, or 256mb sdram component data sheets. pll and register operation these modules can be operated in either registered mode (rege pin high), where the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the fol- lowing rising clock edge (data access is delayed by one clock), or in buffered mode (rege pin low) where the input signals pass through the register/buffer to the sdram devices on the same clock. a phase-lock loop (pll) on the modules is used to redrive the clock sig- nals to the sdram devices to minimize system clock loading (ck0 is connected to the pll, and ck1, ck2 and ck3 are terminated). serial presence-detect operation sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonv olatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various sdram organization s and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (di mm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hard- ware write protect. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simul- taneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge comm and should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are com- plete, the sdram is ready for mode register program- ming. because the mode register will power up in an
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 9 ?2005 micron technology, inc. all rights reserved. unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode, and a write burst mode, as shown in figure 5, mode register definition. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all device banks are idle, and the contro ller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 5, mode register definition. the burst length determines the maximum number of col- umn locations that can be accessed for a given read or write command. burst leng ths of 1, 2, 4, or 8 loca- tions are available for both the sequential and the interleaved burst types, and a full-page burst is avail- able for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in table 7, burst definition, on page 10. the block is uniquely selected by a1?a i when the burst length is set to two; by a2?a i when the burst length is set to four; and by a3?a i when the burst length is set to eight. see note 8 of table 7, burst definition, on page 10, for a i values. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 7, burst definition, on page 10. figure 5: mode register definition m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length 256mb module 64mb and 128mb modules m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. *should program m11 and m10 = ?0, 0? to ensure compatibility with future devices. a12 12 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 op mode a10 a11 10 11 reserved* wb
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 10 ?2005 micron technology, inc. all rights reserved. note: 1. for full-page accesses: y= 512 (64mb), y = 1,024 (128mb, 256mb) 2. for a burst length of two, a1?a i select the block of two burst; a0 selects the starting column with in the block. 3. for a burst length of four, a2?a i select the block of four burst; a0?a1 select the starting column within the block. 4. for a burst length of eight, a3?a i select the block of eight burst; a0?a2 select th e starting colu mn within the block. 5. for a full-page burst, the fu ll row is selected and a0?a i select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, th e following access wraps within the block. 7. for a burst length of one, a0?a i select the unique col- umn to be accessed, and mode register bit m3 is ignored. 8. i = 8 for 64mb and 128mb; i = 9 for 256mb. figure 6: cas latency diagram burst type accesses within a given burst may be programmed to be either sequential or in terleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 7, burst definition. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the rele vant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dq will start driving after t1 and the data will be valid by t2, as shown in figure 6, cas latency table 7: burst definition burst length starting column address orderofaccesseswithina burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n=a0?9/8 (location0-y) cn,cn+1,cn+2 cn+3,cn+4... ...cn-1, cn... not supported clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 11 ?2005 micron technology, inc. all rights reserved. diagram. table 8, cas latency table, on page 11 indi- cates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. table 8: cas latency table registered mode adds one clock cycle to cas latency speed allowable operating clock frequency (mhz) cas latency = 2 cas latency = 3 -13e 133 143 -133 100 133 -10e 100 n/a
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 12 ?2005 micron technology, inc. all rights reserved. commands table 9, commands and dqmb operation truth table provides a quick reference of available com- mands. this is followed by a written description of each command. for a more detailed description of commands and operations refer to the 64mb, 128mb, or 256mb sdram component datasheets. note: 1. a0?a11 provide row address, and ba0, ba1 determine which bank is made active. 2. a0?a8 (64mb and 128mb) or a0?a9 (256mb) provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 3. a10 low: ba0, ba1 determine which bank is being precharged. a10 high: both banks are precharged and ba0, ba1 are ?don?t care.? 4. this command is auto refresh if cke is high, self refresh if cke is low. 5. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 6. a0?a11 define the op-code wr itten to the mode register. 7. activates or deactivates the dq during writes (zero-clock delay) and reads (two-clock delay). table 9: commands and dq mb operation truth table cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) hxxxx x x no operation (nop) l hhhx x x active (select bank and activate row) l l h h x bank/row x 1 read (select bank and column, and start read burst) lhlh l/h 8 bank/col x 2 write (select bank and colu mn, and start write burst) lhl l l/h 8 bank/col valid 2 burst terminate lhhlx xactive precharge (deactivate row in bank or banks) llhlxcodex 3 auto refresh or self refresh (enter self refresh mode) lllhx x x4, 5 load mode register llllxop-codex 6 write enable/output enable ? ? ? ? l ?active7 write inhibit/output high-z ? ? ? ?h ?high-z7
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 13 ?2005 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply, relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature, t opr (commercial - ambient) . . . . . .0c to +55c storage temperature (plastic) . . . . . . -55c to +150c table 10: dc electrical charac teristics and operating conditions notes: 1, 5, 6; note s appear on page 17; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) command and address i l -5 5 a 33 s#, cke -2.5 2.5 ck, dqmb -5 -5 output leakage current: dq pins are disabled; 0v v out v dd q dq i oz -5 5 a 33 output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v table 11: i dd specifications an d conditions ? 64mb notes: 1, 5, 6; v dd = +3.3v 0.3v; note s appear on page 17 max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 i dd 1 1,125 1,035 855 ma 3, 18, 19, 30 standby current: power-down mode; cke = low; all banks idle i dd 2181818ma 30 standby current: active mode; s# = high; cke = high; all banks active after t rcd met; no accesses in progress i dd 3 405 405 315 ma 3, 18, 19, 30 operating current: burst mode; continuous burst; read or write; all banks acti ve; cas latency = 3 i dd 4 1,350 1,260 1,080 ma 3, 18, 19, 30 auto refresh current: cke = high; s# = high t rc = t rc (min) i dd 5 2,070 1,890 1,710 ma 3, 18, 19, 30 t rc = 15.625s i dd 6 27 27 27 ma 18, 19, 30 self refresh current: cke 0.2v i dd 7999ma4
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 14 ?2005 micron technology, inc. all rights reserved. table 12: i dd specifications an d conditions ? 128mb notes: 1, 5, 6, 11, 13; v dd = +3.3v 0.3v; notes appear on page 17 max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 i dd 1 1,440 1,350 1,260 ma 3, 18, 19, 30 standby current: power-down mode; cke = low; all banks idle i dd 2181818ma 30 standby current: active mode; s# = high; cke = high; all banks active after t rcd met; no accesses in progress i dd 3 450 450 360 ma 3, 18, 19, 30 operating current: burst mode; continuous burst; read or write; all banks acti ve; cas latency = 3 i dd 4 1,485 1,350 1,260 ma 3, 18, 19, 30 auto refresh current: cke = high; s# = high t rc = t rc (min) i dd 5 2,970 2,790 2,430 ma 3, 18, 19, 30 t rc = 15.625s i dd 6 27 27 27 ma 18, 19, 30 self refresh current: cke 0.2v i dd 7181818ma 4 table 13: i dd specifications an d conditions ? 256mb notes: 1, 5, 6, 11, 13; v dd = +3.3v 0.3v; notes appear on page 17 max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 i dd 1 1,215 1,125 1,125 ma 3, 18, 19, 30 standby current: power-down mode; cke = low; all banks idle i dd 2181818ma 30 standby current: active mode; s# = high; cke = high; all banks active after t rcd met; no accesses in progress i dd 3 360 360 360 ma 3, 18, 19, 30 operating current: burst mode; continuous burst; read or write; all banks acti ve; cas latency = 3 i dd 4 1,215 1,215 1,215 ma 3, 18, 19, 30 auto refresh current: cke = high; s# = high t rc = t rc (min) i dd 5 2,565 2,430 2,430 ma 3, 18, 19, 30 t rc = 7.8125s i dd 6 32 32 32 ma 18, 19, 30 self refresh current: cke 0.2v i dd 7232323ma 4 table 14: capacitance notes: 2; v dd = 3.3v 0.3v; notes appear on page 17 parameter symbol max units input capacitance: address and command c i 1 8pf input capacitance: s#, cke, dqmb# c i 28pf input capacitance: ck c i 36pf input/output capacitance: dq, cb c io 8pf
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 15 ?2005 micron technology, inc. all rights reserved. table 15: electrical characteristics an d recommended ac operating conditions notes: 5, 6, 7, 8, 9, 10, 31; v dd = 3.3v 0.3v; notes appear on page 17 ac characteristics -13e -133 -10e units notes parameter symbol min max min max min max access time from clk (positive edge) cl=3 t ac 5.4 5.4 6 ns 27 cl = 2 t ac 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high level width t ch 2.5 2.5 3 ns clk low level width t cl 2.5 2.5 3 ns clock cycle time cl=3 t ck 77.58 ns13 cl = 2 t ck 7.5 10 10 ns 13 ckeholdtime t ckh 0.8 0.8 1 ns ckesetuptime t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance time cl=3 t hz 5.4 5.4 6 ns 24 cl = 2 t hz 5.4 6 6 ns 24 data-out low-impedance time t lz 111ns data-out hold time (load) t oh 2.7 2.7 3 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 25 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns 32 active to active command period t rc 60 66 70 ns active to read or write delay t rcd 15 20 20 ns refresh period (4,096 cycles) t ref 64 64 64 ms auto refresh period t rfc 66 66 70 ns prechargecommand period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 20 ns transition time t t 0.3 0.3 1.2 0.3 1.2 ns 23 writ erecovery time t wr 1 clk + 7ns 1 clk + 7.5ns 1 clk + 7.5ns ?28 14 15 15 ns 28 exit self refresh to active command t xsr 67 75 80 ns
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 16 ?2005 micron technology, inc. all rights reserved. table 16: ac function al characteristics notes: 5, 6, 7, 8, 9, 11, 13, 31; v dd = 3.3v 0.3v; notes appear on page 17 parameter symbol -133 -10e units notes read/write command to read/write command t ccd 11 t ck 17 cke to clock disable or power-down entry mode t cked 11 t ck 14, 34 cke to clock enable o rpower-down exit setup mode t ped 11 t ck 14, dqm to input data delay t dqd 00 t ck 17, 34 dqm to data mask during writes t dqm 00 t ck 17, 34 dqm to data high-impedance during reads t dqz 22 t ck 17, 34 write command to input data delay t dwd 00 t ck 17, 34 data-in to active command t dal 54 t ck 15, 21, 34 data-in to precharge command t dpl 22 t ck 21,16, 34 last data-in to burst stop command t bdl 11 t ck 17, 34 last data-in to ne w read/write command t cdl 11 t ck 17, 34 last data-in to precharge command t rdl 22 t ck 21,16, 34 load mode register command to active or refresh command t mrd 22 t ck 26 data-out to high-imp edance from precharge command cl = 3 t roh 33 t ck 17, 34 cl = 2 t roh 22 t ck 17, 34
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 17 ?2005 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz; t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c to +55c). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the isv crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. once clock is added to latency in registered mode. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions aver age one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 10ns for -10e; ; t ck = 7.5ns for -133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7.5ns for -10; and 7ns for -8 after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for33/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for -13e, cl = 2 and t ck = 7.5ns; for -133, cl = 3 and t ck = 7.5ns; for -10e, cl = 2 and t ck = 10ns. 30. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 31. refer to device data sheet for timing waveforms. 32. the value of t ras used in -13e speed grade mod- ule spds is calculated from t rc - t rp = 45ns. 33. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 34. this ac timing function will show an extra clock cycle when in registered mode. q 50pf
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 18 ?2005 micron technology, inc. all rights reserved. note: 1. ssc = spread spectrum cloc k. the use of ssc synthesizers on th e system motherboard will reduce emi. 2. skew is defined as the to tal clock skew between any two outputs and is therefore specified as a maximum only. table 17: register timing requirem ents and switching characteristics register symbol parameter condition 0c t a 55c v dd = +3.3v 0.3v units min max sstl bit pattern by jesd82-2 f clock clock frequency 150 240 mhz t pd1 propagation delay, single rank (ck to output) 50pf to gnd and 50 ohms to vtt 1.4 3.5 ns t pd2 propagation delay, dualrank (ck to output) 30pf to gnd and 50 ? to v tt 0.7 2.4 ns t w pulse duration ck, high or low 3.3 - ns t su setup time data before ck high .75 - ns t h hold time data after ck high .75 - ns table 18: pll clock driver timing requ irements and switching characteristics parameter symbol 0c t a 55c v dd = +3.3v 0.3v units notes min max operating clock frequency f ck 50 140 mhz inupt duty cycle t dc 44 55 % cycle to cycle jitter t jit cc -75 75 ps static phase offeset t ? -150 150 ps ssc induced skew t ssc - 150 ps 1, 2 output to output skew t sk o - 150 ps
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 19 ?2005 micron technology, inc. all rights reserved. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 7, data validity, and figure 8, defini- tion of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 9, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no st op condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 7: data validity figure 8: definition of start and stop figure 9: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 20 ?2005 micron technology, inc. all rights reserved. figure 10: spd eeprom table 19: eeprom device select code most significan t bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 20: eeprom operating modes mode rw bit w c bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = 1 randomaddressread 0v ih or v il 1 start, device select, rw = 0, address 1v ih or v il restart, device select, rw = 1 sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = 0 page write 0v il 16 start, device select, rw = 0 scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 21 ?2005 micron technology, inc. all rights reserved. note: 1. to avoid spurious start and stop conditions, a minimum de lay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom wr ite cycle time ( t wrc) is the time from a valid stop condit ion of a write sequence to the end of the eeprom internal erase/prog ram cycle. during the write cycle, the eepr om bus interface circuit is disabled, sda remains high due to pull-up resistor, and the ee prom does not respond to its slave address. table 21: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v dd or v ss i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma table 22: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 22 ?2005 micron technology, inc. all rights reserved. table 23: serial-pres ence detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt9lsdt872 mt9lsdt1672 mt9lsdt3272 0 number of bytes used by micron 128 80 80 80 1 total number of spd memory bytes 256 08 08 08 2 memory type sdram040404 3 number of row addresses 12 or 13 0c 0c 0d 4 number of column addresses 9 or10 09 0a 0a 5 number of banks 1 010101 6 module data width 72 48 48 48 7 module data width (continued) 0 000000 8 module voltage interface levels lvttl 01 01 01 9 sdram cycle time, t ck (cas latency = 3) 7ns (-13e) 7.5ns (-133) 8ns (-10e) 70 75 80 70 75 80 70 75 80 10 sdram access from clock, t ac (cas latency = 3) 5.4ns (-13e/-133) 6ns (-10e) 54 60 54 60 54 60 11 module configuration type ecc 020202 12 refresh rate/type 15.6s or 7.8/self 80 80 82 13 sdram width (primary dram) 8 080808 14 error-checking sdram data width 8 080808 15 min. clock delay from back-to-back random column addresses, t ccd 1 010101 16 burst lengths supported 1,2,4,8,page 8f 8f 8f 17 number of banks on sdram device 4 040404 18 cas latencies supported 2,3 060606 19 cs latency 0 010101 20 we latency 0 010101 21 sdram module attributes -13e/-133/-10e 1f 1f 1f 22 sdram device attributes: general 0e 0e 0e 0e 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-13e) 10ns (-133/-10e) 75 a0 75 a0 75 a0 24 sdram access from clock, t ac (cas latency = 2) 5.4ns (-13e) 6ns (-133/-10e) 54 60 54 60 54 60 25 sdram cycle time, t ck (cas latency = 1) ? 000000 26 sdram access from clock, t ac (cas latency = 1) ? 000000 27 minimum row pr echarge time, t rp 15ns (-13e) 20ns (-133/-10e) 14ns (-13e) 0f 14 14 0f 14 14 0f 14 14 28 minimum row active to row active, t rrd 14ns (-13e) 15ns (-133) 20ns (-10e) 0e 0f 14 0e 0f 14 0e 0f 14 29 minimum ras# to cas# delay, t rcd 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 23 ?2005 micron technology, inc. all rights reserved. 30 minimum ras# pulse width, t ras 37ns (-13e) 44ns (-133) 50ns (-10e) 2d 2c 32 2d 2c 32 2d 2c 32 31 module rank density 64mb/128mb/ 256mb 10 20 40 32 command and address setup time, t as, t cms 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 33 command and address hold time, t ah, t cmh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 34 data signal input setup time, t ds 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 35 data signal input hold time, t dh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 36?40 reserved 00 00 00 41 device minimum active/auto-refresh time, t rc 66ns (-13e) 71ns (-133) 66ns (-10e) 3c 42 46 3c 42 46 3c 42 46 42?61 reserved 00 00 00 62 spd revision rev. 2.0020202 63 checksum for bytes 0-62 -13e -133 -10e b4 00 4c c5 11 5d e8 34 80 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 01?12 01?0c 01?0c 01?0c 73-90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1?9 01?09 01?09 01?09 92 identification code (cont.) 0 000000 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-125 manufacturer-specific data (rsvd) ??? 126 system frequency 100 mhz (-13e/-133/-10e) 64 64 64 127 sdram component and clock detail 8f 8f 8f table 23: serial-presence detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt9lsdt872 mt9lsdt1672 mt9lsdt3272
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 24 ?2005 micron technology, inc. all rights reserved. figure 11: 168-pin dimm di mensions ? standard pcb note: all dimensions in inches (millim eters); or typical where noted. 1.505 (38.23) 1.495 (37.97) pin 1 0.700 (17.78) typ. 0.118 (3.00) d (2x) 0.118 (3.00) typ. 0.250 (6.35) typ. 4.550 (115.57) typ. 0.050 (1.27) typ. 0.118 (3.00) typ. 0.040 (1.02) typ. 0.079 (2.00) r (2x) 0.039 (1.00) r(2x) pin 84 front view back view pin 168 pin 85 2.625 (66.68) typ. 1.661 (42.18) typ. 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) 0.157 (4.00) max u1 u2 u5 u6 u7 u3 u4 u10 u11 u12 u13 u14 u9 max min
64mb, 128mb, 256m b (x72, ecc, sr) 168-pin sdram rdimm pdf: 09005aef80a2e32f/source: 09005aef80a2e30d micron technology, inc., reserves the right to change products or specifications without notice. sd9c8_16_32x72g.fm - rev. b 2/05 en 25 ?2005 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 12: 168-pin dimm di mensions ? low-profile pcb note: all dimensions in inches (millim eters); or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 1.130 (28.702) 1.120 (28.448) pin 1 0.700 (17.78) typ. 0.118 (3.00) d (2x) 0.118 (3.00) typ. 0.250 (6.35) typ. 4.550 (115.57) typ. 0.050 (1.27) typ. 0.118 (3.00) typ. 0.040 (1.02) typ. 0.079 (2.00) r (2x) 0.039 (1.00) r(2x) pin 84 front view back view pin 168 pin 85 2.625 (66.68) typ. 1.661 (42.18) typ. 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) 0.157 (4.00) max u1 u2 u3 u4 u5 u6 u9 u7 u10 u11 u12 u13 u14 max min

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