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n04l1630c2b (doc# 14-02-042 rei i ecn# 01-1374 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. advance information ami semiconductor, inc. ulp memory solutions 670 north mccarthy blvd. suite 220 milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 4mb ultra-low power asynchronous cmos srams 256k 16 bit power saver technology tm overview the n04l1630c2b is an integrated memory device containing a 4 mbit static random access memory organized as 262,144 words by 16 bits. the device is designed and fabricated using ami semiconductor?s advanced cmos technology to provide both high-speed performance and ultra-low power. the device operates with two chip enable (ce1 and ce2) controls and output enable (oe ) to allow for easy memory expansion. byte controls (ub and lb ) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. the n04l1630c2b is optimized for the ultimate in low power and is suited for various applications where ultra-low- power is critical such as medical applications, battery backup and power sensitive hand-held devices. the unique page mode operation saves operating power while improving the performance over standard srams. the device can operate over a very wide temperature range of -40 o c to +85 o c and is available in jedec standard packages compatible with other standard 256kb x 16 srams. features ? wide power supply range 2.7 to 3.6 volts ? very low standby current 1ua (typical) ? very low operating current 2.0ma at 1s (typical) ? very low page mode operating current 0.8ma at 1s (typical) ? simple memory control dual chip enables (ce1 and ce2) byte control for independent byte operation output enable (oe ) for memory expansion ? very fast output enable access time 30ns oe access time 55ns random access time 30ns page mode access time ? automatic power down to standby mode ? ttl compatible three-state output driver ? rohs compliant tsop and bga packages product family part number package type operating temperature power supply (vcc) speed options standby current (i sb ), typical operating current (icc), typical N04L1630C2BB2 48-bga green -40 o c to +85 o c 2.7v - 3.6v 55ns 70ns 1a 2 ma @ 1mhz n04l1630c2bt2 44-tsop ii green
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. pin configurations (4mb) pin descriptions pin name pin function a 0 -a 17 address inputs we write enable input ce1 chip enable 1 input ce2 chip enable 2 input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 7 lower byte data input/output i/o 8 -i/o 15 upper byte data input/output v cc power v ss ground nc not connected pin one 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 4 a 3 a 2 a 1 a 0 ce1 i/o 0 i/o 1 i/o 2 i/o 3 vcc vss i/o 4 i/o 5 i/o 6 i/o 7 we a 16 a 15 a 14 a 13 a 12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 5 a 6 a 7 oe ub lb i/o 15 i/o 14 i/o 13 i/o 12 vss vcc i/o 11 i/o 10 i/o 9 i/o 8 ce2 a 8 a 9 a 10 a 11 a 17 tsop ii 123456 a lb oe a 0 a 1 a 2 ce2 b i/o 8 ub a 3 a 4 ce1 i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ss i/o 11 a 17 a 7 i/o 3 v cc e v cc i/o 12 nc a 16 i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 nc a 12 a 13 we i/o 7 h nc a 8 a 9 a 10 a 11 nc 48 pin bga (top)
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. functional block diagram functional description ce1 ce2 we oe ub lb i/o 0 - i/o 15 1 1. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - i/o 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. mode power hxxxxx high z standby 2 2. when the device is in standby mode, control inputs (we , oe , ub , and lb ), address inputs and data input/outputs are internally isolated from any external in fluence and disabled from exerti ng any influence externally. standby xlxxxx high z standby 2 standby l h x x h h high z standby standby lhl x 3 3. when we is invoked, the oe input is internally disabled and has no effect on the circuit. l 1 l 1 data in write 3 active lhhl l 1 l 1 data out read active lhhh l 1 l 1 high z active active capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf address inputs a1 - a4 address inputs a0, a5 - a17 word address decode logic 16k page x 16 word x 16 bit ram array word mux input/ output mux and buffers page address decode logic control logic ce1 ce2 we oe ub lb i/o0 - i/o7 i/o8 - i/o15
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions ab ove those indicated in the operating section of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 260 o c, 10sec o c operating characteristics (ove r specified temperature range) item symbol test conditions min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and not 100% tested. max unit supply voltage v cc 2.7 3.0 3.6 v data retention voltage v dr chip disabled 3 1.8 v input high voltage v ih 0.7vcc v cc +0.3 v input low voltage v il ?0.3 0.6 v output high voltage v oh i oh = -100ua v cc ?0.2 v i oh = -1ma 2.4 v output low voltage v ol i ol = 100ua 0.2 v i ol = 2.1ma 0.4 input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe = v ih or chip disabled 0.5 a read/write operating supply current @ 1 s cycle time 2 2. this parameter is specified with the outp uts disabled to avoid external loading effe cts. the user must add current required t o drive output capacitance expected in the actual system. i cc1 v cc =v cc max, v in =v ih or v il chip enabled, i out = 0 2.5 3.0 ma read/write operating supply current @ 70 ns cycle time 2 i cc2 v cc =v cc max, v in =v ih or v il chip enabled, i out = 0 10 15.0 ma page mode operating supply current @ 70ns cycle time 2 (refer to power savings with page mode operation) i cc3 v cc =v cc max, v in =v ih or v il chip enabled, i out = 0 48ma maximum standby current 3 3. this device assumes a standby mo de if the chip is disabled (ce1 high or ce2 low). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 3.6 v 110.0 a maximum data retention current 3 i dr vcc = 1.8v, v in = v cc or 0 chip disabled, t a = 85 o c 5a
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. power savings with page mode operation (we = v ih ) note: page mode operation is a method of addressing the sram to save operating current. the internal organization of the sram is optimized to allow this unique operating mode to be used as a valuable power saving feature. the only thing that needs to be done is to address the sram in a manner that the internal page is left open and 16-bit words of data are read from the open page. by treating addresses a1-a4 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power srams. page address (a0, a5 - a17) lb , ub oe ce1 ce2 word address (a1 - a4) open page word 1 word 2 word 16 ...
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 30pf operating temperature -40 to +85 o c timing item symbol -55 -70 units min. max. min. max. read cycle time t rc 55 70 ns address access time t aa 55 70 ns page mode address access time t aap 30 35 ns chip enable to valid output t co 55 70 ns output enable to valid output t oe 30 35 ns byte select to valid output t be 55 70 ns chip enable to low-z output t lz 10 10 ns output enable to low-z output t olz 55ns byte select to low-z output t bz 10 10 ns chip disable to high-z output t hz 0 20 0 20 ns output disable to high-z output t ohz 0 20 0 20 ns byte select disable to high-z output t bhz 0 20 0 20 ns output hold from address change t oh 10 10 ns write cycle time t wc 55 70 ns chip enable to end of write t cw 45 50 ns address valid to end of write t aw 45 50 ns byte select to end of write t bw 45 50 ns write pulse width t wp 40 40 ns address setup time t as 00ns write recovery time t wr 00ns write to high-z output t whz 20 20 ns data to write time overlap t dw 40 40 ns data hold from write time t dh 00 ns end write to low-z output t ow 55ns
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. timing of read cycle (ce1 = oe = v il , we = ce2 = v ih ) timing waveform of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid address lb , ub oe data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t be t blz ce1 ce2
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. timing waveform of page mode read cycle (we = v ih ) page address (a0, a5 - a17) lb , ub oe t aa t co t hz t ohz t bhz t olz t oe high-z data out t be t blz ce1 ce2 word address (a1 - a4) t aap t rc
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. timing waveform of write cycle (we control) timing waveform of write cycle (ce1 control) address data in ce1 ce2 lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t bw address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t lz t dw t bw data out t whz ce1 (for ce2 control, use inverted signal)
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. 44-lead tsop ii package (t44) note: 1. all dimensions in inches (millimeters) 18.410.13 10.160.13 see detail b 1.100.15 11.760.20 0.45 0.30 0.80mm ref detail b 0.80mm ref 0 o -8 o 0.20 0.00
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. ball grid array package side view top view bottom view e d a1 ball pad corner (3) 1.240.10 0.280.05 0.15 0.05 z z 1. 0.350.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
(doc# 14-02-042 rei i ecn# 01-1374 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n04l1630c2b advance information ami semiconductor, inc. ordering information ? 2006 ami semiconductor, inc. all rights reserved. ami semiconductor, inc. ("amis") reserves the right to change or modify the information contained in this data sheet and the pr oducts described therein, without prior notice. amis does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. amis makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does amis assume an y liability arising out of t he application or use of any product or circuit described herein. amis does not authorize use of its products as critical components in any application in which the failure of the amis product may be expected to result in significant injury or death, incl uding life support systems and critical medical instruments. revision history revision date change description a april 2003 initial advanced release b august 2004 changed part number to -30 from -3w and vcc range to 2.7 v - 3.6v c january 2005 change i dr = 5 a, i cc (typ) = 2.5ma. modified page mode address a1-a4 configuration. d january 2005 general update e march 22, 2005 changed twp and tdw to 40ns for -55 and -70, to 45ns for -85 f june 9, 2005 added tsop ii green package ordering option g dec. 2005 added rohs compliant h july 2006 added bga package i september 2006 converted to ami semiconductor n04l1630c2bx -xx i 55 = 55ns 70 = 70ns b2 = 48-ball bga green (rohs compliant) t2 = 44-pin tsop ii green (rohs compliant) performance package type

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