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october 2005 document control #ml0035 rev 0.0 1 stk14cb16 256k x 16 autostore tm nvsram quantumtrap tm cmos nonvolatile static ram advanced information features ? 25ns access time ? ?hands-off? automatic store on power down with only a small capacitor ? store to quantumtrap? nonvolatile elements is initiated by software , device pin or autostore ? on power down ? recall to sram initiated by software or power up ? unlimited read, write and recall cycles ? 10ma typical i cc at 200ns cycle time ? 500,000 store cycles to quantumtrap? ? 100-year data retention to quantumtrap? ? single 3v +20%, -10% operation ? commercial and industrial temperatures ? ssop and tsop ii packages ? rohs compliance description the simtek stk14cb16 is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate simtek?s quantumtrap tm technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap tm cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. block diagram row decoder column dec g e w column i/o power control store/ recall control software detect a 17 ? a 0 quantum trap 2048 x 2048 static ram array 2048 x 2048 store recall v cc v cap a 17 ? a 0 address latch output buffers input buffers dq 15 ? dq 0 figure 1. block diagram
stk14cb16 october 2005 document control #ml0035 rev 0.0 2 packages pin descriptions pin name i/o description a 17 ? a 0 input address: the 18 address inputs select one of 262,144 words in the nvsram array. dq 15 ?dq 0 i/o data: bi-directional 16-bit data bus for accessing the nvsram. e input chip enable: the active low e input selects the device. w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e . g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high causes the dq pins to tri-state. v cc power supply power 3.0v +20%, -10% hsb i/o hardware store busy: when low this output indicates a hardware store is in progress. when pulled low external to the chip it will initiate a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore capacitor: supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v ss power supply ground (blank) no connect unlabeled pins have no internal connection. ssop relative pcb area usage. see website for detailed package size specifications. 48 pin ssop v cap v ss a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 a 13 a 8 dq 0 v ss dq 6 a 9 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 w hsb dq 1 dq 2 g a 3 a 2 a 1 a 0 dq 5 a 10 dq 7 dq 4 dq 3 v cc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e a 11 a 17 44 pin tsop ii v ss a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 a 13 a 8 dq 0 v ss dq 6 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 w dq 1 dq 2 a 3 a 2 a 1 a 0 dq 5 a 10 dq 7 dq 4 dq 3 17 1 8 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e a 11 a 17 v cc dq 1 5 dq 9 dq 14 dq 13 dq 10 dq 8 dq 11 dq 12 v cap dq 1 5 dq 9 dq 14 dq 13 dq 10 dq 11 dq 12 dq 8 g
stk14cb16 october 2005 document control #ml0035 rev 0.0 3 package thermal characteristics see website: http://www.simtek.com/ dc characteristics commercial industrial symbol parameter min max min max units notes t avav = 25ns t avav = 35ns i cc1 average v cc current 55 45 30 60 50 45 ma ma ma t avav = 45ns dependent on output loading and cycle rate. values obtained without output loads. i cc2 average v cc current during store 2 2 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ). average v cc current at t avav = 200ns w (v cc ? 0.2v) i cc3 3v, 25c, typical 10 10 ma all others inputs cycling, at cmos levels. dependent on output loading and cycle rate. values obtained without output loads. i cc4 average v cap current during autostore ? cycle 2 2 ma all inputs don?t care average current for duration of store cycle (t store ). v cc standby current e (v cc ? 0.2v) i sb (standby, stable cmos input levels) 3 3 ma all others v in 0.2v or (v cc ? 0.2v) standby current level after nonvolatile cycle is complete. v cc = max i ilk input leakage current 1 1 a v in = v ss to v cc v cc = max i olk off-state output leakage current 1 1 a v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v all inputs v il input logic ?0? voltage v ss ? 0.5 0.8 v ss ? 0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ?2ma v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ?40 85 o c v cc operating voltage 2.7 3.6 2.7 3.6 v 3.0v +20%, -10% v cap storage capacitor 44 100 44 100 f between vcap pin and vss, 5v rated. absolute maximum ratings a power supply voltage voltage on input relative to v ss voltage on outputs temperature under bias junction temperature storage temperature power dissipation dc output current (1 output at a time, 1s duration) notes a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. -0.5v to +4.1v -0.5v to (v cc + 0.5v) -0.5v to (v cc + 0.5v) ?55 c to 125 c ?55 c to 140 c ?65 c to 150 c 1w 15ma
stk14cb16 october 2005 document control #ml0035 rev 0.0 4 ac test conditions capacitance b (t a = 25 c, f = 1.0mhz) symbol parameter max units conditions c in input capacitance 7 pf ? v = 0 to 3v c out output capacitance 7 pf ? v = 0 to 3v notes b: these parameters are guaranteed but not tested 3.0v 30 pf including scope and fixture 577 ohms 789 ohms output 3.0v 30 pf including scope and fixture 577 ohms 789 ohms output figure 3. ac output loading, for tristate specs ( t hz , t lz , t wlqz , t whqz , t glqx , t ghqz ) figure 2. ac output loading input pulse levels input rise and fall times input and output timing reference levels output load 0v to 3v 5ns 1.5v see figure 2 and figure 3 5 pf
stk14cb16 october 2005 document control #ml0035 rev 0.0 5 sram read cycles #1 & #2 symbols stk14cb16-25 no. #1 #2 alt. parameter min max units 1 t elqv t acs chip enable access time 25 ns 2 t avav c t avav c t rc read cycle time 25 ns 3 t avqv d t aa address access time 25 ns 4 t glqv t oe output enable to data valid 12 ns 5 t axqx d t oh output hold after address change 3 ns 6 t elqx t lz chip enable to output active 3 ns 7 t ehqz e t hz chip disable to output inactive 10 ns 8 t glqx t olz output enable to output active 0 ns 9 t ghqz e t ohz output disable to output inactive 10 ns 10 t elicc b t pa chip enable to power active 0 ns 11 t ehicc b t ps chip disable to power standby 25 ns notes c: w must be high during sram read cycles d: device is continuously selected with e and g both low e: measured 200mv from steady state output voltage f: hsb must remain high during read and write cycles. sram read cycle #1: address controlled c,d,f sram read cycle #2: e controlled c,f dq (data out) a ddress 3 t avqv 5 t axqx data valid 2 t avav 2 t avav data valid address dq ( data out ) i cc standby active 1 t elqv 6 t elq x 4 t glqv 8 t glq x 10 t elicch 11 t ehiccl 7 t ehqz 9 t ghqz e g
stk14cb16 october 2005 document control #ml0035 rev 0.0 6 sram write cycles #1 & #2 notes g: if w is low when e goes low, the outputs remain in the high-impedance state. h: e or w must be v ih during address transitions. sram write cycle #1: w controlled h,f sram write cycle #2: e controlled h,f symbols stk14cb16-25 units no. #1 #2 alt. parameter min max 12 t avav t avav t wc write cycle time 25 ns 13 t wlwh t wleh t wp write pulse width 20 ns 14 t elwh t eleh t cw chip enable to end of write 20 ns 15 t dvwh t dveh t dw data set-up to end of write 10 ns 16 t whdx t ehdx t dh data hold after end of write 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 ns 18 t avwl t avel t as address set-up to start of write 0 ns 19 t whax t ehax t wr address hold after end of write 0 ns 20 t wlqz e,g t wz write enable to output disable 10 ns 21 t whqx t ow output active after end of write 3 ns data out data in w e address high impedance data valid previous data 14 t elwh 19 t whax 17 t avwh 18 t avwl 13 t wlwh 15 t dvwh 16 t whd x 20 t wlqz 21 t whqx 12 t a va v address 12 t avav data out data in w e high impedance data valid 14 t eleh 18 t avel 19 t ehax 17 t aveh 13 t wleh 15 t dveh 16 t ehdx
stk14cb16 october 2005 document control #ml0035 rev 0.0 7 autostore ? /power-up recall symbols parameter stk14cb16 no. standard alternate min max units notes 22 t hrecall power-up recall duration 10 ms i 23 t store t hlhz store cycle duration 15 ms j 24 v switch low voltage trigger level 2.55 2.65 v 25 t vccrise v cc rise time 150 s notes i: t hrecall starts from the time v cc rises above v switch j: if an sram write has not taken place since the last nonvolatile cycle, no store will take place autostore ?/power-up recall note: read and write cycles will be ignored during store, recall and while v cc is below v switch power-up recall v cc 23 t store 22 t hrecall 24 v switch autostore tm power down autostore tm brown out autostore tm power-up recall read & write inhibited 25 t vccrise 23 t store 22 t hrecall power-up recall store occurs only if a sram write has happened. no store occurs without at least one sram write.
october 2005 document control #ml0000 0.0 8 software-controlled store / recall cycle k,l symbols stk14cb16-25 no. e cont g cont alt. parameter min max units notes 26 t avav t avav t rc store/recall initiation cycle time 25 ns l 27 t avel t avgl t as address set-up time 0 ns 28 t eleh t glgh t cw clock pulse width 20 ns 29 t elax t glax address hold time 20 ns 30 t recall t recall recall duration 50 s notes k: the software sequence is clocked with e controlled reads or g controlled reads. l: the six consecutive addresses must be read in the order listed in the mode selection table. w must be high during all six consecutive cycles. software store / recall cycle: e controlled l software store / recall cycle: g controlled l dq (data) g e 26 t a va v data valid address address #1 high impedence 27 t avel 29 t elax 28 t eleh 30 t recall 26 t a va v address #6 23 t store data valid / address e g dq (data) 26 t avav data valid address #1 high impedence 29 t glax 30 t recall 26 t avav address #6 23 t store 27 t a vgl 28 t glgh data valid /
october 2005 document control #ml0035 rev 0.0 9 hardware store cycle symbols stk14cb16 no. standard alternate parameter min max units notes 31 t delay t hlqz time allowed to complete sram cycle 1 s p 32 t hlhx hardware store pulse width 15 ns 33 t hlbl hardware store low to store busy 300 ns notes m: read and write cycles in progress before hsb is asserted are given this amount of time to complete. hardware store cycle hsb (out) hsb (in) dq (data out) high impedence 31 t dela y data valid 32 t hlhx 33 t hlbl high impedence data valid 23 t s t o re
stk14cb16 october 2005 document control #ml0035 rev 0.0 10 ordering information stk14cb16 ?r f 25 i temperature range blank = commercial (0 to 70oc) i = industrial (-40 to 85oc) access time 25 = 25ns lead finish f = 100% sn (matte tin) rohs compliant package r = plastic 48-pin 300 mil ssop (25 mil pitch) t = plastic 44-pin 400 mil tsop ii (25 mil pitch)
stk14cb16 october 2005 document control #ml0035 rev 0.0 11 document revision history revision date summary 0.0 october 2005 advanced information simtek stk14cb16 data sheet, october 2005 copyright 2005, simtek corporation. all rights reserved. this datasheet may only be printed for the express use of simtek customers. no part of this datasheet may be reproduced in any other form or means without express written permission from simtek corporation. the information contained in this publication i s believed to be accurate, but changes may be made without notice. simtek does not assume responsibility for, or grant or imply any warranty, including merchantability or fitness for a particular purpose regarding this information, the product or its use. nothing herein constitutes a license, grant or transfer of any rights to any simtek patent, copyright, trademark or other proprietary right.

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