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| 8 Bit Microcontroller TLCS-870/C Series TMP86CH09NG TMP86CH09NG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved Page 2 Revision History Date 2006/10/19 2007/2/14 2007/2/14 2007/2/22 2007/2/28 Revision 1 2 3 4 5 First Release Periodical updating.No change in contents. Periodical updating.No change in contents. Contents Revised Contents Revised Table of Contents TMP86CH09NG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Address Map............................................................................................................................... 7 Program Memory (MaskROM).................................................................................................................. 7 Data Memory (RAM) ................................................................................................................................. 7 Clock Generator........................................................................................................................................ 8 Timing Generator .................................................................................................................................... 10 Operation Mode Control Circuit .............................................................................................................. 11 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 16 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External Reset Input ............................................................................................................................... Address trap reset .................................................................................................................................. Watchdog timer reset.............................................................................................................................. System clock reset.................................................................................................................................. 29 30 30 30 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupt acceptance processing is packaged as follows........................................................................ 37 Saving/restoring general-purpose registers ............................................................................................ 38 Interrupt return ........................................................................................................................................ 40 Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 34 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 34 3.4.1 3.4.2 3.4.3 3.5.1 3.5.2 3.4.2.1 3.4.2.2 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Address error detection .......................................................................................................................... 40 Debugging .............................................................................................................................................. 41 i 3.6 3.7 3.8 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4. Special Function Register (SFR) 4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5. I/O Ports 5.1 5.2 5.3 5.4 P0 (P07 to P00) Port (High Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P1 (P16 to P10) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P2 (P22 to P20) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P3 (P37 to P30) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 49 50 51 6. Time Base Timer (TBT) 6.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Configuration .......................................................................................................................................... 53 Control .................................................................................................................................................... 53 Function .................................................................................................................................................. 54 Configuration .......................................................................................................................................... 55 Control .................................................................................................................................................... 55 6.1.1 6.1.2 6.1.3 6.2.1 6.2.2 6.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 58 59 60 60 61 7.3 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 62 62 63 7.3.1 7.3.2 7.3.3 7.3.4 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Timer mode............................................................................................................................................. External Trigger Timer Mode .................................................................................................................. Event Counter Mode ............................................................................................................................... Window Mode ......................................................................................................................................... Pulse Width Measurement Mode............................................................................................................ 68 70 72 73 74 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 ii 8.3.6 Programmable Pulse Generate (PPG) Output Mode ............................................................................. 77 9. 8-Bit TimerCounter (TC3, TC4) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 16-Bit Timer Mode (TC3 and 4) .............................................................................................................. 16-Bit Event Counter Mode (TC3 and 4) ................................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4).......................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................... Warm-Up Counter Mode......................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 87 88 88 91 93 94 94 97 99 9.3.9.1 9.3.9.2 10. Asynchronous Serial interface (UART ) 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 106 Data Receive Operation ..................................................................................................................... 106 107 107 107 108 108 109 101 102 104 105 105 106 106 106 10.8.1 10.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 10.9.6 11. Serial Expansion Interface (SEI) 11.1 11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SEI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SEI Control Register (SECR).............................................................................................................. 112 SEI Status Register (SESR) ............................................................................................................... 113 SEI Data Register (SEDR).................................................................................................................. 113 Transfer rate 11.2.1.1 11.2.1 11.2.2 11.2.3 11.3 11.4 SEI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SEI Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SCLK pin............................................................................................................................................. 115 MISO/MOSI pins ................................................................................................................................. 115 Controlling SEI clock polarity and phase ............................................................................................ 114 SEI data and clock timing ................................................................................................................... 114 11.3.1 11.3.2 11.4.1 11.4.2 iii 11.5 11.4.3 SEI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SEI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Bus Driver Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Write collision error ............................................................................................................................. 119 Overflow error ..................................................................................................................................... 119 CPHA (SECR register bit 2) = 0 format .............................................................................................. 116 CPHA = 1 format................................................................................................................................. 116 SS pin ................................................................................................................................................. 115 11.6 11.7 11.8 11.9 11.5.1 11.5.2 11.8.1 11.8.2 12. 10-bit AD Converter (ADC) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Software Start Mode ........................................................................................................................... 125 Repeat Mode ...................................................................................................................................... 125 Register Setting ................................................................................................................................ 126 12.4 12.5 12.6 12.3.1 12.3.2 12.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 128 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Analog input pin voltage range ........................................................................................................... 129 Analog input shared pins .................................................................................................................... 129 Noise Countermeasure ....................................................................................................................... 129 12.6.1 12.6.2 12.6.3 13. Key-on Wakeup (KWU) 13.1 13.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14. Input/Output Circuitry 14.1 14.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 15. Electrical Characteristics 15.1 15.2 15.3 15.4 15.5 15.6 15.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 136 137 137 138 139 139 16. Package Dimensions iv This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). v vi TMP86CH09NG CMOS 8-Bit Microcontroller TMP86CH09NG Product No. TMP86CH09NG ROM (MaskROM) 16384 bytes RAM 512 bytes Package SDIP32-P-400-1.78 FLASH MCU TMP86FH09NG Emulation Chip TMP86C909/987XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 17interrupt sources (External : 5 Internal : 12) 3. Input / Output ports (26 pins) Large current output: 8pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer - Divider output function 5. Watchdog Timer 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. 8-bit UART : 1 ch 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CH09NG 9. 8bit Serial Expansion Interface (SEI): 1 channel (MSB/LSB selectable and max. 4Mbps at 16MHz) 10. 10-bit successive approximation type AD converter - Analog input: 6 ch 11. Key-on wakeup : 4 channels 12. Clock operation Single clock mode Dual clock mode 13. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Release by Page 2 TMP86CH09NG 1.2 Pin Assignment VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET (STOP/INT5) P20 (TXD) P00 (RXD) P01 (SCLK) P02 (MOSI) P03 (MISO) P04 P14 P16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P37 (AIN5/STOP5) P36 (AIN4/STOP4) P35 (AIN3/STOP3) P34 (AIN2/STOP2) P33 (AIN1) P32 (AIN0) P31 (TC4/PDO4/PWM4/PPG4) P30 (TC3/PDO3/PWM3) P12 (DVO) P11 (INT1) P10 (INT0) P07 (TC1/INT4) P06 (INT3/PPG) P05 (SS) P13 P15 Figure 1-1 Pin Assignment Page 3 1.3 Block Diagram TMP86CH09NG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CH09NG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/2) Pin Name P07 TC1 INT4 P06 INT3 PPG Pin Number Input/Output IO I I IO I O IO I IO IO IO IO IO IO IO I IO O IO IO IO IO IO O IO I IO I IO O PORT07 TC1 input External interrupt 4 input PORT06 External interrupt 3 input PPG output Functions 21 20 P05 SS 19 PORT05 SEI master/slave select input PORT04 SEI master input, slave output PORT03 SEI master input, slave output PORT02 SEI serial clock input/output pin PORT01 UART data input PORT00 UART data output PORT16 PORT15 PORT14 PORT13 PORT12 Divider Output PORT11 External interrupt 1 input PORT10 External interrupt 0 input PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 External interrupt 5 input STOP mode release signal input PORT37 Analog Input5 STOP5 PORT36 Analog Input4 STOP4 P04 MISO P03 MOSI P02 SCLK P01 RXD P00 TXD P16 P15 P14 P13 P12 DVO 14 13 12 11 10 16 17 15 18 24 P11 INT1 P10 INT0 23 22 P22 XTOUT 7 P21 XTIN P20 INT5 STOP 6 IO I IO I I IO I I IO I I 9 P37 AIN5 STOP5 P36 AIN4 STOP4 32 31 Page 5 1.4 Pin Names and Functions TMP86CH09NG Table 1-1 Pin Names and Functions(2/2) Pin Name P35 AIN3 STOP3 P34 AIN2 STOP2 P33 AIN1 P32 AIN0 P31 TC4 PDO4/PWM4/PPG4 Pin Number Input/Output IO I I IO I I IO I IO I IO I O IO I O I O I I I I PORT35 Analog Input3 STOP3 PORT34 Analog Input2 STOP2 PORT33 Analog Input1 PORT32 Analog Input0 Functions 30 29 28 27 26 PORT31 TC4 input PDO4/PWM4/PPG4 output PORT30 TC3 input PDO3/PWM3 output Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. +5V 0(GND) P30 TC3 PDO3/PWM3 25 XIN XOUT RESET 2 3 8 4 5 1 TEST VDD VSS Page 6 TMP86CH09NG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CH09NG memory is composed MaskROM, RAM and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CH09NG memory address map. 0000H SFR 003FH 0040H 64 bytes SFR: RAM 023FH C000H 512 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack MaskROM: Program memory MaskROM FFC0H FFDFH FFE0H FFFFH 16384 bytes Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CH09NG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86CH09NG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Page 7 2. Operational Description 2.2 System Clock Controller TMP86CH09NG Example :Clears RAM to "00H". (TMP86CH09NG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 01FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 8 TMP86CH09NG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 9 2. Operational Description 2.2 System Clock Controller TMP86CH09NG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 10 TMP86CH09NG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CH09NG is placed in this mode after reset. Page 11 2. Operational Description 2.2 System Clock Controller TMP86CH09NG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 12 TMP86CH09NG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CH09NG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 14 TMP86CH09NG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 0 and 1 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: In case of setting as STOP mode is released by a rising edge of STOP pin input, the release setting by STOP5 to STOP2 on STOPCR register is prohibited. Note 8: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 9: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 15 2. Operational Description 2.2 System Clock Controller TMP86CH09NG Note 8: Before setting TGHALT to "1", be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released. 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which are controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pins (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or detecting high or low edge input for the STOP5 to STOP2 pins which are enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 16 TMP86CH09NG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin inputs for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode Page 17 2. Operational Description 2.2 System Clock Controller TMP86CH09NG STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 18 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 19 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CH09NG 2. Operational Description 2.2 System Clock Controller TMP86CH09NG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Reset Yes "0" IMF Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 20 TMP86CH09NG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 21 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request Program counter a+2 SET (SYSCR2). 4 Operate a+3 Halt Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request Program counter a+3 Instruction address a + 2 Operate Normal release mode a+4 Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86CH09NG (b) IDLE1/2 and SLEEP1/2 modes release TMP86CH09NG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 23 2. Operational Description 2.2 System Clock Controller TMP86CH09NG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF6*TBTCR (2) Interrupt release mode (IMF*EF6*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 24 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86CH09NG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86CH09NG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC4: CLR SET (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 26 TMP86CH09NG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC4: CLR CLR (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 27 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CH09NG SLOW1 mode NORMAL2 mode TMP86CH09NG 2.3 Reset Circuit The TMP86CH09NG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 RAM Refer to each of control register Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 29 2. Operational Description 2.3 Reset Circuit TMP86CH09NG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 30 TMP86CH09NG Page 31 2. Operational Description 2.3 Reset Circuit TMP86CH09NG Page 32 TMP86CH09NG 3. Interrupt Control Circuit The TMP86CH09NG has a total of 17 interrupt sources excluding reset, of which 1 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 Interrupt Factors Internal/External Internal Internal Internal Internal External External Internal Internal Internal Internal Internal Internal External Internal Internal External External (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1, IL11ER = 0 IMF* EF11 = 1, IL11ER = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1 IMF* EF15 = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 11 12 INT1 INTTBT INTTC1 INTRXD INTTXD INTTC3 INTTC4 INT3 INTADC INTSEI INT4 INT5 IL12 IL13 IL14 IL15 FFE6 FFE4 FFE2 FFE0 13 14 15 16 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Page 33 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH09NG Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 34 TMP86CH09NG Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH09NG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 36 TMP86CH09NG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTTC4 and INT3 share the interrupt source level whose priority is 12. Interrupt source selector INTSEL (003EH) 7 6 5 4 IL11ER 3 2 1 0 (Initial value: ***0 ****) IL11ER Selects INTTC4 or INT3 0: INTTC4 1: INT3 R/W Note: Always set "0" to bit 5 of INTSEL register. 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 37 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CH09NG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF2H FFF3H 03H D2H Vector D203H D204H 0FH 06H A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Page 38 TMP86CH09NG Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP b-5 A b-4 SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction b-3 b-2 b-1 SP b At execution of RETI instruction 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-2 Saving/Restoring General-purpose Registers under Interrupt Processing Page 39 3. Interrupt Control Circuit 3.5 Software Interrupt (INTSW) TMP86CH09NG 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM or SFR areas. Page 40 TMP86CH09NG 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86CH09NG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P10 pin function selection are performed by the external interrupt control register (EINTCR). Page 41 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH09NG Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT3 INT3 IMF and EF11 = 1 IL11ER Falling edge, Rising edge, Falling and Rising edge or H level INT4 INT4 IMF EF14 = 1 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF15 = 1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 42 TMP86CH09NG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT3ES 4 3 INT4ES 2 1 INT1ES 0 (Initial value: 0000 000*) INT1NC INT0EN Noise reject time select P10/INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port 1: INT0 pin (Port P10 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: "H" level 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: "H" level 0: Rising edge 1: Falling edge R/W R/W INT4 ES INT4 edge select R/W INT3 ES INT3 edge select R/W INT1 ES INT1 edge select R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT3 pin keeps "H" level, the external interrupt 3 request is not generated even if the INT3 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Note 5: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 43 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH09NG Page 44 TMP86CH09NG 4. Special Function Register (SFR) The TMP86CH09NG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter shows the arrangement of the special function register (SFR) for TMP86CH09NG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H UARTSR RDBUF ADCDR2 ADCDR1 Reserved Reserved Reserved UARTCR1 UARTCR2 TDBUF P0PRD P2PRD ADCCR1 ADCCR2 TC1DRAL TC1DRAH TC1DRBL TC1DRBH TC1CR Reserved Reserved Reserved Reserved Reserved TC3CR TC4CR TTREG3 TTREG4 PWREG3 PWREG4 Read P0DR P1DR P2DR P3DR Reserved Reserved Reserved Reserved Reserved P1CR P3CR P0OUTCR Write Page 45 4. Special Function Register (SFR) 4.1 SFR TMP86CH09NG Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read SESR SEDR SECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write - STOPCR WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 46 TMP86CH09NG 5. I/O Ports The TMP86CH09NG have 4 parallel input/output ports as follows. Primary Function Port P0 Port P1 Port P2 Port P3 8-bit I/O port 7-bit I/O port 3-bit I/O port 8-bit I/O port Secondary Functions External interrupt input, Timer/Counter input/output, serial interface input/output. External interrupt input and divider output External interrupt input and STOP mode release signal input Analog input, STOP mode release signal input and Timer/Counter input/output Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 S3 S0 Read cycle S1 S2 S3 : LD A, (x) Input strobe Data input (a) Input timing Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 S3 S0 Write cycle S1 S2 S3 : LD (x), A Output strobe Data Output Old New (b) Output timing Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 47 5. I/O Ports 5.1 P0 (P07 to P00) Port (High Current) TMP86CH09NG 5.1 P0 (P07 to P00) Port (High Current) The P0 port is an 8-bit input/output port shared with external interrupt input, SEI serial interface input/output, and UART and 16-bit timer counter input/output. When using this port as an input port or for external interrupt input, SEI serial interface input/output, or UART input/output, set the output latch to 1. When using this port as an output port, the output latch data (P0DR) is output to the P0 port. When reset, the output latch (P0DR) and the push-pull control register (P0OUTCR) are initialized to 1 and 0, respectively. The P0 port allows its output circuit to be selected between N-channel open-drain output or push-pull output by the P0OUTCR register. When using this port as an input port, set the P0OUTCR register's corresponding bit to 0 after setting the P0DR to 1. The P0 port has independent data input registers. To inspect the output latch status, read the P0DR register. To inspect the pin status, read the P0PRD register. STOP OUTEN P0OUTCRi P0OUTCRi input Data input (P0PRD) Data input (P0DR) Data output (P0DR) Control output Control input DQ Output latch P0i Note: i = 7 to 0 DQ Output latch Figure 5-2 P0 Port P0DR (0000H) R/W P0PRD (000CH) Read only 7 P07 TC1 INT4 7 P07 6 P06 INT3 PPG 5 P05 SS 4 P04 MISO 4 P04 3 P03 MOS 3 P03 2 P02 SCLK 2 P02 1 P01 RxD 1 P01 0 P00 TxD 0 P00 (Initial value: 1111 1111) 6 P06 5 P05 P0OUTCR (000BH) P0OUTCR Controls P0 port input/output (specified bitwise) 0: Nch open-drain output 1: Push-pull output R/W Page 48 TMP86CH09NG 5.2 P1 (P16 to P10) Port The P1 port is a 7-bit input/output port that can be specified for input or output bitwise. The P1 Port Input/output Control Register (P1CR) is used to specify this port for input or output. When reset, the P1CR register is initialized to 0, with the P1 port set for input mode. The P1 port output latch is initialized to 0. The P1 port is shared with external interrupt input and divider output. When using the P1 port as function pin, set its input pins for input mode. For the output pins, first set their output latches to 1 before setting the pins for output mode. Note that the P11 pin is an external interrupt input. (When used as an output port, its interrupt latch is set at the rising or falling edge.) The P10 pin can be used as an input/output port or an external interrupt input by selecting its function with the External Interrupt Control Register (INT0EN). When reset, the P10 pin is chosen to be an input port. Control input OUTEN STOP P1CRi D Q Output latch P1CRi input Data input (P1DR) Data output (P1DR) Control output D Q P1i Note: i = 6 to 0 Output latch Figure 5-3 P1 Port P1DR (0001H) R/W P1CR (0009H) 7 6 P16 5 P15 5 4 P14 4 3 P13 3 2 P12 DVO 1 P11 INT1 1 0 P10 INT0 (Initial value: ***0 0000) 7 6 2 0 (Initial value: ***0 0000) P1CR Controls P1 port input/output (specified bitwise) 0: Input mode 1: Output mode R/W Page 49 5. I/O Ports 5.3 P2 (P22 to P20) Port TMP86CH09NG 5.3 P2 (P22 to P20) Port The P2 port is a 3-bit input/output port shared with external interrupt input, STOP canceling signal input, and lowfrequency resonator connecting pin. When using this port as an input port or function pin, set the output latch to 1. The output latch is initialized to 1 when reset. When operating in dual-clock mode, connect a low-frequency resonator (32.768 kHz) to the P21 (XTIN) and P22 (XTOUT) pins. When operating in single-clock mode, the P21 and P22 pins can be used as ordinary input/output ports. We recommend using the P20 pin for external interrupt input or STOP canceling signal input or as an input port. (When used as an output port, the interrupt latch is set by a falling edge.) The P2 port has independent data input registers. To inspect the output latch status, read the P2DR register. To inspect the pin status, read the P2PRD register. When the P2DR or P2PRD read instruction is executed for the P2 port, the values read from bits 7 to 3 are indeterminate. Data input (P20PRD) Data input (P20) Data output Control input Data input (P21PRD) Data input (P21) Data output Data input (P22PRD) Data input (P22) Data output STOP OUTEN XTEN fs DQ Output latch DQ Output latch DQ Output latch P20 (INT5, STOP) Osc. enable P21 (XTIN) P22 (XTOUT) Figure 5-4 P2 Port P2DR (0002H) R/W P2PRD (000DH) Read only 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 1 P21 0 P20 INT5 STOP (Initial value: **** *111) 7 6 5 4 3 2 P22 0 P20 Note: The P20 pin is shared with the STOP pin, so that when in STOP mode, its output goes to a High-Z state regardless of the OUTEN status. Page 50 TMP86CH09NG 5.4 P3 (P37 to P30) Port The P3 port is an 8-bit input/output port that can be specified for input or output bitwise, and is shared with analog input, key-on wakeup input, and 8-bit timer counter input/output. The P3 Port Input/output Control Register (P3CR) and ADCCR1 STOPnEN Key-on wakeup Analog input STOP OUTEN AINDS SAIN P3CRi Output latch P3CRi input Data input (P3DR) Data output (P3DR) Output latch P3i a) Equivalent circuit of P32 to P37 Note 1: i = 7 to 2 Note 2: n = 7 to 4 Note 3: Functions enclosed with broken lines do not apply to P32 and P33. Control input OUTEN STOP P3CRi Output latch P3CRi input Data input (P3DR) Data output (P3DR) Output latch P3i Note: i = 1 to 0 Control output b) Equivalent circuit of P30, P31 Figure 5-5 P3 Port Page 51 5. I/O Ports 5.4 P3 (P37 to P30) Port TMP86CH09NG 7 P3DR (0003H) R/W P37 AIN5 STOP5 6 P36 AIN4 STOP4 5 P35 AIN3 STOP3 4 P34 AIN2 STOP2 3 P33 AIN1 2 P32 AIN0 1 P31 TC4 PDO4 PWM4 PPG4 0 P30 TC3 PDO3 PWM3 (Initial value: 0000 0000) P3CR (000AH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P3CR Controls P3 port output (specified bitwise) 0: Input mode 1: Output mode R/W Note 1: When using the port for key-on wakeup input (STOP2 to 5), set the P3CR register's corresponding bits to 0. Note 2: P30 and P31 are hysteresis inputs. P34 to P37 become hysteresis inputs only during key-on wakeup. Note 3: Input status on ports set for input mode are read in into the internal circuit. Therefore, when using the ports in a mixture of input and output modes, the contents of the output latches for the ports that are set for input mode may be rewritten by execution of bit manipulating instructions. Page 52 TMP86CH09NG 6. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 6-1 Time Base Timer configuration 6.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 53 6. Time Base Timer (TBT) 6.1 Time Base Timer TMP86CH09NG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 6.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Page 54 TMP86CH09NG 6.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 6.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 6-3 Divider Output 6.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 55 6. Time Base Timer (TBT) 6.2 Divider Output (DVO) TMP86CH09NG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 56 TMP86CH09NG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 57 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CH09NG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 58 TMP86CH09NG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 59 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CH09NG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 023FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 60 TMP86CH09NG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 7-2 Watchdog Timer Interrupt Page 61 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CH09NG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 7.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 7.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 7.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 62 TMP86CH09NG 7.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 63 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CH09NG Page 64 MCAP1 S A TC1S Y INTTC1 interript 8.1 Configuration B 2 Decoder Command start Start MPPG1 TC1S clear Pulse width measurement mode External trigger External trigger start PPG output mode Set Q Rising Falling Clear Edge detector METT1 TC1 Clear Y 8. 16-Bit TimerCounter 1 (TC1) Port (Note) D Figure 8-1 TimerCounter 1 (TC1) 16-bit up-counter S Page 65 Source clock Match CMP Pulse width measurement mode fc/211, fs/23 A B fc/27 B Y A fc/23 C S Toggle Q 2 Window mode Clear Selector S Q Set Set Clear Port (Note) PPG output mode Internal reset Toggle Enable pin Capture TC1DRB TC1DRA 16-bit timer register A, B ACAP1 TC1CK TC1CR Write to TC1CR TFF1 TC1 control register TMP86CH09NG Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". 8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control TMP86CH09NG 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC1DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0010H) Read/Write TC1DRBL (0012H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 1 Control Register 7 TC1CR (0014H) 6 ACAP1 MCAP1 METT1 MPPG1 5 4 3 2 1 0 Read/Write (Initial value: 0000 0000) TFF1 TC1S TC1CK TC1M TFF1 ACAP1 MCAP1 METT1 MPPG1 Timer F/F1 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC1S TC1 start control - O O O O O R/W - O O O O O NORMAL1/2, IDLE1/2 mode DV7CK = 0 TC1CK TC1 source clock select [Hz] 00 01 10 11 TC1 operating mode select fc/211 fc/27 fc/23 DV7CK = 1 fs/23 fc/27 fc/23 External clock (TC1 pin input) Divider SLOW, SLEEP mode fs/23 - - R/W DV9 DV5 DV1 TC1M 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR1 during TC1S=00. Set the timer F/F1 control until the first timer start after setting the PPG mode. Page 66 TMP86CH09NG Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to "0" in the mode except PPG output mode. Note 7: Set TC1DRB after setting TC1M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC1S) is cleared to "00" automatically, and the timer stops. After the STOP mode is exited, set the TC1S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 67 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR NORMAL1/2, IDLE1/2 mode TC1CK DV7CK = 0 Resolution [s] 00 01 10 128 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m Resolution [s] 244.14 8.0 0.5 DV7CK = 1 Maximum Time Setting [s] 16.0 0.524 32.77 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - SLOW, SLEEP mode Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC1CR), 00000000B (TC1CR), 00010000B (EIRL). 7 (TC1DRA), 1E84H ; Sets the timer register (1 s / 211/fc = 1E84H) ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 Example 2 :Auto-capture LD : LD (TC1CR), 01010000B : WA, (TC1DRB) ; Reads the capture value ; ACAP1 1 Note: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 68 TMP86CH09NG Timer start Source clock Counter TC1DRA 0 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 ? n INTTC1 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture Capture m+1 m+2 n-1 TC1DRB ? m-1 m n n+1 ACAP1 (b) Auto-capture Figure 8-2 Timer Mode Timing Chart Page 69 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin (fc =16 MHz) LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 00100100B (EIRL). 7 (TC1DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin (fc =16 MHz) LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 01110100B (EIRL). 7 (TC1DRA), 01F4H ; 4 ms / 27/fc = 1F4H ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Page 70 TMP86CH09NG Count start TC1 pin input Count start At the rising edge (TC1S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC1DRA n Match detect Count clear INTTC1 interrupt request (a) Trigger start (METT1 = 0) At the rising edge (TC1S = 10) Count start Count clear Count start TC1 pin input Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC1DRA n Match detect Count clear INTTC1 interrupt request Note: m < n (b) Trigger start and stop (METT1 = 1) Figure 8-3 External Trigger Timer Mode Timing Chart Page 71 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR Timer start TC1 pin Input Up-counter TC1DRA INTTC1 interrput request ? 0 1 2 n-1 n 0 1 2 At the rising edge (TC1S = 10) n Match detect Counter clear Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulse Width to TC1 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode High-going Low-going 23/fc 23/fc SLOW1/2, SLEEP1/2 Mode 23/fs 23/fs Page 72 TMP86CH09NG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC1CR Count start Timer start Count stop Count start TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request ? 7 Match detect (a) Positive logic (TC1S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request (b) Negative logic (TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-5 Window Mode Timing Chart Page 73 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR Note 1: The captured value must be read from TC1DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC1DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 74 TMP86CH09NG Example :Duty measurement (resolution fc/27 [Hz]) CLR LD DI SET EI LD : PINTTC1: CPL JRS LD LD LD RETI SINTTC1: LD LD LD : RETI : VINTTC1: DW PINTTC1 ; INTTC1 Interrupt vector ; Duty calculation A, (TC1DRBL) W,(TC1DRBH) (WIDTH), WA ; Stores cycle in RAM ; Reads TC1DRB (Cycle) (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W,(TC1DRBH) (HPULSE), WA ; Stores high-level pulse width in RAM ; Reads TC1DRB (High-level pulse width) ; INTTC1 interrupt, inverts and tests INTTC1 service switch (TC1CR), 00100110B (EIRL). 7 (INTTC1SW). 0 (TC1CR), 00000110B ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 ; Sets the TC1 mode and source clock ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Starts TC1 with an external trigger at MCAP1 = 0 WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW Page 75 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG Count start TC1 pin input Trigger Count start (TC1S = "10") Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start Count start (TC1S = "10") TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP1 = "0") Figure 8-6 Pulse Width Measurement Mode Page 76 TMP86CH09NG 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC1CR Since the output level of the PPG pin can be set with TC1CR Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC1CR Page 77 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 MHz) Setting port LD LDW LDW LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc ms = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD LDW LDW LD : LD LD LD LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B : (TC1CR), 10000111B (TC1CR), 10000100B (TC1CR), 00000111B (TC1CR), 00010111B ; Stops the timer ; Sets the timer mode ; Sets the PPG mode, TFF1 = 0 ; Starts the timer ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc s = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer I/O port output latch shared with PPG output Port output enable PPG pin Data output D R Q Function output TC1CR Set Clear Toggle Q Timer F/F1 INTTC1 interrupt request TC1CR Figure 8-7 PPG Output Page 78 TMP86CH09NG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Note: m > n (a) Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC1DRB n TC1DRA m PPG pin output INTTC1 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC1S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 79 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86CH09NG Page 80 TMP86CH09NG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 9-1 8-Bit TimerCouter 3, 4 Page 81 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (001CH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (001EH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (001AH) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 82 TMP86CH09NG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 83 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (001DH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (001FH) R/ W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (001BH) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the TC3CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 84 TMP86CH09NG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 85 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 86 TMP86CH09NG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRH). 3 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 87 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4) 9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 88 TMP86CH09NG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 89 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Counter 0 1 2 Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 90 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86CH09NG TMP86CH09NG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 9-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 91 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) m Shift Shift m Match detect Match detect Page 92 n One cycle period m PWREG4 ? n p Shift p Match detect Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86CH09NG TMP86CH09NG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 3 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 93 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the event counter mode, fix TCjCR 9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 94 TMP86CH09NG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 9-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - 8.2 ms 4.1 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 95 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 96 b Shift Shift bm Match detect an One cycle period PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an bm cp INTTC4 interrupt request TMP86CH09NG TMP86CH09NG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 97 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 98 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86CH09NG TMP86CH09NG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 9.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 99 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH09NG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG4, 3 = 0100H) 16 s Maximum time (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 100 TMP86CH09NG 10. Asynchronous Serial interface (UART ) 10.1 Configuration UART control register 1 UARTCR1 Transmit data buffer TDBUF Receive data buffer RDBUF 3 2 Receive control circuit 2 Transmit control circuit Shift register Shift register Parity bit Stop bit Noise rejection circuit RXD INTTXD INTRXD TXD Transmit/receive clock Y M P X S 2 Y Counter UARTSR S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC3 A B C fc/2 fc/27 8 fc/2 6 fc/96 A B C D E F G H 4 2 UARTCR2 UART status register Baud rate generator UART control register 2 MPX: Multiplexer Figure 10-1 UART (Asynchronous Serial Interface) Page 101 10. Asynchronous Serial interface (UART ) 10.2 Control TMP86CH09NG 10.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR). UART Control Register1 UARTCR1 (0025H) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC3 ( Input INTTC3) fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UARTCR1 UART Control Register2 UARTCR2 (0026H) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UARTCR2 Page 102 TMP86CH09NG UART Status Register UARTSR (0025H) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Receive Data Buffer RDBUF (0027H) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (0027H) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Page 103 10. Asynchronous Serial interface (UART ) 10.3 Transfer Data Format TMP86CH09NG 10.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1 PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 10-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 10-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 10-3 sequence except for the initial setting. Page 104 TMP86CH09NG 10.4 Transfer Rate The baud rate of UART is set of UARTCR1 Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 4 MHz 19200 [baud] 9600 4800 2400 1200 600 When TC3 is used as the UART transfer rate (when UARTCR1 10.5 Data Sampling Method The UART receiver keeps sampling input using the clock selected by UARTCR1 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 10-4 Data Sampling Method Page 105 10. Asynchronous Serial interface (UART ) 10.6 STOP Bit Length TMP86CH09NG 10.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1 10.7 Parity Set parity / no parity by UARTCR1 10.8 Transmit/Receive Operation 10.8.1 Data Transmit Operation Set UARTCR1 10.8.2 Data Receive Operation Set UARTCR1 Note:When a receive operation is disabled by setting UARTCR1 Page 106 TMP86CH09NG 10.9 Status Flag 10.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR RXD pin Parity Stop Shift register UARTSR xxxx0** pxxxx0* 1pxxxx0 After reading UARTSR then RDBUF clears PERR. INTRXD interrupt Figure 10-5 Generation of Parity Error 10.9.2 Framing Error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR RXD pin Final bit Stop Shift register UARTSR xxx0** xxxx0* 0xxxx0 After reading UARTSR then RDBUF clears FERR. INTRXD interrupt Figure 10-6 Generation of Framing Error 10.9.3 Overrun Error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR Page 107 10. Asynchronous Serial interface (UART ) 10.9 Status Flag TMP86CH09NG UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 UARTSR After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 10-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR 10.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 xxxx After reading UARTSR then RDBUF clears RBFL. UARTSR INTRXD interrupt Figure 10-8 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR 10.9.5 Transmit Data Buffer Empty When no data is in the transmit buffer TDBUF, UARTSR Page 108 TMP86CH09NG Data write TDBUF Data write xxxx yyyy zzzz Shift register TXD pin *****1 1xxxx0 *1xxxx Bit 0 ****1x Final bit *****1 Stop 1yyyy0 Start UARTSR INTTXD interrupt Figure 10-9 Generation of Transmit Data Buffer Empty 10.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR Shift register TXD pin ***1xx ****1x *****1 1yyyy0 *1yyyy Stop Data write for TDBUF Start Bit 0 UARTSR UARTSR INTTXD interrupt Figure 10-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Page 109 10. Asynchronous Serial interface (UART ) 10.9 Status Flag TMP86CH09NG Page 110 TMP86CH09NG 11. Serial Expansion Interface (SEI) SEI is one of the serial interfaces incorporated in the TMP86CH09NG. It allows connection to peripheral devices via full-duplex synchronous communication protocols. The TMP86CH09NG contain one channel of SEI. SEI is connected with an external device through SCLK, MOSI, MISO and the terminal SS. SCLK, MOSI, MISO, and SS pins respectively are shared with P02, P03, P04 and P05. When using these ports as SCLK, MOSI, MISO, or SS pins, set the each Port Output Latch to "1". 11.1 Features * The master outputs the shift clock for only a data transfer period. * The clock polarity and phase are programmable. * The data is 8 bits long. * MSB or LSB-first can be selected. * The programmable data and clock timing of SEI can be connected to almost all synchronous serial peripheral devices. Refer to "" 11.5 SEI Transfer Formats "". * The transfer rate can be selected from the following four (master only): 4 Mbps, 2 Mbps, 1 Mbps, or 250 kbps (when operating at 16 MHz) * The error detection circuit supports the following functions: a. Write collision detection: When the shift register is accessed for write during transfer b. Overflow detection: When new data is received while the transfer-finished flag is set (slave only) Note: Mode fault detect function is not supported. Make sure to set SECR MISO MOSI SCLK SS SEE SEI control register MODE MSTR CPHA CPOL BOS SER SEF Port control unit SEI control unit SEI data register Shift register SEI status register Clock control unit WCOL SOVF Read buffer Clock selection 4, 8, 16, 64 divide Bit order selection Internal SEI clock SEI interrupt (INTSEI1) Data Address Figure 11-1 SEI (Serial Extended Interface) Page 111 11. Serial Expansion Interface (SEI) 11.2 SEI Registers TMP86CH09NG 11.2 SEI Registers The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register (SEDR) which are used to set up the SEI system and enable/disable SEI operation. 11.2.1 SEI Control Register (SECR) 7 SECR (002AH) MODE 6 SEE 5 BOS 4 MSTR 3 CPOL 2 CPHA 1 SER 0 (Initial value: 0000 0100) Read-modify-write instruction are prohibited MODE Mode fault detection#1 0: Enables mode fault detection 1: Disables mode fault detection It is available in Master mode only. (Note: Make sure to set SEE BOS MSTR CPOL CPHA SEI operation#2 Bit order selection Mode selection#3 Clock polarity Clock phase SER Selects SEI transfer rate #1 #2 #3 If mode fault detection is enabled, an interrupt is generated when the MODF flag (SESR 11.2.1.1 Transfer rate (1) Master mode (Transfer rate = fc/Internal clock divide ratio (unit : bps)) The table below shows the relationship between settings of the SER bit and transfer bit rates when the SEI is operating as the master. Table 11-1 SEI Transfer Rate SER 00 01 10 11 Internal Clock Divide Ratio of SEI 4 8 16 64 Transfer Rate when fc = 16 MHz 4 Mbps 2 Mbps 1 Mbps 250 kbps Page 112 TMP86CH09NG (2) Slave mode When the SEI is operating as a slave, the serial clock is input from the master and the setting of the SER bit has no effect. The maximum transfer rate is fc/4. Note: Take note of the following relationship between the serial clock speed and fc on the master side: 15.625 kbps < Transfer rate < fc/4 bps Example) 15.625 kbps < Transfer rate < 4 Mbps (fc = 16 MHz at VDD = 4.5 to 5.5 V) 15.625 kbps < Transfer rate < 2 Mbps (fc = 8 MHz at VDD = 2.7 to 5.5 V) 11.2.2 SEI Status Register (SESR) 7 SESR (0028H) SEF 6 WCOL 5 SOVF 4 - 3 2 1 0 (Initial value: 0000 ****) SEF WCOL SOVF Transfer-finished flag#1 Write collision error flag#2 Overflow error flag (slave)#3 0: Transfer in progress 1: Transfer completed 0: No write collision error occurred 1: Write collision error occurred 0: No overflow occurred 1: Overflow occurred Read only #1 #2 #3 The SEF flag is automatically set at completion of transfer. The SEF flag thus set is automatically cleared by reading the SESR register and accessing the SEDR register. The WCOL flag is automatically set by a write to the SEDR register while transfer is in progress. Writing to the SEDR register during transfer has no effect. The WCOL flag thus set is automatically cleared by reading the SESR register and accessing the SEDR register. No interrupts are generated for reasons that the WCOL flag is set. During master mode: This bit does not function; its data when read is "0". During slave mode: The SOVF flag is automatically set when the device finishes reading the next data while the SEF flag is set. The SOVF flag thus set is automatically cleared by reading the SESR register and accessing the SEDR register. The SOVF flag also is cleared by a switchover to master mode. No interrupts are generated for reasons that the SOVF flag is set. 11.2.3 SEI Data Register (SEDR) The SEI Data Register (SEDR) is used to send and receive data. When the SEI is set for master, data transfer is initiated by writing to this SEDR register. If the master device needs to write to the SEDR register after transfer began, always check to see by means of an interrupt or by polling that the SEF flag (SESR 7 SEDR (0029H) SED7 6 SED6 5 SED5 4 SED4 3 SED3 2 SED2 1 SED1 0 SED0 R/W (Initial value: 0000 0000) Page 113 11. Serial Expansion Interface (SEI) 11.3 SEI Operation TMP86CH09NG 11.3 SEI Operation During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simultaneously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or sampled. Slave device can be selected individually using the slave select pin (SS pin). For unselected slave devices, data on the SEI bus cannot be taken in. When operating as the master devices, the SS pin can be used to indicate multiple-master bus connection. 11.3.1 Controlling SEI clock polarity and phase The SEI clock allows its phase and polarity to be selected in software from four combinations available by using two bits, CPHA and CPOL (SECR CPHA CPOL SEI control register (SECR 002AH) bit 2 SEI control register (SECR 002AH) bit 3 11.3.2 SEI data and clock timing The programmable data and clock timing of SEI allows connection to almost all synchronous serial peripheral devices. Refer to Section "" 11.5 SEI Transfer Formats "". Page 114 TMP86CH09NG 11.4 SEI Pin Functions The TMP86CH09NG have four input/output pins associated with SEI transfer. The functionality of each pin depends on the SEI device's mode (master or slave). The SCLK pin, MOSI pin and MISO pin of all SEI devices are connected with the same name pin to each other . 11.4.1 SCLK pin The SCLK pin functions as an output pin when SEI is set for master, or as an input pin when SEI is set for slave. When SEI is set for master, serial clock is output from the SCLK pin to external devices. After the master starts transfer, eight serial clock pulses are output from the SCLK pin only during transfer. When SEI is set for slave, the SCLK pin functions as an input pin. During data transfer between master and slave, device operation is synchronized by the serial clock output from the master. When the SS pin of the slave device is "H", data is not taken in regardless of whether the serial clock is available. For both master and slave devices, data is shifted in and out at a rising or falling edge of the serial clock, and is sampled at the opposite edge where the data is stable. The active edge is determined by SEI transfer protocols. Note:Noise in a slave device's SCLK input may cause the device to operate erratically. 11.4.2 MISO/MOSI pins The MISO and MOSI pins are used for serial data transmission/reception. The status of each pin during master and slave are shown in the table below. Table 11-3 MISO/MOSI Pin Status MISO Master Slave Input Output MOSI Output Input Also, the SCLK, MOSI, and MISO pins can be set for open-drain by the each pin's input/output control register (In case P0 Port, Input/output Control Register is P0OUTCR). The MISO pin of a slave device becomes an output when the SECR |