View APW8723_7855278.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 5 v t o 1 2 v s i n g l e b u c k v o l t a g e m o d e p w m c o n t r o l l e r f e a t u r e s g e n e r a l d e s c r i p t i o n w i d e 5 v t o 1 2 v s u p p l y v o l t a g e p o w e r - o n - r e s e t m o n i t o r i n g o n v c c excellent output voltage regulations - 0.8v internal reference - 1% over temperature range integrated soft-start v o l t a g e m o d e p w m o p e r a t i o n w i t h e x t e r n a l c o m p e n s a t i o n u p t o 9 0 % d u t y r a t i o f o r f a s t t r a n s i e n t r e s p o n s e constant switching frequency - 300khz 10% i n t e g r a t e d b o o t s t r a p f o r w a r d p - c h m o s f e t d r i v e d u a l l o w c o s t n - m o s f e t s w i t h a d a p t i v e d e a d t i m e c o n t r o l 5 0 % u n d e r - v o l t a g e p r o t e c t i o n 1 2 5 % o v e r - v o l t a g e p r o t e c t i o n adjustable over-current protection threshold - using the r ds(on) of low-side mosfet s h u t d o w n c o n t r o l b y c o m p power good monitoring tdfn3x3-10 package lead free and green devices available (rohs compliant) a p p l i c a t i o n s g r a p h i c c a r d s d s l , s w i t c h h u b w i r e l e s s l a n n o t e b o o k c o m p u t e r m o t h e r b o a r d l c d m o n i t o r / t v t h e a p w 8 7 2 3 i s a v o l t a g e m o d e , f i x e d 3 0 0 k h z s w i t c h i n g f r e q u e n c y , s y n c h r o n o u s b u c k c o n v e r t e r . t h e a p w 8 7 2 3 a l l o w s w i d e i n p u t v o l t a g e t h a t i s e i t h e r a s i n g l e 5 v ~ 1 2 v o r t w o s u p p l y v o l t a g e ( s ) f o r v a r i o u s a p p l i c a t i o n s . t h e p o w e r - o n - r e s e t ( p o r ) c i r c u i t m o n i t o r s t h e v c c s u p p l y v o l t a g e t o p r e v e n t w r o n g l o g i c c o n t r o l s . a b u i l t - i n s o f t - s t a r t c i r c u i t p r e v e n t s t h e o u t p u t v o l t a g e s f r o m o v e r s h o o t a s w e l l a s l i m i t s t h e i n p u t c u r r e n t . a n i n t e r n a l 0 . 8 v t e m p e r a - t u r e - c o m p e n s a t e d r e f e r e n c e v o l t a g e w i t h h i g h a c c u r a c y i s d e s i g n e d t o m e e t t h e r e q u i r e m e n t o f l o w o u t p u t v o l t - a g e a p p l i c a t i o n s . t h e a p w 8 7 2 3 p r o v i d e s e x c e l l e n t o u t - p u t v o l t a g e r e g u l a t i o n s a g a i n s t l o a d c u r r e n t v a r i a t i o n . a p w 8 7 2 3 i s b u i l t i n r e f e r e n c e v o l t a g e o f f s e t f u n c t i o n f o r a p p l i c a t i o n s t h a t r e q u i r e a d j u s t i n g s u p p l y v o l t a g e . the controller?s over-current protection monitors the out- put current by using the voltage drop across the r ds(on) of low-side mosfet, eliminating the need for a current sens- ing resistor that features high efficiency and low cost. in addition, the APW8723 also integrates excellent protec- tion functions, the over-voltage protection (ovp) , under- voltage protection (uvp) and over-temperature protec- tion (otp). ovp circuit which monitors the fb voltage to prevent the pwm output from over voltage, and uvp cir- cuit which monitors the fb voltage to prevent the pwm output from under voltage or short circuit. otp circuit which monitors the junction temperature to prevent over-heat- ing conditions. the APW8723 is available in tdfn3x3-10 package. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 2 s i m p l i f i e d a p p l i c a t i o n c i r c u i t o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n 5 6 vcc 7 fb 8 comp 9 pok 10 phase boot 1 ugate 2 repout 3 ofs 4 lgate / ocset tdfn 3 x 3 - 10 ( top view ) apw 872 3 handling code tem perature range package code package code qb : tdfn 3 x 3 - 10 operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 8723 xxxxx apw 872 3 qb : assembly material xxxxx - date code phase lgate / ocset comp apw 8723 ( tdfn 3 x 3 - 10 ) v in ugate boot ofs refout current controller free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v vcc vcc supply voltage (vcc to gnd) - 0.3 ~ 16 v boot supply voltage (boot to phase) - 0.3 ~ 16 v > 40ns - 0.3 ~ 32 v v boot boot supply voltage (boot to gnd) < 40ns - 0.3 ~ 40 v > 40ns - 0.3 ~ v boot +0.3 v v ugate ugate voltage (ugate to phase) < 40ns - 5 ~ v boot +5 v > 40ns - 0.3 ~ v vcc +0.3 v v lgate lgate voltage (lgate to gnd) < 40ns - 5 ~ v vcc +5 v > 40ns - 0.3 ~ 16 v v phase phase voltage (phase to gnd) < 40ns - 5 ~ 30 v fb and comp to gnd - 0.3 ~ 7 v pok to gnd - 0.3 ~v cc +0.3 v t j maximum j unction temperature 150 c t stg storage temperature - 65 ~ 150 c t sdr maximum lead soldering temperature, 10 seconds 260 c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2) tdfn3x3 - 10 55 c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n . symbol parameter range unit v in vin supply voltage 4 ~ 13.2 v v vcc vcc supply voltage 4.5 ~ 13.2 v v out converter output voltage 0.8 ~ 5 v i out converter output c urrent 0 ~ 25 a t a ambient temperature - 40 ~ 85 c t j junction temperature - 4 0 ~ 1 25 c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s refer to the typical application circuit. these specifications apply over v vcc = 12v, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c. apw 8723 symbol parameter test condition s min. typ. max. unit input supply voltage and current vcc supply current (shutdown mode) ugate and lgate open; comp=gnd - - 550 m a i vcc vcc supply current ugate and lgate open - 2 3 ma power - on - reset(p or) rising vcc por threshold 3.8 4.1 4.4 v vcc por hysteresis 0.3 0.5 0.6 v oscillator f osc oscillator frequency 270 300 330 khz d v osc oscillator sawtooth amplitude (note 4) (1.2v~2.7v typical) - 1.5 - v d max maximum duty cycle - - 90 % refere nce v ref reference voltage t a = - 40 ~ 85 c 0.792 0.8 0.808 v error amplifier gm transconductance (note 4) - 667 - ua/v open - loop bandwidth (note 4) r l = 10k w , c l = 10pf - 20 - mhz fb input leakage current v fb = 0.8v - - 0.1 m a maximum comp sourc e current v comp =2v 200 ua maximum comp sink current v comp =2v 200 ua gate drivers high - side gate driver source current v boot - gnd = 12v, v ugate - phase = 6v - 1.0 - high - side gate driver sink current v boot - gnd = 12v, v ugate - phase = 6v - 1.1 - a low - side gate driver source current v vcc = 1 2 v , v lgate - gnd = 6v - 1.8 - low - side gate driver sink current v vcc = 1 2 v , v lgate - gnd = 6v - 2.0 - a t d dead - time ( note 4) - 30 - ns p rotections v fb_uv fb under - voltage protection trip point percentage of v ofs 45 50 55 % under - voltage debounce interval - 2 - m s v fb_ov fb over - voltage protection rising threshold v fb rising 120 125 130 % fb over - voltage protection hysteresis v fb falling - 20 - % over - voltage debounce interval - 2 - m s ocp setting range v ocset =i ocset ?? r ocset 55 - 600 mv v ocp_max built - in maximum ocp voltage 621 690 759 mv free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) refer to the typical application circuit. these specifications apply over v vcc = 12v, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c. apw 8723 symbol parameter test condition s min. typ. max. unit p rotections (cont.) i ocset ocset current source 9 10 11 m a over - temperature protection threshold - 140 - o c hysteresis - 40 - o c soft - start t ss internal soft - start interval ( note 4) v out from 0% to 90% regulation - 2 - ms comp voltage v disable shutdown threshold of v comp - - 0.4 v ofs function refout current limiting only sourcing - 2 - ma ofs setting range 0.4 - 3 v power good (only for tdfn3 ?? 3 - 10 package) i pok pok leakage current v pok =5v - 0.1 1 m a vfb is from low to target value (pok goes high) 85 90 95 % vfb falling, pok goes low 45 50 55 % v pok pok threshold vfb rising, pok goes low 120 125 130 % pok delay time vref=90% regulat ion to pok goes high - 1.5 - ms note 4: guaranteed by design, not production tested. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 0 . 79 0 . 795 0 . 8 0 . 805 0 . 81 - 20 0 20 40 60 80 100 r e f e r e n c e v o l t a g e ( v ) reference voltage vs . junction temperature v cc = 12 v 120 junction temperature ( o c ) s w i t c h i n g f r e q u e n c y ( k h z ) 250 260 270 280 290 300 310 320 330 340 350 switching frequency vs . junction temperature - 20 0 20 40 60 80 100 120 junction temperature ( o c ) 4 5 6 7 8 9 10 11 12 13 input voltage ( v ) o u t p u t v o l t a g e v a r i a t i o n ( % ) line regulation - 0 . 3 - 0 . 2 - 0 . 1 0 0 . 1 0 . 2 0 . 3 vcc = 12 v il = 0 a vout = 1 . 2 v 0 2 4 6 8 10 - 0 . 1 0 0 . 1 0 . 2 - 0 . 2 load regulation output current ( a ) o u t p u t v o l t a g e v a r i a t i o n ( % ) - 20 0 20 40 60 80 100 120 8 . 6 9 . 4 9 . 8 10 . 2 10 . 6 11 11 . 4 o c s e t c u r r e n t s o u r c e ( a ) i ocset vs . junction temperature 9 junction temperature ( o c ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . p o w e r o n power off e n a b l e s h u t d o w n ch 1 : v in , 5 v / div ch 2 : v out , 1 v / div time : 1 ms / div ch 3 : v ugate , 10 v / div ch 2 : v out , 1 v / div ch 3 : v u gate , 10 v / div time : 50 ms / div ch 1 : v in , 5 v / div ch 1 : v comp , 1 v / div ch 2 : v out , 1 v / div time : 1 ms / div ch 3 : v ugate , 10 v / div ch 1 : v comp , 1 v / div ch 2 : v out , 1 v / div time : 1 ms / div ch 3 : v ugate , 10 v / div 1 3 2 v in v out v ugate 1 3 2 v in v out v ugate v comp v out v ugate 1 3 2 v comp v out v ugate 1 3 2 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . o v e r - c u r r e n t p r o t e c t i o n under-voltage protection u g a t e f a l l i n g u g a t e r i s i n g ch 1 : v out , 1 v / div ch 2 : v phase , 10 v / div ch 3 : i l , 10 a / div time : 10 us / div ch 1 : v out , 1 v / div ch 2 : i l , 10 a / div time : 1 ms / div ch 1 : v ugate , 20 v / div ch 2 : v lgate , 10 v / div ch 3 : v phase , 10 v / div time : 20 ns / div ch 1 : v ugate , 20 v / div ch 2 : v lgate , 10 v / div ch 3 : v phase , 10 v / div time : 20 ns / div 1 3 r ocset = 6 . 8 k [ , r ds ( low side ) = 10 . 5 m [ 2 v out v phase i l 1 2 v out i l v ugate v lgate v phase 1 3 2 v ugate v lgate v phase 1 3 2 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . p o w e r o k load transient ch 1 : v out , 1 v / div ch 2 : p ok , 5 v / div time : 1 ms / div ch 1 : v out , 50 mv / div , ac ch 2 : i out , 5 a / div time : 200 us / div 1 2 pok v out 1 2 v out i out free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 0 p i n d e s c r i p t i o n pin no. tdfn3x3 - 10 name function 1 boot this pin provides the bootstrap voltage to the high - side gate driver for driving the n - channel mosfet. an external capacitor (0.1 m f at least) from phase to boot, an internal switch generates the bootstrap volta ge for the high - side gate d r iver (ugate). 2 ugate high - side g ate dr iver output. this pin is the gate driver for high - side mosfet. 3 phase this pin is the return path for the high - side gate driver. connect ing this pin to the high - side mosfet source and co nnect a capacitor to boot for the bootstrap voltage. this pin is also used to monitor the voltage drop across the low - side mosfet for o ver - current protection. 4 lgate/ ocset low - side gate driver output and over - current setting input. this pin is the gate driver for low - side mosfet. it also used to set the maximum inductor current. refer to the section in ? function description ? for detail. 5 vcc power s upply i nput. connect a nominal 5v to 12v power supply voltage to this pin. a power - on reset function moni tors the input voltage at this pin. it is recommended that a decoupling capacitor (1 m f to 10 m f) be connected to gnd for noise decoupling. 6 fb feedback i nput of converter . the converter senses feedback voltage via fb and regulate s the fb voltage at 0.8v. connecting fb with a resistor - divider from the output set s the output voltage of the converter . 7 comp this is a multiplexed pin. during soft - start and normal converter operation, this pin represents the output of the error amplifier. it is used to compensate the regulation control loop in combination with the fb pin . pulling comp low (v disable = 0. 4 v max.) will shut down the controller . when the pull - down device is released, the comp pin will start to rise. when the comp pin rises above the v disable trip point, the APW8723 will begin a new i nitialization and soft - start cycle. 8 pok pok is an open drain output used to indicate the status of the output voltage. connect the pok pin to 5 to 12v through a pull - high resistor. 9 ofs reference voltage offset setting. must connect this pin to refout pin through a resister when APW8723 is used. o perate d an installation that can make bi - direction current flow within limits to develop a positive and negative voltage difference between ofs pin and refout pin, then the APW8723 can adjust reference voltage . 10 refout 0.8v reference output. bypass to gnd with a capacitor ( 0.01 m f to 0.1 m f ). 11 (expo sed pad) gnd signal and power ground. connect this pad to the system ground plan for good thermal conductivity. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 1 b l o c k d i a g r a m sample and hold to lgate v rocset soft start and fault logic gate control v rocset sense low side error amplifier oscillator pwm comparator uvp comparator regulator v ref ( 0 . 8 v typical ) izcmp phase ugate boot comp gnd fb vcc soft - start inhibit i ocset ( 10 a typical ) lgate ovp comparator 1 . 25 0 . 5 0 . 4 v disable vcc ofs v ref ( 0 . 8 v typical ) refout power - on reset uvlo free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 2 t y p i c a l a p p l i c a t i o n c i r c u i t phase fb gnd vcc lgate / ocset comp apw 8723 ( tdfn 3 * 3 - 10 ) c in 2 220 m f x 2 c in 1 1 m f l 1 0 . 5 h v in v out ugate c out 1000 m f x 2 vcc supply ( 5 ~ 12 v ) boot r 3 2 k w 5 7 6 exposed pad 4 3 2 1 r 4 2 r 2 c 4 1 m f q 1 apm 310 9 q 2 apm 3106 on off c 3 0 . 1 m f r ocset q 3 2 n 7002 ofs 9 pok 8 r 5 100 k w refout r 1 1 k w 10 c 5 0 . 1 m f r offset current controller c 1 33 pf r 2 10 k w c 2 47 nf free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 3 f u n c t i o n d e s c r i p t i o n p o w e r - o n - r e s e t ( p o r ) t h e p o w e r - o n - r e s e t ( p o r ) f u n c t i o n o f a p w 8 7 2 3 c o n - t i n u a l l y m o n i t o r s t h e i n p u t s u p p l y v o l t a g e ( v c c ) a n d e n - s u r e s t h a t t h e i c h a s s u f f i c i e n t s u p p l y v o l t a g e a n d c a n w o r k w e l l . t h e p o r f u n c t i o n i n i t i a t e s a s o f t - s t a r t p r o c e s s w h i l e t h e v c c v o l t a g e j u s t e x c e e d s t h e p o r t h r e s h o l d ; t h e p o r f u n c t i o n a l s o i n h i b i t s t h e o p e r a t i o n s o f t h e i c w h i l e t h e v c c v o l t a g e f a l l s b e l o w t h e p o r t h r e s h o l d . s o f t - s t a r t the APW8723 builds in a soft-start function about 2ms (typ.) interval, which controls the output voltage rising as well as limiting the current surge at the start-up. during soft-start, an internal ramp voltage connected to the one of the positive inputs of the error amplifier replaces the reference voltage (0.8v typical) until the ramp voltage reaches the reference voltage. the soft-start circuit inter- val is shown as figure 1. f i g u r e 1 . s o f t - s t a r t i n t e r v a l o v e r - c u r r e n t p r o t e c t i o n o f t h e p w m c o n v e r t e r the over-current function protects the switching converter against over-current or short-circuit conditions. the con- troller senses the inductor current by detecting the drain- to-source voltage which is the product of the inductor?s current and the on-resistance of the low-side mosfet during it?s on-state. this method enhances the converter?s efficiency and reduces cost by eliminating a current sens- ing resistor required. a r e s i s t o r ( r o c s e t ) , c o n n e c t e d f r o m t h e l g a t e / o c s e t t o g n d , p r o g r a m s t h e o v e r - c u r r e n t t r i p l e v e l . b e f o r e t h e i c i n i t i a t e s a s o f t - s t a r t p r o c e s s , a n i n t e r n a l c u r r e n t s o u r c e , i o c s e t ( 1 0 m a t y p i c a l ) , f l o w i n g t h r o u g h t h e r o c s e t d e v e l o p s a v o l t a g e ( v r o c s e t ) a c r o s s t h e r o c s e t . t h e d e v i c e h o l d s v r o c s e t a n d s t o p s t h e c u r r e n t s o u r c e i o c s e t d u r i n g n o r m a l o p e r a t i o n . w h e n t h e v o l t a g e a c r o s s t h e l o w - s i d e m o s f e t e x c e e d s t h e v r o c s e t , t h e a p w 8 7 2 3 t u r n s o f f t h e h i g h s i d e a n d l o w - s i d e m o s f e t , a n d t h e d e v i c e w i l l e n t e r h i c c u p m o d e u n t i l t h e o v e r - c u r r e n t p h e n o m e n o n i s r e l e a s e d . the APW8723 has an internal ocp voltage, v ocp_max , and the value is 0.621v(minmum). when the r ocset x i ocset exceed 0.621v or the r ocset is floating or not connected, the v rocset will be the default value 0.621v. the over cur- rent threshold would be 0.621v across low-side mosfet. the threshold of the valley inductor current limit is there- fore given by: ) side low ( r r i i ) on ( ds ocset ocset limit - = for the over-current is never occurred in the normal oper- ating load range, the variation of all parameters in the above equation should be considered: - the r ds(on) of low-side mosfet is varied by tempera- ture and gate to source voltage. users should deter- mine the maximum r ds(on) by using the manufacturer?s datasheet. - the minimum i ocset (9 m a) and minimum r ocset should be used in the above equation. - note that the i limit is the current flow through the low- side mosfet; i limit must be greater than valley inductor current which is output current minus the half of induc- tor ripple current. 2 i i i ) max ( out limit d - > where d i = output inductor ripple current - the overshoot and transient peak current also should be considered. t 1 t 2 t 3 v vcc v out time voltage ( v ) v pok pok delay time ocset count start ( ocset duratiom , t 2 - t 1 , less than 0 . 474 ms ) 0 . 9 x v ref ocset count completed t 4 t 0 soft start time free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f a l l s b e l o w t h e f a l l i n g u v p t h r e s h o l d ( 5 0 % v r e f ) , a f a u l t s i g n a l i s i n t e r n a l l y g e n e r a t e d a n d t h e d e v i c e t u r n s o f f h i g h - s i d e a n d l o w - s i d e m o s f e t s . t h e d e v i c e w i l l e n t e r s h i c - c u p m o d e u n t i l t h e u v p i s r e l e a s e d . o v e r - v o l t a g e p r o t e c t i o n ( o v p ) t h e o v e r - v o l t a g e p r o t e c t i o n m o n i t o r s t h e f b v o l t a g e t o p r e v e n t t h e o u t p u t f r o m o v e r - v o l t a g e c o n d i t i o n . w h e n t h e o u t p u t v o l t a g e r i s e s a b o v e 1 2 5 % o f t h e n o m i n a l o u t p u t v o l t a g e , t h e a p w 8 7 2 3 t u r n s o f f t h e h i g h - s i d e m o s f e t a n d t u r n s o n t h e l o w - s i d e m o s f e t u n t i l t h e o u t p u t v o l t - a g e f a l l s b e l o w 1 0 5 % , t h e o v p c o m p a r a t o r i s d i s e n - g a g e d a n d b o t h h i g h - s i d e a n d l o w - s i d e d r i v e r s t u r n o f f . t h i s o v p s c h e m e o n l y c l a m p s t h e v o l t a g e o v e r s h o o t a n d d o e s n o t i n v e r t t h e o u t p u t v o l t a g e w h e n o t h e r w i s e a c t i - v a t e d w i t h a c o n t i n u o u s l y h i g h o u t p u t f r o m l o w - s i d e m o s f e t d r i v e r . i t ? s a c o m m o n p r o b l e m f o r o v p s c h e m e s w i t h a l a t c h . o n c e a n o v e r - v o l t a g e f a u l t c o n d i t i o n i s s e t , i t c a n b e r e s e t b y r e l e a s i n g c o m p o r t o g g l i n g v c c p o w e r - o n - r e s e t s i g n a l . s h u t d o w n a n d e n a b l e the APW8723 can be shut down or enabled by pulling low the voltage on comp. the comp is a dual-function pin. during normal operation, this pin represents the out- put of the error amplifier. it is used to compensate the regulation control loop in combination with the fb pin. pulling the comp low (v disable = 0.4v maximum) places a d a p t i v e s h o o t - t h r o u g h p r o t e c t i o n o f t h e p w m c o n - v e r t e r the gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off the low-side mosfet, the lgate voltage is monitored until it is below 1.5v threshold, at which time the ugate is released to rise after a constant delay. during turn-off of the high-side mosfet, the ugate-to- phase voltage is also monitored until it is below 1.5v threshold, at which time the lgate is released to rise after a constant delay. u n d e r - v o l t a g e p r o t e c t i o n t h e u n d e r - v o l t a g e f u n c t i o n m o n i t o r s t h e v o l t a g e o n f b ( v f b ) b y u n d e r - v o l t a g e ( u v ) c o m p a r a t o r t o p r o t e c t t h e p w m c o n v e r t e r a g a i n s t s h o r t - c i r c u i t c o n d i t i o n s . w h e n t h e v f b o v e r - t e m p e r a t u r e p r o t e c t i o n ( o t p ) w h e n t h e j u n c t i o n t e m p e r a t u r e i n c r e a s e s a b o v e t h e r i s - i n g t h r e s h o l d t e m p e r a t u r e t o t r , t h e i c w i l l e n t e r t h e o v e r - t e m p e r a t u r e p r o t e c t i o n s t a t e t h a t s u s p e n d s t h e p w m , w h i c h f o r c e s t h e u g a t e a n d l g a t e g a t e d r i v e r s o u t p u t l o w . t h e t h e r m a l s e n s o r a l l o w s t h e c o n v e r t e r s t o s t a r t a s t a r t - u p p r o c e s s a n d r e g u l a t e t h e o u t p u t v o l t a g e a g a i n a f t e r t h e j u n c t i o n t e m p e r a t u r e c o o l s b y 4 0 o c . t h e o t p i s d e s i g n e d w i t h a 4 0 o c h y s t e r e s i s t o l o w e r t h e a v - e r a g e t j d u r i n g c o n t i n u o u s t h e r m a l o v e r l o a d c o n d i t i o n s , w h i c h i n c r e a s e s l i f e t i m e o f t h e a p w 8 7 2 3 . the controller into shutdown mode which ugate and lgate are pulled to phase and gnd respectively. when the pull-down device is released, the comp volt- age will start to rise. when the comp voltage rises above the v disable threshold, the APW8723 will begin a new ini- tialization and soft-start process. r e f e r e n c e v o l t a g e o f f s e t f u n c t i o n r for some special applications like over-clocking purpose or variety output voltage choice, the APW8723 can pro- vide reference voltage offset function to support these applications. it must connect ofs pin to refout pin through a resister (r offset ) when APW8723 is used. op- erated an installation that can make bi-direction cur- rent flow within limits to develop a positive and negative voltage difference between ofs pin and refout pin, then the APW8723 can adjust reference voltage. it is de- termined by: ( ) offset offset refout ofs r i v v = when this function is inhibited, the r offset should be short to ensure that v ofs equals v refout . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 5 a p p l i c a t i o n i n f o r m a t i o n o u t p u t v o l t a g e s e l e c t i o n the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier, and the reference voltage is 0.8v. the output voltage is determined by: w h e r e r 1 i s t h e r e s i s t o r c o n n e c t e d f r o m v o u t t o f b a n d r 2 i s t h e r e s i s t o r c o n n e c t e d f r o m f b t o t h e g n d . ? ? ? ? ? + = 2 1 out r r 1 0.8 v o u t p u t c a p a c i t o r s e l e c t i o n t h e s e l e c t i o n o f c o u t i s d e t e r m i n e d b y t h e r e q u i r e d e f f e c - t i v e s e r i e s r e s i s t a n c e ( e s r ) a n d v o l t a g e r a t i n g r a t h e r t h a n t h e a c t u a l c a p a c i t a n c e r e q u i r e m e n t . t h e r e f o r e , s e l e c t i n g h i g h p e r f o r m a n c e l o w e s r c a p a c i t o r s i s i n t e n d e d f o r s w i t c h i n g r e g u l a t o r a p p l i c a t i o n s . i n s o m e a p p l i c a t i o n s , m u l t i p l e c a p a c i t o r s h a v e t o b e p a r a l l e l e d t o a c h i e v e t h e d e s i r e d e s r v a l u e . i f t a n t a l u m c a p a c i t o r s a r e u s e d , m a k e s u r e t h e y a r e s u r g e t e s t e d b y t h e m a n u f a c t u r e s . i f i n d o u b t , c o n s u l t t h e c a p a c i t o r s m a n u f a c t u r e r . i n p u t c a p a c i t o r s e l e c t i o n the input capacitor is chosen based on the voltage rat- ing and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2 where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the ca- pacitors manufacturer. for high frequency decoupling, a ceramic capacitor be- tween 0.1 m f to 1 m f can connect between vcc and ground pin. i n d u c t o r s e l e c t i o n t h e i n d u c t a n c e o f t h e i n d u c t o r i s d e t e r m i n e d b y t h e o u t - p u t v o l t a g e r e q u i r e m e n t . t h e l a r g e r t h e i n d u c t a n c e , t h e l o w e r t h e i n d u c t o r ? s c u r r e n t r i p p l e . t h i s w i l l t r a n s l a t e i n t o l o w e r o u t p u t r i p p l e v o l t a g e . t h e r i p p l e c u r r e n t a n d r i p p l e v o l t a g e c a n b e a p p r o x i m a t e d b y : w h e r e f s i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . d v o u t = i r i p p l e x e s r in out sw out in ripple v v l f v v i - = a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a s m a l l e r i n - d u c t o r w i l l g i v e t h e r e g u l a t o r a f a s t e r l o a d t r a n s i e n t r e - s p o n s e a t t h e e x p e n s e o f h i g h e r r i p p l e c u r r e n t a n d v i c e v e r s a . t h e m a x i m u m r i p p l e c u r r e n t o c c u r s a t t h e m a x i - m u m i n p u t v o l t a g e . a g o o d s t a r t i n g p o i n t i s t o c h o o s e t h e r i p p l e c u r r e n t t o b e a p p r o x i m a t e l y 3 0 % o f t h e m a x i m u m o u t p u t c u r r e n t . o n c e t h e i n d u c t a n c e v a l u e h a s b e e n c h o s e n , s e l e c t i n g a n i n d u c t o r i s c a p a b l e o f c a r r y i n g t h e r e q u i r e d p e a k c u r - r e n t w i t h o u t g o i n g i n t o s a t u r a t i o n . i n s o m e t y p e s o f i n d u c t o r s , e s p e c i a l l y c o r e t h a t i s m a k e o f f e r r i t e , t h e r i p p l e c u r r e n t w i l l i n c r e a s e a b r u p t l y w h e n i t s a t u r a t e s . t h i s w i l l r e s u l t i n a l a r g e r o u t p u t r i p p l e v o l t a g e . c o m p e n s a t i o n t h e o u t p u t l c f i l t e r o f a s t e p d o w n c o n v e r t e r i n t r o d u c e s a d o u b l e p o l e , w h i c h c o n t r i b u t e s w i t h - 4 0 d b / d e c a d e g a i n s l o p e a n d 1 8 0 d e g r e e s p h a s e s h i f t i n t h e c o n t r o l l o o p . a c o m p e n s a t i o n n e t w o r k b e t w e e n c o m p p i n a n d g r o u n d s h o u l d b e a d d e d . t h e s i m p l e s t l o o p c o m p e n s a t i o n n e t - w o r k i s s h o w n i n f i g u r e 5 . t h e o u t p u t l c f i l t e r c o n s i s t s o f t h e o u t p u t i n d u c t o r a n d o u t p u t c a p a c i t o r s . t h e t r a n s f e r f u n c t i o n o f t h e l c f i l t e r i s g i v e n b y : t h e p o l e s a n d z e r o o f t h i s t r a n s f e r f u n c t i o n a r e : t h e f l c i s t h e d o u b l e p o l e s o f t h e l c f i l t e r , a n d f e s r i s t h e z e r o i n t r o d u c e d b y t h e e s r o f t h e o u t p u t c a p a c i t o r . 1 c esr s c l s c esr s 1 out out 2 out + + + = gain lc out c l p 2 1 = f lc out c esr p 2 1 = f esr free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 6 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) f i g u r e 3 . t h e l c f i l t e r g a i n & f r e q u e n c y t h e p w m m o d u l a t o r i s s h o w n i n f i g u r e 4 . t h e i n p u t i s t h e o u t p u t o f t h e e r r o r a m p l i f i e r a n d t h e o u t p u t i s t h e p h a s e n o d e . t h e t r a n s f e r f u n c t i o n o f t h e p w m m o d u l a t o r i s g i v e n b y : f i g u r e 4 . t h e p w m m o d u l a t o r t h e c o m p e n s a t i o n c i r c u i t i s s h o w n i n f i g u r e 5 . r 2 a n d c 2 i n t r o d u c e a z e r o a n d c 1 i n t r o d u c e s a p o l e t o r e d u c e t h e s w i t c h i n g n o i s e . t h e t r a n s f e r f u n c t i o n o f e r r o r a m p l i - f i e r i s g i v e n b y : t h e p o l e a n d z e r o o f t h e c o m p e n s a t i o n n e t w o r k a r e : c o m p e n s a t i o n ( c o n t . ) f i g u r e 5 . c o m p e n s a t i o n n e t w o r k t h e c l o s e d l o o p g a i n o f t h e c o n v e r t e r c a n b e w r i t t e n a s : f i g u r e 6 s h o w s t h e c o n v e r t e r g a i n a n d t h e f o l l o w i n g g u i d e - l i n e s w i l l h e l p t o d e s i g n t h e c o m p e n s a t i o n n e t w o r k . 1 . s e l e c t t h e d e s i r e d z e r o c r o s s o v e r f r e q u e n c y f o : ( 1 / 5 ~ 1 / 1 0 ) x f s w > f o > f z u s e t h e f o l l o w i n g e q u a t i o n t o c a l c u l a t e r 2 : f esr f lc frequency -40db/dec -20db/dec gain v osc pwm comparator driver driver output of error amplifier v in phase figure 2. the output lc filter l c out esr output phase osc in pwm v v = gain d w h e r e : g m = 6 6 7 m a / v ? ? ? ? ? ? ? + = = sc1 1 // sc2 1 r2 gm gm o amp z gain c1 c2 c1 r2 c1 c2 s s c2 r2 1 s gm + + + = ? ? ? ? ? ? ? ? ? ? c2 r2 2 1 p = f z c2 c1 c2 c1 r2 2 1 + p = p f c1 v out r3 r1 r2 error amplifier v ref c2 comp fb - + amp pwm lc gain gain gain + r3 r1 r3 gm f r3 r3 r1 2 f f v v r2 o lc esr in osc + d = free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) c o m p e n s a t i o n ( c o n t . ) f i g u r e 6 . c o n v e r t e r g a i n & f r e q u e n c y m o s f e t s e l e c t i o n t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s i s d e t e r - m i n e d b y t h e r d s ( o n ) , r e v e r s e t r a n s f e r c a p a c i t a n c e ( c r s s ) , a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e u p p e r a n d l o w e r m o s f e t , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p u p p e r = i o u t 2 ( 1 + t c ) ( r d s ( o n ) ) d + ( 0 . 5 ) ( i o u t ) ( v i n ) ( t s w ) f s w p l o w e r = i o u t 2 ( 1 + t c ) ( r d s ( o n ) ) ( 1 - d ) w h e r e i o u t i s t h e l o a d c u r r e n t t c i s t h e t e m p e r a t u r e d e p e n d e n c y o f r d s ( o n ) f s w i s t h e s w i t c h i n g f r e q u e n c y t s w i s t h e s w i t c h i n g i n t e r v a l d i s t h e d u t y c y c l e n o t e t h a t b o t h m o s f e t s h a v e c o n d u c t i o n l o s s e s w h i l e t h e u p p e r m o s f e t i n c l u d e s a n a d d i t i o n a l t r a n s i t i o n l o s s . t h e s w i t c h i n g i n t e r n a l , t s w , i s t h e f u n c t i o n o f t h e r e v e r s e t r a n s f e r c a p a c i t a n c e c r s s . f i g u r e 7 i l l u s t r a t e s t h e s w i t c h - i n g w a v e f o r m i n t e r n a l o f t h e m o s f e t . t h e ( 1 + t c ) t e r m f a c t o r s i n t h e t e m p e r a t u r e d e p e n d e n c y o f t h e r d s ( o n ) a n d c a n b e e x t r a c t e d f r o m t h e ? r d s ( o n ) v s t e m - p e r a t u r e ? c u r v e o f t h e p o w e r m o s f e t . layout consideration in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at 300khz,the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is car- rying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting imped f i g u r e 7 . s w i t c h i n g w a v e f o r m a c r o s s m o s f e t 2 . p l a c e t h e z e r o f z b e f o r e t h e l c f i l t e r d o u b l e p o l e s f l c : f z = 0 . 7 5 x f l c c a l c u l a t e t h e c 2 b y t h e e q u a t i o n : 3 . s e t t h e p o l e a t t h e h a l f t h e s w i t c h i n g f r e q u e n c y : f p = 0 . 5 x f s w c a l c u l a t e t h e c 1 b y t h e e q u a t i o n : v o l t a g e a c r o s s d r a i n a n d s o u r c e o f m o s f e t time v ds t sw lc f 0.75 r2 2 1 c2 p = 1 f c2 r2 c2 c1 sw - p = f lc f esr f p =0.5f sw f z =0.75f lc f o frequency pwm & filter gain compensation gain converter gain gain 20 . log(gm . r2) d v osc v in 20 . log free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) layout consideration (cont.) figure 8. layout guidelines - keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ug and lg) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimiz- ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the up- per mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking. - the r ocset resistance should be placed near the ic as close as possible. ances and the magnitude of voltage spike. and signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: vcc boot phase ugate lgate v in v out l o a d apw 8723 r ocset close to ic recommended minimum footprint 0 . 3 0 mm 1 . 75 mm ground plane for thermalpad thermalvia diameter 12 mil x 5 0 . 27 5 mm 0 . 75 mm 0 . 50 mm tdfn 3 x 3 - 10 l and pattern r ecommendation 2 . 7 0 m m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 1 9 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 d e pin 1 a a1 a3 b pin 1 corner d2 e 2 l e 0.70 0.069 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 note : 1. followed from jedec mo-229 veed-5. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 2 0 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 3.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity tdfn3x3 - 10 tape & reel 3000 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 2 1 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 3 x 3 - 1 0 user direction of feed c l a s s i f i c a t i o n p r o f i l e free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 2 2 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a p r . , 2 0 1 3 a p w 8 7 2 3 w w w . a n p e c . c o m . t w 2 3 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 free datasheet http:///

▲Up To Search▲

Price & Availability of APW8723

	To Download APW8723 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .