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Integrated Silicon Solution, Inc.
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| Part No. |
IS61VPD25636A-200TQ2I IS61VPD51218A-200B2I
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| Description |
256K x 36, 512k x 18 9 Mb synchronous PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 256K x 36 CACHE SRAM, 3.1 ns, PQFP100
256K x 36, 512k x 18 9 Mb synchronous PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 512k x 18 CACHE SRAM, 3.1 ns, PBGA119
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| File Size |
300.37K /
32 Page |
 View
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Download Datasheet
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
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| Part No. |
M38230G4-xxxFP M38230G4-xxxHP M38231G4-xxxHP M38232G4-xxxFP M38232G4-xxxHP M38233G4-xxxFP M38233G4-xxxHP M38234G4-xxxFP M38234G4-xxxHP M38235G4-xxxFP M38230G6-xxxFP M38230G6-xxxHP M38231G6-xxxFP M38231G6-xxxHP M38232G6-xxxFP M38232G6-xxxHP M38233G6-xxxFP M38233G6-xxxHP M38234G6-xxxFP M38234G6-xxxHP M38235G6-xxxFP M38235G6-xxxHP M38236G6-xxxHP M38237G6-xxxFP M38237G6-xxxHP M38238G6-xxxFP M38230G7-xxxFP M38230G7-xxxHP M38231G7-xxxFP M38231G7-xxxHP M38232G7-xxxFP M38232G7-xxxHP M38233G7-xxxFP M38233G7-xxxHP M38234G7-xxxFP M38234G7-xxxHP M38235G7-xxxFP M38235G7-xxxHP M38236G7-xxxFP M38236G7-xxxHP M38237G7-xxxFP M38237G7-xxxHP M38238G7-xxxFP M38238G7-xxxHP M38239G7-xxxFP M38239G7-xxxHP M38230G8-xxxFP M38230G8-xxxHP M38231G8-xxxFP M38231G8-xxxHP M38232G8-xxxFP M38232G8-xxxHP M38233G8-xxxFP M38233G8-xxxHP M38234G8-xxxFP M38234G8-xxxHP M38235G8-xxxFP M38235G8-xxxHP M38236G8-xxxFP M38236G8-xxxHP M38237G8-xxxFP M38237G8-xxxHP M38238G8-xxxFP M38238G8-xxxHP M38230GA-xxxFP M38230GA-xxxHP M38231GA-xxxFP M38231GA-xxxHP M38232GA-xxxFP M38232GA-xxxHP M38233GA-xxxFP M38233GA-xxxHP M38234GA-xxxFP M38234GA-xxxHP M38235GA-xxxFP M38235GA-xxxHP M38236GA-xxxFP M38236GA-xxxHP M38237GA-xxxFP M38237GA-xxxHP
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| Description |
18-Mbit (512k x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512k x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512k x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512k x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512k x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512k x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-bit CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-bit CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
901.80K /
76 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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