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Atmel
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| Part No. |
ATF1500A ATF1500AL
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| OCR Text |
...ds up to 125 mhz. with 32 logic macrocells and up to 36 inputs, it easily integrates logic from several ttl, ssi, msi and classic plds. the atf1500as global input and feedback architecture simplifies logic placement and eliminates pinout ch... |
| Description |
1500 gate electrically erasable CPLD, 5V, 44 pins
1500 gate electrically erasable low power CPLD, 5V, 44 pins
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| File Size |
366.33K /
17 Page |
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Xilinx
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| Part No. |
XC9536XV DS053 XC9536XV-SERIES
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| OCR Text |
...ecification
Features
* * 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) Optimized for high-performance 2.5V sys... |
| Description |
High-performance CPLD
From old datasheet system
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| File Size |
59.60K /
8 Page |
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it Online |
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N/A
Altera Corp
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| Part No. |
EPM7032SLC44-10 EPM7128ELC84-20 EPM7128ELC84-15 EPM7128ELC84-10P EPM7128ELC84-10 EPM7064SLI44-7
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| OCR Text |
... 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) ... |
| Description |
MAX 7000 Programmable Logic Device
COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,128-CELL,15NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,128-CELL,20NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,32-CELL,10NS PROP DELAY,LDCC,44PIN,PLASTIC
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| File Size |
436.37K /
62 Page |
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it Online |
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Altera
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| Part No. |
EPM7128SLC84-10
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| OCR Text |
... 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) ... |
| Description |
IC,COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC
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| File Size |
473.32K /
66 Page |
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it Online |
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lattice
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| Part No. |
LC4128V-10T100I
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| OCR Text |
...
Ease of Design
* Enhanced macrocells with individual clock, reset, preset and clock enable controls * Up to four global OE controls * Individual local OE control per I/O pin * Excellent First-Time-FitTM and refit * Fast path, SpeedLoc... |
| Description |
IC,COMPLEX-EEPLD,128-CELL,10.5NS PROP DELAY,QFP,100PIN,PLASTIC
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| File Size |
264.92K /
83 Page |
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it Online |
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Lattice Semiconductor Corp
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| Part No. |
LC4256 LC4384V75T176C LC4512 LC4128 LC4064 LC4032
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| OCR Text |
...to 80 PTs per output * Enhanced macrocells with individual clock, reset, preset and clock enable controls * Up to four global OE controls * Individual local OE control per I/O pin * Excellent First-Time-FitTM and refit * Fast path, SpeedLoc... |
| Description |
IC,COMPLEX-EEPLD,256-CELL,3.8NS PROP DELAY,QFP,100PIN,PLASTIC
IC,COMPLEX-EEPLD,384-CELL,10NS PROP DELAY,QFP,176PIN,PLASTIC
IC,COMPLEX-EEPLD,512-CELL,4.5NS PROP DELAY,QFP,176PIN,PLASTIC
System Programmable Super Fast High Density PLDs
IC,COMPLEX-EEPLD,64-CELL,3.2NS PROP DELAY,QFP,100PIN,PLASTIC
IC,COMPLEX-EEPLD,32-CELL,3.2NS PROP DELAY,TQFP,48PIN,PLASTIC
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| File Size |
740.67K /
91 Page |
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Xilinx
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| Part No. |
XC95144XL 95144XL XC95144XL-SERIES
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| OCR Text |
...tem frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins) Optimized for high-performance 3... |
| Description |
High Performance CPLD
From old datasheet system
Preliminary Product Specification
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| File Size |
78.77K /
9 Page |
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it Online |
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Price and Availability
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