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GSI Technology, Inc.
http://
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| Part No. |
GS882ZV18BB-200 GS882ZV36BB-200 GS882ZV18BB-300 GS882ZV36BB-300 GS882ZV18BB-300I GS882ZV36BB-300I GS882ZV18BD-300 GS882ZV36BD-300 GS882ZV18BD-333 GS882ZV36BD-333 GS882ZV18BGB-200I GS882ZV36BGD-300I GS882ZV18BGB-333
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| OCR Text |
...near burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operati ons must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished... |
| Description |
9Mb Pipelined and Flow Through Synchronous NBT SRAM 512K X 18 ZBT SRAM, 4.5 ns, PBGA119
9Mb Pipelined and Flow Through Synchronous NBT SRAM 256K X 36 ZBT SRAM, 5 ns, PBGA119
9Mb Pipelined and Flow Through Synchronous NBT SRAM 256K X 36 ZBT SRAM, 5 ns, PBGA165
9Mb Pipelined and Flow Through Synchronous NBT SRAM 512K X 18 ZBT SRAM, 6.5 ns, PBGA119
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| File Size |
616.54K /
33 Page |
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Download Datasheet
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飞思卡尔半导体(中国)有限公司
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| Part No. |
DSP56857BUE
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| OCR Text |
...el host interface, two enhanced synchr onous serial interfaces (essi), one serial peripheral interface (spi), two serial communications interfaces (sci), and one quad timer. the essis, spi, scis io and quad timer can be used as general ... |
| Description |
16-bit Digital Signal Controllers
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| File Size |
680.10K /
53 Page |
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it Online |
Download Datasheet |
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http://
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| Part No. |
AT89C5132-ROTIL
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| OCR Text |
... sclk is the oversampling clock synchr onized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an exter... |
| Description |
USB Microcontroller with 64K Bytes Flash Memory
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| File Size |
1,498.70K /
181 Page |
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it Online |
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GSI Technology, Inc.
http://
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| Part No. |
GS8160E36T-200I GS8160E36T-150I GS8160E36T-166 GS8160E36T-133I GS8160E36T-166I GS8160E36T-250 GS8160E18GT-133IT
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| OCR Text |
...evice now finds application in synchr onous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os , chip enables (e1 , e2, e3 ), address burst control inputs (adsp , adsc , adv ), ... |
| Description |
1M X 18 CACHE SRAM, 8.5 ns, PQFP100
1M x 18, 512K x 36 18Mb Sync Burst SRAMs 512K X 36 CACHE SRAM, 5.5 ns, PQFP100
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| File Size |
443.16K /
25 Page |
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it Online |
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Price and Availability
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