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Renesas Electronics Corporation.
Renesas Electronics, Corp.
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| Part No. |
M38030F2L-XXXHP M38030F2L-XXXKP M38030F2L-XXXSP M38030F2L-XXXWG M38030MaL-XXXWG M38030MaL-XXXKP M38030FaL-XXXSP M38031FaL-XXXHP M38030FaL-XXXWG M38030MaL-XXXHP M38030FaL-XXXKP M38031FaL-XXXKP M38030FaL-XXXHP M38031FaL-XXXSP M38031FaL-XXXWG M38030MaL-XXXSP M38030F3L-XXXHP M38030F3L-XXXWG M38030M3L-XXXKP M38030F3L-XXXSP M38030F3L-XXXKP M38030M3L-XXXHP M38030FBL-XXXWG M38030MBL-XXXHP M38030FBL-XXXHP M38030FBL-XXXSP M38030MBL-XXXKP M38030M2L-XXXHP M38030M2L-XXXKP M38030M2L-XXXSP M38030M2L-XXXWG M38031F2L-XXXHP M38031F2L-XXXKP M38031F2L-XXXSP M38031F2L-XXXWG M38030FB-XXXHP M38031FBL-XXXSP M38035MBL-XXXSP M38038FBL-XXXSP M38039FBL-XXXSP M38030MBL-XXXSP M38036MBL-XXXSP M38037FBL-XXXSP M38037MBL-XXXSP M38036FBL-XXXSP M38038MBL-XXXSP M38031FC-XXXHP M38031FC-XXXKP M38031FC-XXXWG M38031FCL-XXXHP M38031FCL-XXXKP M38031FCL-XXXSP M38031FCL-XXXWG M38031F5-XXXKP M38031F5-XXXSP M38031F5-XXXWG M38031F5L-XXXHP M38031F5L-XXXKP M38031F5L-XXXSP M38031F5L-XXXWG M38030F1-XXXHP M38030F1-XXXKP M38030F1-XXXSP M38030F1-XXXWG M38030F1L-XXXHP M38030F1L-XXXKP M38030F1L-XXXSP M38030F1L-XXXWG M38031F1-XXXKP M38031F1-XXXWG M38031F1L-XXXHP M38031F1L-XXXKP M38031F6-XXXHP M38031F6-XXXKP M38031F6-XXXSP M38031F6-XXXWG M
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| Description |
256 Kbit (32K x 8) nvSRaM; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x 8) Static RaM; Density: 256 Kb; Organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V;
Three-PLL General Purpose FLaSH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
8-Mbit (512K x 16) Static RaM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V;
9-Mbit (256K x 36/512K x 18) Pipelined SRaM; architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRaM; architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
18-Mbit QDR(TM)-II SRaM 4-Word Burst architecture; architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C
18-Mbit QDR(TM)-II SRaM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRaM with NoBL(TM) architecture; architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 2.4 to 2.6 V
4-Mbit (512K x 8) Static RaM; Density: 4 Mb; Organization: 512Kb x 8; Vcc (V): 4.50 to 5.50 V;
4-Mbit (256K x 16) Static RaM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V;
64K x 16 Static RaM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
1-Mbit (64K x 16) Static RaM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined SRaM; architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
1-Mbit (64K x 16) Static RaM; Density: 1 Mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
4 Mbit (512K x 8/256K x 16) nvSRaM; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
4 Mbit (512K x 8/256K x 16) nvSRaM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
16-Mbit (1M x 16 / 2M x 8) Static RaM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 4.50 to 5.50 V;
4K x 16/18 and 8K x 16/18 Dual-Port Static RaM with SEM, INT, BUSY; Density: 128 Kb; Organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns
9-Mbit (256K x 36/512K x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through SRaM with NoBL(TM) architecture; architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V
9-Mbit (256K x 36/512K x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
8-Mbit (512K x 16) Static RaM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 4.50 to 5.50 V;
9-Mbit (256K x 36/512K x 18) Flow-Through SRaM; architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RaM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRaM; architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
4-Mbit (256K x 16) Static RaM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1024K x 8) Static RaM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
18-Mbit (512K x 36/1M x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RaM; Density: 4 Mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1M x 8) Static RaM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: -40 to 85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C
18-Mbit (512K x 36/1M x 18) Flow-Through SRaM with NoBL(TM) architecture; architecture: NoBL, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
512K x 8 Static RaM; Density: 4 Mb; Organization: 512Kb x 8; Vcc (V): 4.5 to 5.5 V;
18-Mbit (512K x 36/1M x 18) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 2.4 to 2.6 V
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C
2M x 8 Static RaM; Density: 16 Mb; Organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;
16 Mbit (512K X 32) Static RaM; Density: 16 Mb; Organization: 512Kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C
8-Mbit (1M x 8) Static RaM; Density: 8 Mb; Organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2-Mbit (128K x 16) Static RaM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V;
16-Mbit (1M x 16) Static RaM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (256K x 18) Pipelined DCD Sync SRaM; architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RaM; Density: 512 Kb; Organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (128K x 36) Pipelined SRaM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RaM; Density: 16 Mb; Organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBL(R) 2 Mbit (128K x 16) Static RaM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) XDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4
2-Mbit (128K x 16) Static RaM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
4-Mbit (128K x 36) Pipelined Sync SRaM; architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
18-Mbit DDR-II SRaM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Three-PLL General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
8-Mbit (512K x 16) MoBL(R) Static RaM; Density: 8 Mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRaM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -40 to 85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RaM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBL(R) 1 Mbit (128K x 8) Static RaM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
18-Mbit QDR(TM)-II SRaM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1-Mbit (128K x 8) Static RaM; Density: 1 Mb; Organization: 128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机
4-Mbit (256K x 18) Pipelined Sync SRaM; architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2-Mbit (64K x 32) Pipelined Sync SRaM; architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RaM; Density: 2 Mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
2-Mbit (256K x 8) Static RaM; Density: 2 Mb; Organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机
Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C 单芯位CMOS微机
Three-PLL General Purpose FLaSH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 18; Operating Range: -40 to 85 C 单芯位CMOS微机
-bit aVR Microcontroller with 8K Bytes In- System Programmable Flash 位aVR微控制器具有8K字节的系统内可编程闪
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 32 MHz; Output Frequency Range: 4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
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| File Size |
1,602.57K /
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Data Delay Devices, Inc...
DaTa DELaY DEVICES INC
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| Part No. |
1504 1504SERIES 1504-600F 1504-80B 1504-80C 1504-75D 1504-250B 1504-250G 1504-25a 1504-25D 1504-160C 1504-160F 1504-360E 1504-360F 1504-375D 1504-75a 1504-450E 1504-450G 1504-150D 1504-50D 1504-120F 1504-320F 1504-480F 1504-90E 1504-380G 1504-45a 1504-220G 1504-1000G 1504-100a 1504-100B 1504-100C 1504-100D 1504-100G 1504-10B 1504-120B 1504-120C 1504-120E 1504-125D 1504-140C 1504-150B 1504-150G 1504-150E 1504-30E 1504-225D 1504-30B 1504-750G 1504-180E 1504-400C 1504-400G 1504-40a 1504-40B 1504-40C 1504-40F 1504-800F 1504-500D 1504-500G 1504-300C 1504-300D 1504-300G 1504-60C 1504-60E 1504-60B 1504-60a 1504-200B 1504-200D 1504-200F 1504-20a 1504-20B 1504-20C 1504-240C 1504-240E 1504-80F 1504-600E 1504-50B 1504-50G
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| Description |
FIXED DIP DELaY line TD/TR = 5
Delay 20 /-1.0 ns, Fixed dip delay line Td/Tr=5
Delay 60 /-3 ns, Fixed dip delay line Td/Tr=5
Delay 800 /-40 ns, Fixed dip delay line Td/Tr=5
Delay 40 /-2 ns, Fixed dip delay line Td/Tr=5
Delay 400 /-20 ns, Fixed dip delay line Td/Tr=5
Delay 750 /-37.5 ns, Fixed dip delay line Td/Tr=5
Delay 225 /-12 ns, Fixed dip delay line Td/Tr=5
Delay 140 /-7 ns, Fixed dip delay line Td/Tr=5
Delay 100 /-5 ns, Fixed dip delay line Td/Tr=5
Delay 220 /-11 ns, Fixed dip delay line Td/Tr=5
Delay 380 /-19 ns, Fixed dip delay line Td/Tr=5
Delay 480 /-24 ns, Fixed dip delay line Td/Tr=5
Delay 120 /-6 ns, Fixed dip delay line Td/Tr=5
Delay 150 /-7.5 ns, Fixed dip delay line Td/Tr=5
Delay 450 /-22.5 ns, Fixed dip delay line Td/Tr=5
Delay 75 /-3.8 ns, Fixed dip delay line Td/Tr=5
Delay 360 /-18 ns, Fixed dip delay line Td/Tr=5
Delay 25 /-1.3 ns, Fixed dip delay line Td/Tr=5
Delay 250 /-12.5 ns, Fixed dip delay line Td/Tr=5
Fixed passive DIP delay line
PaSSIVE DELaY line, TRUE OUTPUT, DIP16
Delay 160 /-8 ns, Fixed dip delay line Td/Tr=5
Delay 375 /-18.8 ns, Fixed dip delay line Td/Tr=5
Delay 50 /-2.5 ns, Fixed dip delay line Td/Tr=5
Delay 320 /-16 ns, Fixed dip delay line Td/Tr=5
Delay 90 /-4.5 ns, Fixed dip delay line Td/Tr=5
Delay 45 /-2.3 ns, Fixed dip delay line Td/Tr=5
Delay 1000 /-50 ns, Fixed dip delay line Td/Tr=5
Delay 10 /-1 ns, Fixed dip delay line Td/Tr=5
Delay 125 /-6.3 ns, Fixed dip delay line Td/Tr=5
Delay 30 /-1.5 ns, Fixed dip delay line Td/Tr=5
Delay 180 /-9 ns, Fixed dip delay line Td/Tr=5
Delay 500 /-25 ns, Fixed dip delay line Td/Tr=5
Delay 300 /-15 ns, Fixed dip delay line Td/Tr=5
Delay 200 /-10 ns, Fixed dip delay line Td/Tr=5
Delay 240 /-12 ns, Fixed dip delay line Td/Tr=5
Delay 80 /-4 ns, Fixed dip delay line Td/Tr=5
Delay 600 /-30 ns, Fixed dip delay line Td/Tr=5
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41.38K /
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Price and Availability
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