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pmc
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Part No. |
2000088
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OCR Text |
...mulation services, ranging from structured DS1/E1/J1 for carrying voice traffic, unstructured DS1/E1/J2 for private line consolidation to unstructured DS3/E3/J2/STS-1/STM0. The AAL1gator product family comprises five products: AAL1gator-I, ... |
Description |
From old datasheet system
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File Size |
184.71K /
19 Page |
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Zarlink
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Part No. |
MT90503 161
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OCR Text |
...ional VCs AAL1 cell format for "structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services Interoperability Specifications" (Nx64 Basic Service, DS1 Nx64 Service with CAS, and E1 Nx64 Service with CAS... |
Description |
2048VC AAL1 SAR From old datasheet system
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File Size |
1,521.61K /
232 Page |
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MAXIM - Dallas Semiconductor
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Part No. |
DS34S108DK-L7
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OCR Text |
...ip (aal1), hdlc, unstructured, structured, structured with cas ? adaptive clock recovery, common clock, external clock and loopback timing modes ? on - chip tdm clock recovery machines, one per port, independently configurable ... |
Description |
Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices
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File Size |
2,375.22K /
198 Page |
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Maxim Integrated Products Lattice Semiconductor Corporation Lattice Semiconductor, Corp.
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Part No. |
DS1004Z-3T LFSCM3GA15EP1-7F256C LFSCM3GA15EP1-7F900C LFSCM3GA25EP1-7F900C LFSCM3GA15EP1-7FN256C LFSCM3GA15EP1-7FN900C LFSCM3GA15EP1-7F256CES LFSCM3GA15EP1-7F900CES LFSCM3GA25EP1-7F900CES LFSCM3GA25EP1-7FF1020C LFSCM3GA40EP1-7FC1152C LFSCM3GA40EP1-7FF1020C LFSCM3GA40EP1-7FF1152C LFSCM3GA80EP1-7FC1152C LFSCM3GA80EP1-7FC1704C LFSCM3GA80EP1-7FF1152C LFSC3GA40E-6FFAN1020C LFSCM3GA80EP1-6FC1704I LFSCM3GA80EP1-5FC1152C LFSCM3GA40EP1-6FF1152C LFSCM3GA40EP1-5FFN1020C LFSCM3GA40EP1-5FFN1152I LFSC3GA25E-5FF1020C LFSC3GA25E-5FFN1020C LFSC3GA25E-5FFA1020C LFSC3GA25E-5FN900C LFSC3GA25E-5FFAN1020C
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OCR Text |
...tion (MACOTM) Blocks
* On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system level integration
High Performance System Bus
* Ties FPGA elements together with a standard bus framework - Connects to perip... |
Description |
FPGA, 56 CLBS, 15000 GATES, 1000 MHz, PBGA256 17 X 17 MM, LEAD FREE, FPBGA-256 FPGA, 56 CLBS, 15000 GATES, 1000 MHz, PBGA900 31 X 31 MM, LEAD FREE, FPBGA-900 FPGA, 104 CLBS, 25000 GATES, 1000 MHz, PBGA900 31 X 31 MM, FPBGA-900 FPGA, 56 CLBS, 15000 GATES, 1000 MHz, PBGA256 17 X 17 MM, FPBGA-256 FPGA, 216 CLBS, 40000 GATES, 1000 MHz, PBGA1020 33 X 33 MM, LEAD FREE, FCBGA-1020 FPGA, 308 CLBS, 80000 GATES, 1000 MHz, CBGA1704 42.5 X 42.5 MM, CERAMIC, FCBGA-1704 FPGA, 308 CLBS, 80000 GATES, 1000 MHz, PBGA1152 35 X 35 MM, FCBGA-1152 FPGA, 216 CLBS, 40000 GATES, 1000 MHz, PBGA1152 35 X 35 MM, FCBGA-1152 FPGA, 216 CLBS, 40000 GATES, 1000 MHz, PBGA1152 35 X 35 MM, LEAD FREE, FCBGA-1152 FPGA, 104 CLBS, 25000 GATES, 1000 MHz, PBGA1020
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File Size |
2,074.79K /
243 Page |
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Zarlink Semiconductor
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Part No. |
ZL50111
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OCR Text |
...) over the packet domain: * * * structured, synchronous CES unstructured, asynchronous CES, with integral per stream clock recovery complies with standards for native TDM circuit emulation proposed by the IETF's PWE3 working group
System... |
Description |
Telecomm/Datacomm, Other - Datasheet Reference
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File Size |
1,394.88K /
107 Page |
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Zarlink
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Part No. |
ZL50110ZL50111ZL50114
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OCR Text |
...) over the packet domain: * * * structured, synchronous CES unstructured, asynchronous CES, with integral per stream clock recovery complies with standards for native TDM circuit emulation proposed by the IETF's PWE3 working group
System... |
Description |
1024 Channel (32 T1/E1) Circuit Emulation Services over Packet Processor
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File Size |
1,358.81K /
107 Page |
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Price and Availability
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