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Infineon
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| Part No. |
V23814-K1306-M130 M130 V23814-K1306-MXXX V23815-K1306-MXXX
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| OCR Text |
... -0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2) .............................. 2.0 V Operating Case Temperature (TCASE)(3) ............... 0C to 80C Storage Ambient Temperature (TSTG )................ -20C to 100C Operating ... |
| Description |
1.25 Gbit/s Rx Receiver
1.25 Gbit/s Tx Transmitter
From old datasheet system
Parallel Optical Link: PAROLI Tx AC
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| File Size |
142.85K /
9 Page |
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it Online |
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Infineon
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| Part No. |
V23815-K1306-M230 V23814-K1306-M230 M230
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| OCR Text |
...er supply (3.3 V) * Low voltage differential signal electrical interface (LVDS) * 22 electrical data + 1 clock channels * Synchronous, DC-co...to 11 Gbit/s * Two clocking modes can be selected * Transmission distance depends on data rate and f... |
| Description |
Parallel Optical Link: PAROLI Rx DC/DEMUX-DEC
Parallel Optical Link: PAROLI Tx DC/MUX-ENC
From old datasheet system
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| File Size |
177.89K /
12 Page |
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it Online |
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XILINX
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| Part No. |
XC3S1500-4 XC3S200
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| OCR Text |
...le-ended signal standards - Six differential signal standards including LVDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to 3.45V - Double Data Rate (DDR) support Logic resources - Abundant, flexible lo... |
| Description |
Spartan-3 Field Programmable Gate Array
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| File Size |
1,420.09K /
159 Page |
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it Online |
Download Datasheet |
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Maxim
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| Part No. |
MAX19541
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| OCR Text |
....8V supply. The analog input is differential and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circ...to reduce the phase noise of the input clock source, allowing for higher dynamic performance. For be... |
| Description |
12-Bit, 125Msps ADC with CMOS Outputs for Wideband Applications
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| File Size |
266.72K /
23 Page |
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it Online |
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MICRON[Micron Technology]
Micron Technology, Inc.
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| Part No. |
MT46V8M16 MT46V32M4 MT46V16M8
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| OCR Text |
...data accesses per clock cycle * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Fo... |
| Description |
DOUBLE DATA RATE DDR SDRAM
DOUBLE DATA RATE DDR SDRAM 双倍数据速率的DDR SDRAM内存
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| File Size |
148.77K /
8 Page |
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it Online |
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Price and Availability
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