| |
|
 |
XILINX INC
|
| Part No. |
XCR3064A-10CP56C
|
| OCR Text |
...d as either a d- or t-type flip-flop or a combinatorial logic function. a d-type flip-flop is generally more useful for implementing state machines and data buffering while a t-type flip-flop is generally more useful in implementing counter... |
| Description |
EE PLD, 10 ns, PBGA56
|
| File Size |
158.77K /
17 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
QUICKLOGIC CORP
|
| Part No. |
QL6325-E-6PQ208M QL6325-E-6PQ208C
|
| OCR Text |
...e synchronous input of the flip-flop must be stable before the active clock edge 0.22 ns - t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t co clock-to-out delay: the amount o... |
| Description |
FPGA, 1536 CLBS, 320640 GATES, PQFP208
|
| File Size |
306.20K /
36 Page |
View
it Online |
Download Datasheet |
| |
|
|
XILINX INC
|
| Part No. |
XCV100-4HQ240C XCV100-4HQG240C XILINXINC-XCV600-4PQ240C XCV200-6HQ240C
|
| OCR Text |
...ck enable signals for each flip-flop. in addition to the clk and ce control signals, the three flip-flops share a set/reset (sr). for each flip-flop, this sig- nal can be independently configured as a synchronous set, a synchronous reset, ... |
| Description |
FPGA, 600 CLBS, 108904 GATES, 250 MHz, PQFP240
FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240
|
| File Size |
437.02K /
71 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
