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				FAIRCHILD[Fairchild Semiconductor]
Part No.	74ACTQ563 74ACTQ563PC
OCR Text	...= - 50 A Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined as (n). Data inputs...
Description	Quiet Series⑩ Octal Latch with 3-STATE Outputs Quiet Series Octal Latch with 3-STATE Outputs From old datasheet system
File Size	56.92K / 7 Page	View it Online	Download Datasheet

				Fairchild Semiconductor
Part No.	74ACTQ573PC 74ACTQ573QSC 74ACTQ573SC 74ACTQ573SJ 74ACQ573 74ACQ573MTC 74ACQ573PC 74ACQ573SC 74ACQ573SJ 74ACQ573CW 74ACTQ573CW
OCR Text	...nditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the resp...
Description	Quiet Series Octal Latch with 3-STATE Outputs
File Size	122.77K / 12 Page	View it Online	Download Datasheet

				Fairchild Semiconductor Corporation FAIRCHILD[Fairchild Semiconductor]
Part No.	74ACTQ574PC 74ACQ574 74ACQ574PC 74ACQ574SC 74ACQ574SJ 74ACTQ574SJ 74ACTQ574SC 74ACQ574CW 74ACTQ574CW
OCR Text	...nditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the resp...
Description	Quiet Series Octal D Flip-Flop with 3-STATE Outputs Quiet SeriesOctal D-Type Flip-Flop with 3-STATE Outputs 18-Bit LVTTL-to-GTLP Bus Transceiver with Source Synchronous Clock Outputs 56-TSSOP -40 to 85 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs Quiet Series⑩ Octal D-Type Flip-Flop with 3-STATE Outputs From old datasheet system
File Size	96.78K / 10 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	74AHC595 74AHC595D 74AHC595PW 74AHCT595PW 74AHCT595 74AHCT595D
OCR Text	... registers empty shift register loaded into storage register shift register clear. Parallel outputs in high impedance OFF-state. logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e....
Description	8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
File Size	103.14K / 20 Page	View it Online	Download Datasheet

				Fairchild Semiconductor, Corp. FAIRCHILD[Fairchild Semiconductor]
Part No.	74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ
OCR Text	...Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR ('F161A) or SR (74F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits c...
Description	Synchronous Presettable Binary Counter F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
File Size	70.56K / 7 Page	View it Online	Download Datasheet

				NXP Semiconductors http:// PHILIPS[Philips Semiconductors]
Part No.	74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN
OCR Text	... data at the D0-D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs. ...
Description	4-bit binary counter
File Size	111.89K / 14 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74HC40104 74HCT40104
OCR Text	...e (S0 and S1 are HIGH), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished...
Description	4-bit bidirectional universal shift register; 3-state
File Size	58.35K / 8 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74HCT40105U 74HC40105U
OCR Text	...3 Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the falling edge of...
Description	4-bit x 16-word FIFO register
File Size	199.99K / 25 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V. PHILIPS[Philips Semiconductors]
Part No.	74HCT4510 74HC4510 74HC4510PW 74HC4510D 74HC4510DB 74HC4510N 74HCT4510D 74HCT4510DB 74HCT4510N 74HCT4510PW
OCR Text	...MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. U...
Description	Quadruple D-Type Flip-Flops With Clear 16-TSSOP -40 to 85 BCD up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16 BCD up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16 BCD up/down counter BCD码向向下计数
File Size	97.72K / 12 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V. PHILIPS[Philips Semiconductors]
Part No.	74HCT4516 74HC4516 74HC4516N 74HC4516D 74HC4516DB 74HCT4516D 74HCT4516DB 74HCT4516N
OCR Text	...MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. When PL and CE are LOW, the counter changes on the LOW-to-HIGH transition of CP. UP/...
Description	Binary up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16
File Size	95.51K / 14 Page	View it Online	Download Datasheet

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