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lvpecl-to-pecl Datasheet PDF File

For lvpecl-to-pecl Found Datasheets File :: 2009 Search Time::2.234ms
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				ICS
Part No.	ICS843001-22
OCR Text	LVPECL FREQUENCY SYNTHESIZER FEATURES * One 3.3V LVPECL output pair and one LVCMOS output * Selectable crystal oscillator interface or LVC...to 70C ambient operating temperature GENERAL DESCRIPTION The ICS843001-22 is a a highly versatil...
Description	FemtoClocks? Crystal to LVPECL Frequency Synthesizer
File Size	170.87K / 11 Page	View it Online	Download Datasheet

				ICS
Part No.	ICS843001I-22
OCR Text	LVPECL FREQUENCY SYNTHESIZER FEATURES * One 3.3V or 2.5V LVPECL output pair and one LVCMOS/LVTTL output * Selectable crystal oscillator in...to 85C ambient operating temperature * Lead-Free package fully RoHS compliant GENERAL DESCRIPTION...
Description	FemtoClocks? Crystal/LVCMOS to 3.3V, 2.5V LVPECL Frequency Synthesizer
File Size	192.12K / 14 Page	View it Online	Download Datasheet

				Maxim
Part No.	MAX9424EVKIT
OCR Text	...24, a four-channel lowskew PECL/LVPECL-to-ECL/LVECL translator. The EV kit accepts differential PECL/LVPECL input signals and converts these differential ECL/LVECL signals at an operating frequency up to 3GHz. The MAX9424 EV kit is a four-l...
Description	Evaluation Kit for the MAX9424/ MAX9425/MAX9426/MAX9427
File Size	421.76K / 6 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	PCK9448 PCK9448BD
OCR Text	...port of LVCMOS and differential LVPECL clock distribution systems. The PCK9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic LOW state, thus e...
Description	3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
File Size	96.78K / 20 Page	View it Online	Download Datasheet

				Electronic Theatre Controls, Inc. ETC ICST[Integrated Circuit Systems]
Part No.	M1010 M1010-01 M1010-01I156.2500 M1010-01-155.5200 M1010-01-156.2500 M1010-01I155.5200
OCR Text	... rms, typical (12kHz to 20MHz) LVPECL clock output Pin-selectable feedback and reference divider ratios, no programming required Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance Reference clock ...
Description	Frequency Translation PLL Family for VXCO Replacement with Hitless Switching options VCSO BASED CLOCK JITTER ATTENUATOR
File Size	268.04K / 8 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	MC100EP196 MC100EP196FA MC100EP196FAR2
OCR Text	...ge LVCMOS YES N/A LVTTL YES N/A LVPECL YES N/A LVNECL N/A YES http://onsemi.com 4 FTUNE IN IN EN 512 GD* 0 1 256 GD* 0 1 128...to 34 UL 94 V-0 @ 0.125 in 1237 Devices Moisture Sensitivity (Note 1) Flammability Rating Transis...
Description	3.3V ECL Programmable Delay Chip with FTUNE
File Size	146.28K / 20 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	MC100EPT23DTG MC100EPT23DTR2G MC100EPT23 MC100EPT23D MC100EPT23DG MC100EPT23DR2 MC100EPT23DR2G MC100EPT23DT MC100EPT23DTR2
OCR Text	LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dua...
Description	Dual Differential LVPECL to LVTTL Translator
File Size	65.13K / 8 Page	View it Online	Download Datasheet

				Freescale (Motorola) FREESCALE[Freescale Semiconductor, Inc] Freescale Semiconductors 飞思卡尔半导体(中国)有限公司
Part No.	MC100ES6039 MC100ES6039EGR2 MC100ES6039DW MC100ES6039DWR2 MC100ES6039EG
OCR Text	...sitive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the d...to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random ...
Description	3.3 V ECL/PECL/HSTL/LVDS /-2/4, /-4/5/6 Clock Generation Chip 3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip 3.3 ECL / PECL HSTL / LVDS / 44 / 6时钟发生器芯
File Size	228.41K / 8 Page	View it Online	Download Datasheet

				Motorola
Part No.	MC100ES6221
OCR Text	...tandards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP (DC) is the minimum differential input ...
Description	Low Voltage 1:20 Dlfferentlal ECL/PECL HSTL Clock Fanout Buffer
File Size	111.77K / 12 Page	View it Online	Download Datasheet

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