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For mid-power Found Datasheets File :: 6302 Search Time::2.359ms
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				WOLFSON[Wolfson Microelectronics plc]
Part No.	WM8721 XWM8721EDS
OCR Text	...utput Analogue VDD Analogue GND Mid-rail reference decoupling point Control Interface Selection, Pull up (on power up only) 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (on power up only) 3-Wire MPU Da...
Description	Internet Audio DAC with Integrated Headphone Driver
File Size	338.30K / 34 Page	View it Online	Download Datasheet

				WOLFSON[Wolfson Microelectronics plc]
Part No.	WM8729 XWM8729ED
OCR Text	... Supply Left Channel DAC Output Mid Rail Decoupling Point DAC Negative Reference - normally AGND, must not be below AGND DAC Positive Refere...Power On Reset (POR) POR threshold 100 (VREFP VREFN)/2 2.4 pF V V Notes: 1. Ratio of out...
Description	24-bit/ 192kHz Stereo DAC 24-bit, 192kHz Stereo DAC
File Size	162.08K / 15 Page	View it Online	Download Datasheet

				Wolfson ETC[ETC]
Part No.	WM8734 WM8734EDS
OCR Text	...utput Analogue VDD Analogue GND Mid-rail reference decoupling point Right Channel Line Input (AC coupled) Left Channel Line Input (AC couple...Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off Hysteresis DCVDD Threshold Off -> On Anal...
Description	STEREO AUDIO CODEC
File Size	404.65K / 42 Page	View it Online	Download Datasheet

				WOLFSON[Wolfson Microelectronics plc]
Part No.	WM8739 WM8739EDS WM8739LEDS
OCR Text	...ction Analogue VDD Analogue GND Mid-rail reference decoupling point Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull up (on power up only) 3-Wire MPU Chip Select/ 2-Wire MPU interf...
Description	STEREO AUDIO ADC
File Size	346.96K / 35 Page	View it Online	Download Datasheet

				WOLFSON[Wolfson Microelectronics plc]
Part No.	WM8746 WM8746EDS
OCR Text	...DAC Reference Analogue Internal Mid-Rail Reference De-Coupling Point Left Channel 2 Output. Channel 2 Negative Reference. Right Channel 2 Ou...Power down, stop clock Power down, stop clock SYMBOL DVDD AVDD1, AVDD2 AGND, GR, DGND -0.3 TEST COND...
Description	24BIT 192KHZ 6 CHANNEL DAC WITH VOLUME CONTROL
File Size	254.42K / 31 Page	View it Online	Download Datasheet

				WOLFSON[Wolfson Microelectronics plc]
Part No.	WM8756 WM8756EFT
OCR Text	...al connection Analogue Internal Mid-Rail Reference De-Coupling Point No internal connection Left Channel 2 Output. Channel 2 Negative Refere...Power down, stop clock Power down, stop clock SYMBOL DVDD AVDD AGND, DGND -0.3 -0.3 TEST CONDITIONS ...
Description	192KHZ SIX CHANNEL SACD COMPATIBLE AUDIO DAC
File Size	320.28K / 39 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY2V995 CY2V995AC CY2V995ACT CY2V995AI CY2V995AIT
OCR Text	...ock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal ope...Power-down and reference divider control. When LOW, shuts off entire chip. Please see Table 2 for se...
Description	S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
File Size	279.15K / 10 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC Integrated Device Technology, Inc. IDT[Integrated Device Technology]
Part No.	IDT5V2528 IDT5V2528A IDT5V2528APG IDT5V2528APGG IDT5V2528APGGI IDT5V2528APGI IDT5V2528PG IDT5V2528PGG IDT5V2528PGGI IDT5V2528PGI IDT5V2528APGGI8 IDT5V2528PGGI8 IDT5V2528APGI8
OCR Text	...gnals may be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. ...power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any c...
Description	2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER 2.5V / 3.3V的锁相环时钟驱动器零延迟缓冲 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER .5V / 3.3V的锁相环时钟驱动器零延迟缓冲
File Size	59.21K / 7 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT5V9950 IDT5V9950PFI
OCR Text	... hard-wired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is ...Power 24 23 22 21 20 19 18 17 1F1 1F0 sOE VDDQ 1Q0 1Q1 GND GND Max -0.5 to +4.6 -0.5 to VDD+0.5 ...
Description	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK? II JR.
File Size	65.38K / 9 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT5V9955 IDT5V9955BFI IDT5V9955BFI8
OCR Text	... hard-wired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:...Power Dissipation TSTG TA = 85C TA = 55C Max -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to +5.5 1.1 1.9 -65 t...
Description	3.3V Programmable Skew Dual PLL Clock Driver Turboclock II 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
File Size	124.58K / 11 Page	View it Online	Download Datasheet

For mid-power Found Datasheets File :: 6302 Search Time::2.359ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | <13> | 14 | 15 |