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    ST Microelectronics, Inc.
Part No. M5or='#FF0000'>8LR12or='#FF0000'>8GU
Description The M5or='#FF0000'>8LR12or='#FF0000'>8GU/L and M5or='#FF0000'>8LR256GU/L are 12or='#FF0000'>8 or='#FF0000'>mbit (or='#FF0000'>8 or='#FF0000'>mbit x16) and 256 or='#FF0000'>mbit (16 or='#FF0000'>mbit
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    Renesas Electronics Corporation.
Renesas Electronics, Corp.
Part No. M3or='#FF0000'>8030F2Lor='#FF0000'>-xxxHP M3or='#FF0000'>8030F2Lor='#FF0000'>-xxxKP M3or='#FF0000'>8030F2Lor='#FF0000'>-xxxSP M3or='#FF0000'>8030F2Lor='#FF0000'>-xxxWG M3or='#FF0000'>8030MALor='#FF0000'>-xxxWG M3or='#FF0000'>8030MALor='#FF0000'>-xxxKP M3or='#FF0000'>8030FALor='#FF0000'>-xxxSP M3or='#FF0000'>8031FALor='#FF0000'>-xxxHP M3or='#FF0000'>8030FALor='#FF0000'>-xxxWG M3or='#FF0000'>8030MALor='#FF0000'>-xxxHP M3or='#FF0000'>8030FALor='#FF0000'>-xxxKP M3or='#FF0000'>8031FALor='#FF0000'>-xxxKP M3or='#FF0000'>8030FALor='#FF0000'>-xxxHP M3or='#FF0000'>8031FALor='#FF0000'>-xxxSP M3or='#FF0000'>8031FALor='#FF0000'>-xxxWG M3or='#FF0000'>8030MALor='#FF0000'>-xxxSP M3or='#FF0000'>8030F3Lor='#FF0000'>-xxxHP M3or='#FF0000'>8030F3Lor='#FF0000'>-xxxWG M3or='#FF0000'>8030M3Lor='#FF0000'>-xxxKP M3or='#FF0000'>8030F3Lor='#FF0000'>-xxxSP M3or='#FF0000'>8030F3Lor='#FF0000'>-xxxKP M3or='#FF0000'>8030M3Lor='#FF0000'>-xxxHP M3or='#FF0000'>8030FBLor='#FF0000'>-xxxWG M3or='#FF0000'>8030MBLor='#FF0000'>-xxxHP M3or='#FF0000'>8030FBLor='#FF0000'>-xxxHP M3or='#FF0000'>8030FBLor='#FF0000'>-xxxSP M3or='#FF0000'>8030MBLor='#FF0000'>-xxxKP M3or='#FF0000'>8030M2Lor='#FF0000'>-xxxHP M3or='#FF0000'>8030M2Lor='#FF0000'>-xxxKP M3or='#FF0000'>8030M2Lor='#FF0000'>-xxxSP M3or='#FF0000'>8030M2Lor='#FF0000'>-xxxWG M3or='#FF0000'>8031F2Lor='#FF0000'>-xxxHP M3or='#FF0000'>8031F2Lor='#FF0000'>-xxxKP M3or='#FF0000'>8031F2Lor='#FF0000'>-xxxSP M3or='#FF0000'>8031F2Lor='#FF0000'>-xxxWG M3or='#FF0000'>8030FBor='#FF0000'>-xxxHP M3or='#FF0000'>8031FBLor='#FF0000'>-xxxSP M3or='#FF0000'>8035MBLor='#FF0000'>-xxxSP M3or='#FF0000'>803or='#FF0000'>8FBLor='#FF0000'>-xxxSP M3or='#FF0000'>8039FBLor='#FF0000'>-xxxSP M3or='#FF0000'>8030MBLor='#FF0000'>-xxxSP M3or='#FF0000'>8036MBLor='#FF0000'>-xxxSP M3or='#FF0000'>8037FBLor='#FF0000'>-xxxSP M3or='#FF0000'>8037MBLor='#FF0000'>-xxxSP M3or='#FF0000'>8036FBLor='#FF0000'>-xxxSP M3or='#FF0000'>803or='#FF0000'>8MBLor='#FF0000'>-xxxSP M3or='#FF0000'>8031FCor='#FF0000'>-xxxHP M3or='#FF0000'>8031FCor='#FF0000'>-xxxKP M3or='#FF0000'>8031FCor='#FF0000'>-xxxWG M3or='#FF0000'>8031FCLor='#FF0000'>-xxxHP M3or='#FF0000'>8031FCLor='#FF0000'>-xxxKP M3or='#FF0000'>8031FCLor='#FF0000'>-xxxSP M3or='#FF0000'>8031FCLor='#FF0000'>-xxxWG M3or='#FF0000'>8031F5or='#FF0000'>-xxxKP M3or='#FF0000'>8031F5or='#FF0000'>-xxxSP M3or='#FF0000'>8031F5or='#FF0000'>-xxxWG M3or='#FF0000'>8031F5Lor='#FF0000'>-xxxHP M3or='#FF0000'>8031F5Lor='#FF0000'>-xxxKP M3or='#FF0000'>8031F5Lor='#FF0000'>-xxxSP M3or='#FF0000'>8031F5Lor='#FF0000'>-xxxWG M3or='#FF0000'>8030F1or='#FF0000'>-xxxHP M3or='#FF0000'>8030F1or='#FF0000'>-xxxKP M3or='#FF0000'>8030F1or='#FF0000'>-xxxSP M3or='#FF0000'>8030F1or='#FF0000'>-xxxWG M3or='#FF0000'>8030F1Lor='#FF0000'>-xxxHP M3or='#FF0000'>8030F1Lor='#FF0000'>-xxxKP M3or='#FF0000'>8030F1Lor='#FF0000'>-xxxSP M3or='#FF0000'>8030F1Lor='#FF0000'>-xxxWG M3or='#FF0000'>8031F1or='#FF0000'>-xxxKP M3or='#FF0000'>8031F1or='#FF0000'>-xxxWG M3or='#FF0000'>8031F1Lor='#FF0000'>-xxxHP M3or='#FF0000'>8031F1Lor='#FF0000'>-xxxKP M3or='#FF0000'>8031F6or='#FF0000'>-xxxHP M3or='#FF0000'>8031F6or='#FF0000'>-xxxKP M3or='#FF0000'>8031F6or='#FF0000'>-xxxSP M3or='#FF0000'>8031F6or='#FF0000'>-xxxWG M
Description 256 Kbit (32K x or='#FF0000'>8) nvSRAM; organization: 32Kb x or='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x or='#FF0000'>8) Static RAM; Density: 256 Kb; organization: 32Kb x or='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;
Threeor='#FF0000'>-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) Static RAM; Density: or='#FF0000'>8 Mb; organization: 512kb x 16; Vcc (V): 2.20 to 3.60 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 512kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Flowor='#FF0000'>-Through SRAM; Architecture: Standard Sync, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 512kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM 4or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, 4 Word Burst; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCIor='#FF0000'>-x and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, 2 Word Burst; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 512kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 512kb x 1or='#FF0000'>8; Vcc (V): 2.4 to 2.6 V
4or='#FF0000'>-or='#FF0000'>mbit (512K x or='#FF0000'>8) Static RAM; Density: 4 Mb; organization: 512kb x or='#FF0000'>8; Vcc (V): 4.50 to 5.50 V;
4or='#FF0000'>-or='#FF0000'>mbit (256K x 16) Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V;
64K x 16 Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
1or='#FF0000'>-or='#FF0000'>mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
1or='#FF0000'>-or='#FF0000'>mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
4 or='#FF0000'>mbit (512K x or='#FF0000'>8/256K x 16) nvSRAM; organization: 512kb x or='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
4 or='#FF0000'>mbit (512K x or='#FF0000'>8/256K x 16) nvSRAM; organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
16or='#FF0000'>-or='#FF0000'>mbit (1M x 16 / 2M x or='#FF0000'>8) Static RAM; Density: 16 Mb; organization: or='#FF0000'>1mb x 16; Vcc (V): 4.50 to 5.50 V;
4K x 16/1or='#FF0000'>8 and or='#FF0000'>8K x 16/1or='#FF0000'>8 Dualor='#FF0000'>-Port Static RAM with SEM, INT, BUSY; Density: 12or='#FF0000'>8 Kb; organization: or='#FF0000'>8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 512kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) Static RAM; Density: or='#FF0000'>8 Mb; organization: 512kb x 16; Vcc (V): 4.50 to 5.50 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Flowor='#FF0000'>-Through SRAM; Architecture: Standard Sync, Flowor='#FF0000'>-through; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V;
9or='#FF0000'>-or='#FF0000'>mbit (256K x 36/512K x 1or='#FF0000'>8) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
4or='#FF0000'>-or='#FF0000'>mbit (256K x 16) Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (1024K x or='#FF0000'>8) Static RAM; Density: or='#FF0000'>8 Mb; organization: or='#FF0000'>1mb x or='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (1M x or='#FF0000'>8) Static RAM; Density: or='#FF0000'>8 Mb; organization: or='#FF0000'>1mb x or='#FF0000'>8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: or='#FF0000'>8; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to or='#FF0000'>80 MHz; Outputs: or='#FF0000'>8; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 1or='#FF0000'>8) Flowor='#FF0000'>-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flowor='#FF0000'>-through; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1or='#FF0000'>8 Mb; organization: or='#FF0000'>1mb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
512K x or='#FF0000'>8 Static RAM; Density: 4 Mb; organization: 512kb x or='#FF0000'>8; Vcc (V): 4.5 to 5.5 V;
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 36/1M x 1or='#FF0000'>8) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 2.4 to 2.6 V
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C
2M x or='#FF0000'>8 Static RAM; Density: 16 Mb; organization: 2Mb x or='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;
16 or='#FF0000'>mbit (512K x 32) Static RAM; Density: 16 Mb; organization: 512kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (1M x or='#FF0000'>8) Static RAM; Density: or='#FF0000'>8 Mb; organization: or='#FF0000'>1mb x or='#FF0000'>8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 16) Static RAM; Density: 2 Mb; organization: 12or='#FF0000'>8Kb x 16; Vcc (V): 3.0 to 3.6 V;
16or='#FF0000'>-or='#FF0000'>mbit (1M x 16) Static RAM; Density: 16 Mb; organization: or='#FF0000'>1mb x 16; Vcc (V): 3.0 to 3.6 V;
4or='#FF0000'>-or='#FF0000'>mbit (256K x 1or='#FF0000'>8) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; organization: 256Kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RAM; Density: 512 Kb; organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
4or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 36) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; organization: 12or='#FF0000'>8Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RAM; Density: 16 Mb; organization: or='#FF0000'>1mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to or='#FF0000'>80 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBL(R) 2 or='#FF0000'>mbit (12or='#FF0000'>8K x 16) Static RAM; Density: 2 Mb; organization: 12or='#FF0000'>8Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) xDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to or='#FF0000'>800 MHz; # Out: 4
2or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 16) Static RAM; Density: 2 Mb; organization: 12or='#FF0000'>8Kb x 16; Vcc (V): 2.20 to 3.60 V;
4or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: 12or='#FF0000'>8Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 12or='#FF0000'>8; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 12or='#FF0000'>8; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 12or='#FF0000'>8; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit DDRor='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: DDRor='#FF0000'>-II CIO, 2 Word Burst; Density: 1or='#FF0000'>8 Mb; organization: 512kb x 36; Vcc (V): 1.7 to 1.9 V
Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to or='#FF0000'>80 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to or='#FF0000'>80 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机
SINGLEor='#FF0000'>-CHIP or='#FF0000'>8or='#FF0000'>-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 12or='#FF0000'>8; Vcc (V): 3.3; fMax (MHz): or='#FF0000'>83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Threeor='#FF0000'>-PLL Generalor='#FF0000'>-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (512K x 16) MoBL(R) Static RAM; Density: or='#FF0000'>8 Mb; organization: 512kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer for Mobile PCs with 4 SOor='#FF0000'>-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to or='#FF0000'>80 MHz; Outputs: or='#FF0000'>8; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 16) Static RAM; Density: 2 Mb; organization: 12or='#FF0000'>8Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBL(R) 1 or='#FF0000'>mbit (12or='#FF0000'>8K x or='#FF0000'>8) Static RAM; Density: 1 Mb; organization: 12or='#FF0000'>8Kb x or='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
1or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit QDR(TM)or='#FF0000'>-II SRAM 2or='#FF0000'>-Word Burst Architecture; Architecture: QDRor='#FF0000'>-II, 2 Word Burst; Density: 1or='#FF0000'>8 Mb; organization: or='#FF0000'>1mb x 1or='#FF0000'>8; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x or='#FF0000'>8) Static RAM; Density: 1 Mb; organization: 12or='#FF0000'>8Kb x or='#FF0000'>8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机
4or='#FF0000'>-or='#FF0000'>mbit (256K x 1or='#FF0000'>8) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: 256Kb x 1or='#FF0000'>8; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (64K x 32) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200or='#FF0000'>-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (12or='#FF0000'>8K x 16) Static RAM; Density: 2 Mb; organization: 12or='#FF0000'>8Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGLEor='#FF0000'>-CHIP or='#FF0000'>8or='#FF0000'>-BIT CMOS MICROCOMPUTER 单芯or='#FF0000'>8位CMOS微机
2or='#FF0000'>-or='#FF0000'>mbit (256K x or='#FF0000'>8) Static RAM; Density: 2 Mb; organization: 256Kb x or='#FF0000'>8; Vcc (V): 2.20 to 3.60 V; 单芯or='#FF0000'>8位CMOS微机
Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
Threeor='#FF0000'>-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:or='#FF0000'>8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: or='#FF0000'>8; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
Quad PLL Clock Generator with 2or='#FF0000'>-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multior='#FF0000'>-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:1or='#FF0000'>8 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 1or='#FF0000'>8; Operating Range: or='#FF0000'>-40 to or='#FF0000'>85 C 单芯位CMOS微机
or='#FF0000'>-bit AVR Microcontroller with or='#FF0000'>8K Bytes Inor='#FF0000'>- System Programmable Flash 位AVR微控制器具有or='#FF0000'>8K字节的系统内可编程闪
2.5V or 3.3V, 200or='#FF0000'>-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:or='#FF0000'>8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 32 MHz; Output Frequency Range: 4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: or='#FF0000'>8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) Highor='#FF0000'>-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
File Size 1,602.57K  /  119 Page

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    Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTor CorP
Part No. CY14B104NAor='#FF0000'>-ZSP20xCT CY14B104NAor='#FF0000'>-ZSP20xIT CY14B104LAor='#FF0000'>-BA25xC CY14B104NAor='#FF0000'>-BA20xC
Description 4 or='#FF0000'>mbit (512K x or='#FF0000'>8/256K x 16) nvSRAM; organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 256K x 16 NONor='#FF0000'>-VOLATILE SRAM, 20 ns, PDSO54
4 or='#FF0000'>mbit (512K x or='#FF0000'>8/256K x 16) nvSRAM; organization: 512kb x or='#FF0000'>8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
4 or='#FF0000'>mbit (512K x or='#FF0000'>8/256K x 16) nvSRAM; organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
File Size 613.78K  /  23 Page

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    Silicon Storage Technology Inc
Silicon Storage Technology, Inc.
SILICON STorAGE TECHNOLOGY INC
Part No. 49LF002 SST49LF003Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-NH SST49LF003Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-WH SST49LF002Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-WH SST49LF002Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-NH SST49LF004Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-NH SST49LF004Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-WH SST49LF00or='#FF0000'>8Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-WH SST49LF00or='#FF0000'>8Aor='#FF0000'>-33or='#FF0000'>-4Cor='#FF0000'>-NH
Description MB 6C 6#20 SKT PLUG
2 or='#FF0000'>mbit / 3 or='#FF0000'>mbit / 4 or='#FF0000'>mbit / or='#FF0000'>8 or='#FF0000'>mbit Firmware Hub 3or='#FF0000'>84K x or='#FF0000'>8 FLASH 3V PROM, 11 ns, PQCC32
2 or='#FF0000'>mbit / 3 or='#FF0000'>mbit / 4 or='#FF0000'>mbit / or='#FF0000'>8 or='#FF0000'>mbit Firmware Hub 256K x or='#FF0000'>8 FLASH 3V PROM, 11 ns, PQCC32
2 or='#FF0000'>mbit / 3 or='#FF0000'>mbit / 4 or='#FF0000'>mbit / or='#FF0000'>8 or='#FF0000'>mbit Firmware Hub 512K x or='#FF0000'>8 FLASH 3V PROM, 11 ns, PQCC32
File Size 394.84K  /  36 Page

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    M36W0R6040B3ZAQE M36W0R6050B3 M36W0R6050B3ZAQE M36W0R6050B3ZAQF M36W0R6050T3 M36W0R6050T3ZAQE M36W0R6050T3ZAQF M36W0R604

Numonyx B.V
http://
Part No. M36W0R6040B3ZAQE M36W0R6050B3 M36W0R6050B3ZAQE M36W0R6050B3ZAQF M36W0R6050T3 M36W0R6050T3ZAQE M36W0R6050T3ZAQF M36W0R6040T3ZAQE M36W0R6040T3ZAQF M36W0R6040B3ZAQF
Description 64or='#FF0000'>-or='#FF0000'>mbit (4 or='#FF0000'>mbits ×16, multiple bank, burst) Flash memory and 16or='#FF0000'>-or='#FF0000'>mbit (1 or='#FF0000'>mbit ×16) or 32or='#FF0000'>-or='#FF0000'>mbit (2 or='#FF0000'>mbits x16) PSRAM MCP
File Size 435.20K  /  23 Page

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    Motorola, Inc.
Motorola Mobility Holdings, Inc.
Part No. MPC2104P MPC2105P
Description (MPC2104P / MPC2105P) 256KB/512kb BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
256KB/512kb BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms 256KB/512kb BurstRAM二级缓存模块为PowerPC制备/ CH旺平
File Size 162.22K  /  16 Page

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    M27C4001-35F1TR M27C4001-35F1X M27C4001-35F6TR M27C4001-35F6X M27C4001-55F1TR M27C4001-55F1X M27C4001-55F6TR M27C4001-55

ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
意法半导
STMicroelectronics N.V.
Part No. M27C4001or='#FF0000'>-35F1TR M27C4001or='#FF0000'>-35F1x M27C4001or='#FF0000'>-35F6TR M27C4001or='#FF0000'>-35F6x M27C4001or='#FF0000'>-55F1TR M27C4001or='#FF0000'>-55F1x M27C4001or='#FF0000'>-55F6TR M27C4001or='#FF0000'>-55F6x M27C4001or='#FF0000'>-12F M27C4001or='#FF0000'>-55B1TR M27C4001or='#FF0000'>-55B1x M27C4001or='#FF0000'>-55B6TR M27C4001or='#FF0000'>-55B6x M27C4001or='#FF0000'>-55C1TR M27C4001or='#FF0000'>-55C1x M27C4001or='#FF0000'>-55C6TR M27C4001or='#FF0000'>-55C6x M27C4001or='#FF0000'>-90xN6x 27C4001 M27C4001 M27C4001or='#FF0000'>-10B1 M27C4001or='#FF0000'>-10B1TR M27C4001or='#FF0000'>-10B1x M27C4001or='#FF0000'>-10B6TR M27C4001or='#FF0000'>-10B6x M27C4001or='#FF0000'>-10C1TR M27C4001or='#FF0000'>-10C1x M27C4001or='#FF0000'>-10C6TR M27C4001or='#FF0000'>-10C6x M27C4001or='#FF0000'>-10F1TR M27C4001or='#FF0000'>-10F1x M27C4001or='#FF0000'>-10F6TR M27C4001or='#FF0000'>-10F6x M27C4001or='#FF0000'>-10L1TR M27C4001or='#FF0000'>-10L1x M27C4001or='#FF0000'>-10L6TR M27C4001or='#FF0000'>-10L6x M27C4001or='#FF0000'>-10N1TR M27C4001or='#FF0000'>-10N1x M27C4001or='#FF0000'>-10N6TR M27C4001or='#FF0000'>-10N6x M27C4001or='#FF0000'>-10xB1TR M27C4001or='#FF0000'>-10xB1x M27C4001or='#FF0000'>-10xB6TR M27C4001or='#FF0000'>-10xB6x M27C4001or='#FF0000'>-10xC1TR M27C4001or='#FF0000'>-10xC1x M27C4001or='#FF0000'>-10xC6TR M27C4001or='#FF0000'>-10xC6x M27C4001or='#FF0000'>-10xF1TR M27C4001or='#FF0000'>-10xF1x M27C4001or='#FF0000'>-10xF6TR M27C4001or='#FF0000'>-10xF6x M27C4001or='#FF0000'>-10xL1TR M27C4001or='#FF0000'>-10xL1x M27C4001or='#FF0000'>-10xL6TR M27C4001or='#FF0000'>-10xL6x M27C4001or='#FF0000'>-10xN1TR M27C4001or='#FF0000'>-10xN1x M27C4001or='#FF0000'>-10xN6TR M27C4001or='#FF0000'>-10xN6x M27C4001or='#FF0000'>-12B1TR M27C4001or='#FF0000'>-12B1x M27C4001or='#FF0000'>-12B6TR M27C4001or='#FF0000'>-12B6x M27C4001or='#FF0000'>-12C1TR M27C4001or='#FF0000'>-12C1x M27C4001or='#FF0000'>-12C6TR M27C4001or='#FF0000'>-12C6x M27C4001or='#FF0000'>-12F1TR M27C4001or='#FF0000'>-12F1x M27C4001or='#FF0000'>-12F6TR M27C4001or='#FF0000'>-12F6x M27C4001or='#FF0000'>-12L1TR M27C4001or='#FF0000'>-12L1x M27C4001or='#FF0000'>-12L6TR M27C4001or='#FF0000'>-12L6x M27C
Description 4 or='#FF0000'>mbit (512kb xor='#FF0000'>8) UV EPROM AND OTP ROM
CAP 1000PF 50V 5% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR MARKED
CAP 0.01UF 25V 1% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 0.01UF 25V 10% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 1000PF 100V 10% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-13or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 1000PF 100V 5% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR MARKED
CAP 0.01UF 25V 20% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 12PF 100V 10% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 120PF 100V 5% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 1300PF 50V 5% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 1000PF 100V 10% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
CAP 12PF 50V 10% NP0(C0G) SMDor='#FF0000'>-1206 TRor='#FF0000'>-7or='#FF0000'>-PL SNor='#FF0000'>-NIBAR
LED Lamp; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
4 or='#FF0000'>mbit 512kb x or='#FF0000'>8 UV EPROM and OTP EPROM 4兆位× or='#FF0000'>8紫外12KB的存储器和OTP存储
SERVSWITCH USB COAx CPU CABLES, WITH AUDIO 20FT 4兆位× or='#FF0000'>8紫外12KB的存储器和OTP存储
File Size 157.32K  /  17 Page

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    M27V402 M27V402-120B1TR M27V402-120B4TR M27V402-120B5TR M27V402-120B6TR M27V402-120F1TR M27V402-120F4TR M27V402-120F5TR

STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
Part No. M27V402 M27V402or='#FF0000'>-120B1TR M27V402or='#FF0000'>-120B4TR M27V402or='#FF0000'>-120B5TR M27V402or='#FF0000'>-120B6TR M27V402or='#FF0000'>-120F1TR M27V402or='#FF0000'>-120F4TR M27V402or='#FF0000'>-120F5TR M27V402or='#FF0000'>-120F6TR M27V402or='#FF0000'>-120K1TR M27V402or='#FF0000'>-120K4TR M27V402or='#FF0000'>-120K5TR M27V402or='#FF0000'>-120K6TR M27V402or='#FF0000'>-120N1TR M27V402or='#FF0000'>-120N4TR M27V402or='#FF0000'>-120N5TR M27V402or='#FF0000'>-120N6TR M27V402or='#FF0000'>-150B1TR M27V402or='#FF0000'>-150B4TR M27V402or='#FF0000'>-150B5TR M27V402or='#FF0000'>-150B6TR M27V402or='#FF0000'>-150F1TR M27V402or='#FF0000'>-150F4TR M27V402or='#FF0000'>-150F5TR M27V402or='#FF0000'>-150F6TR M27V402or='#FF0000'>-150K1TR M27V402or='#FF0000'>-150K4TR M27V402or='#FF0000'>-150K5TR M27V402or='#FF0000'>-150K6TR M27V402or='#FF0000'>-150N1TR M27V402or='#FF0000'>-150N4TR M27V402or='#FF0000'>-150N5TR M27V402or='#FF0000'>-150N6TR M27V402or='#FF0000'>-200B1TR M27V402or='#FF0000'>-200B4TR M27V402or='#FF0000'>-200B5TR M27V402or='#FF0000'>-200B6TR M27V402or='#FF0000'>-200F1TR M27V402or='#FF0000'>-200F4TR M27V402or='#FF0000'>-200F5TR M27V402or='#FF0000'>-200F6TR M27V402or='#FF0000'>-200K1TR M27V402or='#FF0000'>-200K4TR M27V402or='#FF0000'>-200K5TR M27V402or='#FF0000'>-200K6TR M27V402or='#FF0000'>-200N1TR M27V402or='#FF0000'>-200N4TR M27V402or='#FF0000'>-200N5TR M27V402or='#FF0000'>-200N6TR 4375 M27V402or='#FF0000'>-1or='#FF0000'>80N6TR M27V401or='#FF0000'>-200N6TR or='#FF0000'>-M27V402or='#FF0000'>-200F6TR
Description 4 or='#FF0000'>mbit 256Kb x 16 Low Voltage UV EPROM and OTP EPROM 4兆位56Kb × 16低压紫外线存储器和OTP存储
Quadruple 2or='#FF0000'>-Input Positiveor='#FF0000'>-AND Gates 14or='#FF0000'>-SOIC 0 to 70
Quadruple 2or='#FF0000'>-Input Positiveor='#FF0000'>-AND Gates 14or='#FF0000'>-SO 0 to 70
Hex Inverters 14or='#FF0000'>-SO 0 to 70
Quadruple 2or='#FF0000'>-Input Positiveor='#FF0000'>-Nor Gates 14or='#FF0000'>-PDIP 0 to 70
Quadruple 2or='#FF0000'>-Input Positiveor='#FF0000'>-NAND Gates 14or='#FF0000'>-PDIP 0 to 70
Quadruple 2or='#FF0000'>-Input Positiveor='#FF0000'>-Nor Gates 14or='#FF0000'>-SOIC 0 to 70
Hex Inverters 14or='#FF0000'>-SOIC 0 to 70
Switch Mode Power Supply; Series:ZWS; Output Voltage:15VDC; Output Power Max:10W; Output Current:0.7A; Number of Outputs:1; Supply Voltage Max:265VAC; Supply Voltage Min:or='#FF0000'>85VAC
Switch Mode Power Supply; Output Power:100W; No. of Outputs:1; Output 1 VDC :12VDC; Output Current 1:or='#FF0000'>8.5A; Power Supply Mounting:Open Frame; Approval Bodies:UL, CSA, CE; External Depth:222mm; External Width:62mm RoHS Compliant: Yes
Switch Mode Power Supply; Series:ZWS; Output Voltage:12VDC; Output Power Max:10W; Output Current:0.or='#FF0000'>85A; Number of Outputs:1; Supply Voltage Max:265VAC; Supply Voltage Min:or='#FF0000'>85VAC
Hex Inverters 14or='#FF0000'>-PDIP 0 to 70
From old datasheet system
4 or='#FF0000'>mbit 512kb x or='#FF0000'>8 Low Voltage OTP EPROM
4 or='#FF0000'>mbit 512kb xor='#FF0000'>8 Low Voltage UV EPROM and OTP EPROM
File Size 99.69K  /  15 Page

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    M29DW127G M29DW127G70NF6E

Numonyx B.V
Part No. M29DW127G M29DW127G70NF6E
Description 12or='#FF0000'>8or='#FF0000'>-or='#FF0000'>mbit (or='#FF0000'>8 or='#FF0000'>mbit x16 or 16 or='#FF0000'>mbit xor='#FF0000'>8 , multiple bank, page, dual boot) 3 V supply flash memory
File Size 1,927.14K  /  95 Page

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    PMCor='#FF0000'>-Sierra, Inc.
Part No. PM39F020or='#FF0000'>-70JCE PM39F020or='#FF0000'>-55PCE PM39F020or='#FF0000'>-55JCE PM39F020or='#FF0000'>-55VCE PM39F010or='#FF0000'>-55PCE PM39F010or='#FF0000'>-55VCE PM39F010or='#FF0000'>-55JCE PM39F020or='#FF0000'>-70VC PM39F040or='#FF0000'>-70VCE PM39F020or='#FF0000'>-70VCE PM39F040or='#FF0000'>-55PCE PM39F010or='#FF0000'>-70PCE PM39F040or='#FF0000'>-70PCE PM39F040or='#FF0000'>-55JCE PMCor='#FF0000'>-SIERRAINC.or='#FF0000'>-PM39F020or='#FF0000'>-55VCE PMCor='#FF0000'>-SIERRAINC.or='#FF0000'>-PM39F020or='#FF0000'>-55JCE PM39F020or='#FF0000'>-70PC
Description 1 or='#FF0000'>mbit / 2 or='#FF0000'>mbit / 4 or='#FF0000'>mbit 5 Voltor='#FF0000'>-only CMOS Flash Memory 1兆位/ 2 4兆位5伏，只有闪存的CMOS
File Size 140.68K  /  23 Page

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