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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
IDT723634L12PF
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| OCR Text |
...directions. fifo data on port b can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of big- or little-endian configura...bus-matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 communication between each port may bypass t... |
| Description |
512 X 36 BI-DIRECTIONAL FIFO, 8 ns, PQFP128
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| File Size |
405.88K /
35 Page |
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Winbond Electronics
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| Part No. |
W78L52/P/F
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| OCR Text |
...consumption. the external clock can be stopped at any time and in any state without affecting the processor. features ? fully static design ...bus during accesses to external memory. p1.0 ? p1.7 port 1, bits 0 through 7. port 1 is a bidirectio... |
| Description |
W78C52D Wide Voltage Version
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| File Size |
174.31K /
18 Page |
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it Online |
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Renesas
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| Part No. |
M5M5V5636GP-20
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| OCR Text |
...ible. Therefore the M5M5V5636GP can replace the M5M5T5636GP.
APPLICATION
High-end networking products that require high bandwidth, such ...bus width WRITEs occur if all byte write enables are LOW. Byte "a" is DQa , DQPa pins; Byte "b" is D... |
| Description |
Memory>Fast SRAM>Network SRAM
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| File Size |
680.52K /
18 Page |
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it Online |
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MOTOROLA[Motorola, Inc]
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| Part No. |
MC6800 MC6800CL MC6800CP MC6800CS MC6800L MC6800P MC6800S MC68A00CL MC68A00CP MC68A00CS MC68A00L MC68A00P MC68A00S MC6828 MC68BOOP MC68BOOS MC68BOOL MC6844 MC6854 MC6808 MC6852 MC68B00 MC68622 MC6843 MCM6810 6800 MC6802 MC6821 MC6822 MC6829 MC6835 MC6839 MC6840 MC6845 MC6846 MC6847 MC6847Y MC68488 MC6850 MC6859
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| OCR Text |
...NSIDERATIONS from:
TJ, in `C can be obtained
TJ=TA+(PDo Where: TA = Ambient OJA=
(1)
`C
,.,\wy\ \ ~.::$,i~ ;F's~; .,$ `f:?ki,, ...Bus Enable Down Time During @l Up Time Data Bus Enable Rise and Fall Times
ns
--
m
M070R... |
| Description |
8-BIT MPUS, 8-BIT MCUS, 8-BIT PERIPHERALS
8-BIT MICROPROCESSING UNIT (MPU)
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| File Size |
3,992.33K /
32 Page |
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it Online |
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Cypress
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| Part No. |
CY28353OC-2
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| OCR Text |
...FBINC). The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT, CLKI... |
| Description |
Differential Clock Buffer/Driver
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| File Size |
207.44K /
10 Page |
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ST Microelectronics
STMicroelectronics N.V.
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| Part No. |
M48T86MH M48T86PC1 M48T86SH
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| OCR Text |
...od so that a valid system reset can be established. The block diagram in Figure 3 shows the pin connections and the major internal functions...Bus). The M48T86 provides a multiplexed bus in which address and data information share the same sig... |
| Description |
5V PC REAL TIME CLOCK 5V的电脑实时时
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| File Size |
166.29K /
23 Page |
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it Online |
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Price and Availability
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