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logic-controlled Datasheet PDF File

For logic-controlled Found Datasheets File :: 36047 Search Time::5.266ms
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				SpectraLinear Inc
Part No.	W149
OCR Text	........................ 175 ps Logic Block Diagram VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC PLL Ref Freq Pin Configuration[2] REF1/FS2 ...controlled by voltage applied to VDDQ2. PCI Clock Outputs 1 through 5: These five PCI clock outputs ...
Description	440BX AGPset Spread Spectrum Frequency Synthesizer
File Size	198.79K / 15 Page	View it Online	Download Datasheet

				Fairchild Semiconductor
Part No.	74LCXZ16224405 74LCXZ162244 74LCXZ162244MEA 74LCXZ162244MEX 74LCXZ162244MTD 74LCXZ162244MTX
OCR Text	...162244 Connection Diagram Logic Symbol Pin Descriptions Pin Names OEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) I...controlled with each nibble functioning identically, but independent of the other. The control pins ...
Description	Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs/Outputs and 26ohm Series Resistors in the Outputs
File Size	91.02K / 8 Page	View it Online	Download Datasheet

				Fairchild Semiconductor Corporation
Part No.	74LCXZ16240 74LCXZ16240MEA 74LCXZ16240MTD
OCR Text	... code. Connection Diagram Logic Symbol Pin Descriptions Pin Names OEn I0-I15 O0-O15 Description Output Enable Inputs (Active LOW) ...controlled with each nibble functioning identically, but independent of the other. The control pins ...
Description	Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary)
File Size	86.90K / 8 Page	View it Online	Download Datasheet

				AD[Analog Devices]
Part No.	AD9953 AD9953ASV AD9953PCB
OCR Text	...U X 0 SYNC Timing & Control Logic 4 Control Registers Oscillator/Buffer RefClk RefClk ENABLE 4x-20x Clock Multipler M U...Controlled Modes of Operation 24 Direct Switch Mode 24 Ramp-Up Mode 25 Bi-directional Ramp Mode 25 C...
Description	400 MSPS 14-Bit DAC 1.8 V CMOS Direct Digital Synthesizer with 1024x32 RAM 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer
File Size	459.48K / 42 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems] INTEGRATED DEVICE TECHNOLOGY INC
Part No.	M2040 M2040-01I400.0000 M2040-01-400.0000 M2040-01I533.3334 M2040-01-533.3334
OCR Text	...n Initialization; LVCMOS/LVTTL: Logic 1 allows device to enter narrow mode if selected (in addition must have 8 LOL=0 counts) Logic 0 forced...controlled output clock phase change during a reference clock reselection. HS is triggered by a Loss...
Description	FREQUENCY TRANSLATION PLL WITH AUTOSWITCH SAW PLL for Fault Tolerant Computers with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching PHASE LOCKED LOOP, 285 MHz, CQCC36
File Size	189.51K / 12 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CY7B9973V-AC CY7B9973V
OCR Text	...ide the reference frequency. Logic Diagram PECL_CLK (11) PECL_CLK (12) PLL_En (6) Ref_Sel (7) TCLK_Sel (8) 1 LOCK (25) Qa0 (50) 0 D...Controlled by TCLK_Sel TCLK0 Bypass PLL Noninverted Qc2, Qc3 /4 /6 /8 /10 /8 /12 /16 /20 Maste...
Description	High-Speed Multi-Output PLL Clock Buffer
File Size	152.92K / 8 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	ICS9LPRS464YGLFT
OCR Text	...funtional block diagram control logic xtal osc. fixed pll 48mhz(1:0) ref(2:0) srcclk(5:0) x1 x2 pll cpu div pd smbdat smbclk fs(2:0) clkreqb# atig div atigclk(1:0) cpuclk(1:0) clkreqc# i r e f src div htt div httclk0 reset_in# clkreqa# 5 ...
Description	System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 240 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153N, TSSOP-56
File Size	248.25K / 23 Page	View it Online	Download Datasheet

				CYPRESS SEMICONDUCTOR CORP
Part No.	CY7C1329-100AI CY7C132904 CY7C1329-100ACT CY7C1329-133ACT
OCR Text	...condary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[15:0] GW BWE BW 3 BW2 BW1 MODE (A[1:0]) 2 BURST Q0 CE ...controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] are place...
Description	64K X 32 CACHE SRAM, 4.2 ns, PQFP100 64K X 32 CACHE SRAM, 5 ns, PQFP100 64K x 32 Synchronous-Pipelined Cache RAM
File Size	349.22K / 15 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CY7C1334H-133AXC CY7C1334H-133AXI CY7C1334H-166AXC CY7C1334H-166AXI
OCR Text	...anced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle....controlled by the rising edge of the clock. All data outputs pass through output registers controlle...
Description	2-Mbit (64K x 32) Pipelined SRAM with NoBL?/a> Architecture 2-Mbit (64K x 32) Pipelined SRAM with NoBLArchitecture 2-Mbit (64K x 32) Pipelined SRAM with NoBL Architecture 2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ Architecture
File Size	573.33K / 13 Page	View it Online	Download Datasheet

For logic-controlled Found Datasheets File :: 36047 Search Time::5.266ms
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