Description |
lor='#FF0000'>1K x 8 Duallor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port Static Ram lor='#FF0000'>1K X 8 DUAllor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port SRAM, lor='#FF0000'>lor='#FF0000'>2lor='#FF0000'>5 ns, PQFPlor='#FF0000'>5lor='#FF0000'>lor='#FF0000'>2 lor='#FF0000'>1K x 8 Duallor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port Static Ram lor='#FF0000'>1K X 8 DUAllor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port SRAM, 4lor='#FF0000'>5 ns, PQCClor='#FF0000'>5lor='#FF0000'>lor='#FF0000'>2 lor='#FF0000'>1K x 8 Duallor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port Static Ram lor='#FF0000'>1K X 8 DUAllor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port SRAM, lor='#FF0000'>lor='#FF0000'>30 ns, PDIP48 lor='#FF0000'>1K x 8 Duallor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port Static Ram lor='#FF0000'>1K X 8 DUAllor='#FF0000'>lor='#FF0000'>-lor='#FF0000'>port SRAM, lor='#FF0000'>5lor='#FF0000'>5 ns, PDIP48
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