Description |
256 Kbit (32K x 8) nvSRAm; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 5; Operating Range: 0 to 70 C 256K (32K x 8) Static RAm; Density: 256 Kb; Organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V; Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 mHz to 166 mHz; Output Range: 1 mHz to 200 mHz; Outputs: 6 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 256; Vcc (V): 3.3; fmax (mHz): 66; tPD (ns): 12 8-mbit (512K x 16) Static RAm; Density: 8 mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V; 9-mbit (256K x 36/512K x 18) pipelined SRAm; Architecture: Standard sync, Pipeline SCD; Density: 9 mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V 9-mbit (256K x 36/512K x 18) Flow-Through SRAm; Architecture: Standard sync, Flow-through; Density: 9 mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V 18-mbit QDR(Tm)-II SRAm 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 mHz to 140 mHz; Outputs: 4; Operating Range: 0 to 70 C 18-mbit QDR(Tm)-II SRAm 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V 9-mbit (256K x 36/512K x 18) Flow-Through SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Flow-through; Density: 9 mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V 9-mbit (256K x 36/512K x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 9 mb; Organization: 512Kb x 18; Vcc (V): 2.4 to 2.6 V 4-mbit (512K x 8) Static RAm; Density: 4 mb; Organization: 512Kb x 8; Vcc (V): 4.50 to 5.50 V; 4-mbit (256K x 16) Static RAm; Density: 4 mb; Organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V; 64K x 16 Static RAm; Density: 1 mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V; 1-mbit (64K x 16) Static RAm; Density: 1 mb; Organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V; 9-mbit (256K x 36/512K x 18) pipelined SRAm; Architecture: Standard sync, Pipeline SCD; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 1-mbit (64K x 16) Static RAm; Density: 1 mb; Organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V; 4 mbit (512K x 8/256K x 16) nvSRAm; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 mb; Package: TSOP 4 mbit (512K x 8/256K x 16) nvSRAm; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 mb; Package: TSOP 16-mbit (1m x 16 / 2m x 8) Static RAm; Density: 16 mb; Organization: 1mb x 16; Vcc (V): 4.50 to 5.50 V; 4K x 16/18 and 8K x 16/18 Dual-Port Static RAm with SEm, INT, BUSY; Density: 128 Kb; Organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns 9-mbit (256K x 36/512K x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 9-mbit (256K x 36/512K x 18) Flow-Through SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Flow-through; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 9-mbit (256K x 36/512K x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V 9-mbit (256K x 36/512K x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 9 mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V 8-mbit (512K x 16) Static RAm; Density: 8 mb; Organization: 512Kb x 16; Vcc (V): 4.50 to 5.50 V; 9-mbit (256K x 36/512K x 18) Flow-Through SRAm; Architecture: Standard sync, Flow-through; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 256K x 16 Static RAm; Density: 4 mb; Organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V; 9-mbit (256K x 36/512K x 18) pipelined DCD sync SRAm; Architecture: Standard sync, Pipeline DCD; Density: 9 mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V 4-mbit (256K x 16) Static RAm; Density: 4 mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V; 8-mbit (1024K x 8) Static RAm; Density: 8 mb; Organization: 1mb x 8; Vcc (V): 2.20 to 3.60 V; 18-mbit (512K x 36/1m x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 256K x 16 Static RAm; Density: 4 mb; Organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V; 8-mbit (1m x 8) Static RAm; Density: 8 mb; Organization: 1mb x 8; Vcc (V): 2.20 to 3.60 V; 3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 8; Operating Range: -40 to 85 C Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 mHz to 80 mHz; Outputs: 8; Operating Range: -40 to 85 C 18-mbit (512K x 36/1m x 18) Flow-Through SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Flow-through; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 18-mbit (512K x 36/1m x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 18 mb; Organization: 1mb x 18; Vcc (V): 3.1 to 3.6 V 512K x 8 Static RAm; Density: 4 mb; Organization: 512Kb x 8; Vcc (V): 4.5 to 5.5 V; 18-mbit (512K x 36/1m x 18) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 2.4 to 2.6 V 2.5V or 3.3V, 200-mHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 mHz to 200 mHz; Outputs: 12; Operating Range: -40 to 85 C 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 5; Operating Range: -40 to 85 C 2m x 8 Static RAm; Density: 16 mb; Organization: 2mb x 8; Vcc (V): 3.0 to 3.6 V; 16 mbit (512K X 32) Static RAm; Density: 16 mb; Organization: 512Kb x 32; Vcc (V): 3.0 to 3.6 V; 3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 8; Operating Range: 0 to 70 C 8-mbit (1m x 8) Static RAm; Density: 8 mb; Organization: 1mb x 8; Vcc (V): 3.0 to 3.6 V; 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 5; fmax (mHz): 125; tPD (ns): 6 2-mbit (128K x 16) Static RAm; Density: 2 mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 16-mbit (1m x 16) Static RAm; Density: 16 mb; Organization: 1mb x 16; Vcc (V): 3.0 to 3.6 V; 4-mbit (256K x 18) pipelined DCD sync SRAm; Architecture: Standard sync, Pipeline DCD; Density: 4 mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 512K (32K x 16) Static RAm; Density: 512 Kb; Organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V; 4-mbit (128K x 36) pipelined SRAm with NoBL(Tm) Architecture; Architecture: NoBL, Pipeline; Density: 4 mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V 1m x 16 Static RAm; Density: 16 mb; Organization: 1mb x 16; Vcc (V): 3.0 to 3.6 V; Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 mHz to 80 mHz; Outputs: 8; Operating Range: 0 to 70 C 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 9; Operating Range: 0 to 70 C moBL(R) 2 mbit (128K x 16) Static RAm; Density: 2 mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; Rambus(R) XDR(Tm) Clock Generator; VDD: 2.5 V; Input Frequency: 100 mHz to 133 mHz; Output Frequency: 300 mHz to 800 mHz; # Out: 4 2-mbit (128K x 16) Static RAm; Density: 2 mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 4-mbit (128K x 36) pipelined sync SRAm; Architecture: Standard sync, Pipeline SCD; Density: 4 mb; Organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 128; Vcc (V): 5; fmax (mHz): 167; tPD (ns): 7 2.5V or 3.3V, 200-mHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 mHz to 200 mHz; Outputs: 10; Operating Range: 0 to 70 C 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 128; Vcc (V): 5; fmax (mHz): 100; tPD (ns): 7 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 128; Vcc (V): 5; fmax (mHz): 125; tPD (ns): 7 18-mbit DDR-II SRAm 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 18 mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 mHz to 80 mHz; Outputs: 8; Operating Range: 0 to 70 C Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 mHz to 100 mHz; Output Frequency Range: 25 mHz to 100 mHz; Operating Range: 0 to 70 C; Package: SOIC Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 mHz to 80 mHz; Outputs: 8; Operating Range: 0 to 70 C 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 3.3; fmax (mHz): 143; tPD (ns): 9 单芯位CmOS微机 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 5; fmax (mHz): 154; tPD (ns): 6 单芯位CmOS微机 SINGLE-CHIP 8-BIT CmOS mICROCOmPUTER 单芯位CmOS微机 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 3.3; fmax (mHz): 100; tPD (ns): 9 单芯位CmOS微机 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 128; Vcc (V): 3.3; fmax (mHz): 83; tPD (ns): 10 单芯位CmOS微机 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 5; fmax (mHz): 125; tPD (ns): 6 单芯位CmOS微机 Three-PLL General-Purpose EPROm Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 mHz to 30 mHz; Output Range: .077 mHz to 100 mHz; Outputs: 6 单芯位CmOS微机 8-mbit (512K x 16) moBL(R) Static RAm; Density: 8 mb; Organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CmOS微机 High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 mHz to 110 mHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CmOS微机 3.3V SDRAm Buffer for mobile PCs with 4 SO-DImms; Voltage (V): 3.3 V; Frequency Range: 0 mHz to 100 mHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CmOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 9; Operating Range: -40 to 85 C 单芯位CmOS微机 Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 mHz to 80 mHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CmOS微机 2-mbit (128K x 16) Static RAm; Density: 2 mb; Organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CmOS微机 moBL(R) 1 mbit (128K x 8) Static RAm; Density: 1 mb; Organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CmOS微机 18-mbit QDR(Tm)-II SRAm 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 mb; Organization: 1mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CmOS微机 1-mbit (128K x 8) Static RAm; Density: 1 mb; Organization: 128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CmOS微机 4-mbit (256K x 18) pipelined sync SRAm; Architecture: Standard sync, Pipeline SCD; Density: 4 mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CmOS微机 2-mbit (64K x 32) pipelined sync SRAm; Architecture: Standard sync, Pipeline SCD; Density: 2 mb; Organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CmOS微机 200-mHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 mHz to 200 mHz; Outputs: 12; Operating Range: -40 to 85 C 单芯位CmOS微机 2-mbit (128K x 16) Static RAm; Density: 2 mb; Organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CmOS微机 SINGLE-CHIP 8-BIT CmOS mICROCOmPUTER 单芯8位CmOS微机 2-mbit (256K x 8) Static RAm; Density: 2 mb; Organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CmOS微机 Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 mHz to 133 mHz; Output Range: 20 mHz to 200 mHz; Outputs: 2 单芯位CmOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CmOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 5; Operating Range: -40 to 85 C 单芯位CmOS微机 Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 mHz to 166 mHz; Output Range: 0 mHz to 200 mHz; Outputs: 3 单芯位CmOS微机 1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 mHz to 350 mHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CmOS微机 Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 mHz to 27 mHz; Output Range: 4.2 mHz to 166 mHz; Outputs: 5 单芯位CmOS微机 2.5V or 3.3V, 200-mHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 mHz to 200 mHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CmOS微机 3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 mHz to 133 mHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CmOS微机 High Speed multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 mHz to 200 mHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CmOS微机 2.5V or 3.3V, 200-mHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 mHz to 200 mHz; Outputs: 18; Operating Range: -40 to 85 C 单芯位CmOS微机 -bit AVR microcontroller with 8K Bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪 2.5V or 3.3V, 200-mHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 mHz to 200 mHz; Outputs: 12; Operating Range: 0 to 70 C 1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 mHz to 350 mHz; Outputs: 8; Operating Range: 0 to 70 C Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 mHz to 32 mHz; Output Frequency Range: 4 mHz to 32 mHz; Operating Range: 0 to 70 C; Package: SOIC High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 mHz to 110 mHz; Outputs: 8; Operating Range: 0 to 70 C 5V, 3.3V, ISR(Tm) High-Performance CPLDs; # macrocells: 64; Vcc (V): 3.3; fmax (mHz): 100; tPD (ns): 9
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