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Fairchild Semiconductor Corporation
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| Part No. |
ML6421
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| OCR Text |
phase and sinx/x equalized, low-pass video filter 1 block diagram triple input/anti-aliasing video filter 15 5 6 4 buf 1x/2x buf low pass filter a v in a 10 v out a 3k w 1k w 3.33k w 16 1 buf low pass filter b v in b 9 3 v out b 3.33k w 2 1... |
| Description |
Triple Phase and Sinx/x Equalized, Low-Pass Video Filter(三相和Sinx/x相均衡的视频低通滤波器)
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| File Size |
241.52K /
12 Page |
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Pulse Engineering
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| Part No. |
PE-68538G PE-68531G PE-68532G PE-68537G
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| OCR Text |
...uency dependent attenuation and phase distortion which the signal suffers in the cable. The optimum compensation required will vary with cab...equalized and DC restored signal is decoded in the line decoder as per appropriate scheme and driven... |
| Description |
(PE-6853xG) Fastpulse High Speed LAN Transceivers
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| File Size |
258.79K /
8 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT77V7101 77V7101_DS_98613
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| OCR Text |
... internal Receive PLL locks the phase of its VCO to that of the incoming data to produce a bitclock. This bit-clock is then divided down to become the internal 125MHz code-group clock (ICLK). Finally, the recovered receive clock is output a... |
| Description |
Gigabit SERDES Transceiver
From old datasheet system
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| File Size |
155.23K /
13 Page |
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it Online |
Download Datasheet |
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Keysight Technologies
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| Part No. |
1810-0118 11904-60004
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| OCR Text |
...ck for the error detector. the phase delay between these clocks must be adjustable in fne resolution of time to center the error detector sample point in the eye. the n4960a serial bert controller has dedicated outputs for both jitter... |
| Description |
Serial BERT 17 and 32 Gb/s
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| File Size |
4,664.35K /
26 Page |
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it Online |
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Price and Availability
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