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Pericom Technology
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| Part No. |
PI6C2502
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| OCR Text |
...eatures a low-skew, low-jitter, phase-locked loop (pll) clock driver. by connecting the feedback fb_out output to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. product featur... |
| Description |
phase-locked Loop Clock Driver
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| File Size |
367.25K /
6 Page |
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it Online |
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| Part No. |
CYW2330
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| OCR Text |
...Bit Programmable Counter
fp1 Phase Detector Charge Pump
DOPLL1 (3)
19-Bit Latch OSC_IN (8)
Pwr-dwn PLL1 fr1 fr fp Monitor Output...locked. It is multiplexed to the output of the programmable counters or reference dividers in the te... |
| Description |
From old datasheet system
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| File Size |
160.43K /
10 Page |
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it Online |
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| Part No. |
CYW3335
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| OCR Text |
...Bit Programmable Counter
fp1 Phase Detector Charge Pump
DOPLL1 (3)
19-Bit Latch OSC_IN (8)
Pwr-dwn PLL1 fr1 fr fp Monitor Output...locked. It is multiplexed to the output of the programmable counters or reference dividers in the te... |
| Description |
From old datasheet system
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| File Size |
157.75K /
10 Page |
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it Online |
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| Part No. |
W183G
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| OCR Text |
...al Description
The W183 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Fig... |
| Description |
MISCELLANEOUS CLOCK GENERATOR|CMOS|SOP|14PIN|PLASTIC
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| File Size |
124.94K /
9 Page |
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it Online |
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| Part No. |
4923PI_2
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| OCR Text |
... Buffers q DAC Clock via Analog Phase Locked Loop q Dedicated Byte or Serial Host Interface q Multiple Compressed Data Input Modes q PES Layer Decode for A/V Sync q 96 kHz Capable PCM I/O, Master or Slave q Optional External Memory and Auto... |
| Description |
From old datasheet system
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| File Size |
176.36K /
7 Page |
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it Online |
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| Part No. |
E421215
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| OCR Text |
...ntermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with pulse swallow operation. The reference divider and comparison divider have fixed divide ratios, so that it is not required to set the divide ratios by a micr... |
| Description |
From old datasheet system
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| File Size |
106.01K /
17 Page |
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it Online |
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| Part No. |
395
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| OCR Text |
...
wn
0
Where; Kf is the phase detector gain factor in mA/radian K0 is the VCO gain factor in radian/second/Volt N is the total divis...locked operating point is critical, the input offset voltage of most amplifiers can be adjusted to n... |
| Description |
From old datasheet system
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| File Size |
179.24K /
13 Page |
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it Online |
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| Part No. |
E421216
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| OCR Text |
...ntermediate Frequency (IF) band Phase Locked Loop (PLL) frequency synthesizer with pulse swallow operation. The reference divider and comparison divider have fixed divide ratios, so that it is not required to set the divide ratios by a micr... |
| Description |
From old datasheet system
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| File Size |
101.71K /
16 Page |
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it Online |
Download Datasheet |
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