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IDT
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Part No. |
IDT77V7101 77V7101_DS_98613
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OCR Text |
... internal Receive PLL locks the phase of its VCO to that of the incoming data to produce a bitclock. This bit-clock is then divided down to become the internal 125MHz code-group clock (ICLK). Finally, the recovered receive clock is output a... |
Description |
Gigabit SERDES Transceiver From old datasheet system
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File Size |
155.23K /
13 Page |
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it Online |
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PHILIPS[Philips Semiconductors]
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Part No. |
SZA1000H SZA1000
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OCR Text |
... run-in capability - Ideal zero phase restart. * Parallel 8-bit input and output for product development and production testing * Programmab...equalized signal at the interpolator output generates a read pulse. The peak is detected if a zero c... |
Description |
QIC digital equalizer
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File Size |
164.79K /
32 Page |
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it Online |
Download Datasheet |
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Price and Availability
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