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ATMEL[ATMEL Corporation]
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| Part No. |
ATLV15 ATLV7 ATLV10 ATLV2 ATLV20 ATLV3 ATLV35 ATLV5
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| OCR Text |
...000 10,000 15,000 22,000 35,000 routable Gates 1,400 1,600 2,800 4,400 6,600 8,000 12,000 18,000 Max Pin Count 44 68 84 100 120 144 160 208 Max I/O(1) Pins 36 60 76 92 112 136 152 192 Gate(2) Speed 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns ... |
| Description |
From old datasheet system
ATLV Series Ultra Low Voltage Gate Arrays
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| File Size |
49.11K /
7 Page |
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List of Unclassifed Manufacturers
ETC
QuickLogic Corp.
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| Part No. |
QL2003 QL2003_DS QL2003-0PF100C QL2003-0PF100I QL2003-0PF144C QL2003-0PF144I QL2003-0PL84I QL2003-1PF100I QL2003-1PL84C QL2003-2PF144C QL2003-2PL84C QL2003-2PL84I QL2003-XPF144I QL2003-XPL84C QL2003-1PF100C QL2003-1PF144I QL2003-1PL84I QL2003-2PF100I QL2003-XPF100C QL2003-0PL84C QL2003-XPF144C QL2003-1PF144C QL2003-2PF100C QL2003-2PF144I QL2003-XPF100I QL2003-XPL84I
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| OCR Text |
...ocess for small die sizes -100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragme... |
| Description |
3.3V and 5.0V pASIC2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASICò 2 FPGA
From old datasheet system
3.3V AND 5.0V PASIC-R 2 FPGA COMBINING SPEED, DENSITY, LOW COST AND FLEXIBILITY
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
FPGA, 192 CLBS, 5000 GATES, 200 MHz, PQCC84
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| File Size |
329.53K /
10 Page |
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QuickLogic
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| Part No. |
QL3012
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| OCR Text |
...Fast Development Cycles
* 100% routable with 100% utilization and
inputs -- each driven by an input-only pin * Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock,... |
| Description |
qASIC 3 FPGA
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| File Size |
158.78K /
16 Page |
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Xilinx, Inc.
XILINX INC
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| Part No. |
XCR3064 DS036 XCR3064-12PC68I XCR3064-12PC84I XCR3064-10PC84C
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| OCR Text |
...ic power of less than 50 A 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Four clocks available Programmable clock polarity at every macrocell Suppo... |
| Description |
EE PLD, 10 ns, PQCC84
EE PLD, 12 ns, PQCC84
64 Macrocell CPLD(64瀹????????缂???昏??ㄤ欢)
EE PLD, 12 ns, PQCC68
From old datasheet system
Product Specification
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| File Size |
111.78K /
15 Page |
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Price and Availability
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