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two-clock Datasheet PDF File

For two-clock Found Datasheets File :: 60038 Search Time::2.734ms
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				ATMEL Corporation
Part No.	ATTINY2011
OCR Text	...? one 8-bit timer/counte r with two pwm channels ? one 16-bit timer/counter with two pwm channels ? 10-bit analog to digital converter ? 8 s...clock is not running and prov ided the reset pin has not been disabled. the min- imum pulse length i...
Description	8-bit Microcontroller with 2K Bytes In-System Programmable Flash
File Size	4,720.16K / 224 Page	View it Online	Download Datasheet

				SpectraLinear Inc
Part No.	CY28346ZC CY28346ZCT CY28346 CY28346OC CY28346OCT CY28346OXC CY28346OXCT CY28346ZXC CY28346ZXCT
OCR Text	..., November 24, 2006 CY28346 Two-Wire SMBus Control Interface The two-wire control interface implements a Read/Write slave only interfac...Clock Register[2,3] Bit 7 6 @Pup 0 0 Pin# Description Spread Spectrum Enable. 0 = Spread Off, 1 = Sp...
Description	Clock Synthesizer with Differential CPU Outputs
File Size	217.35K / 19 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1270V18 CY7C1270V18-300BZC CY7C1270V18-300BZI CY7C1270V18-300BZXC CY7C1270V18-300BZXI CY7C1270V18-333BZC CY7C1270V18-333BZXC CY7C1270V18-333BZXI CY7C1270V18-375BZC CY7C1270V18-375BZI CY7C1270V18-375BZXC CY7C1270V18-375BZXI CY7C1270V18-400BZC CY7C1270V18-400BZXC CY7C1270V18-400BZXI CY7C1266V18-333BZC CY7C1268V18-333BZC
OCR Text	...d latency of 2.5 clock cycles * Two input clocks (K and K) for precise DDR timing * * * * * * * * * -- SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Data valid pin (QVLD) to indicate valid d...
Description	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	1,082.18K / 27 Page	View it Online	Download Datasheet

				Pericom Semiconductor C... Pericom Semiconductor, Corp. Pericom Semiconductor Corp.
Part No.	PI6C2308A-6W PI6C2308A-2WI PI6C2308A-6WI PI6C2308A-6LII PI6C2308A-3WI PI6C2308A-3LI PI6C2308A-1LI PI6C2308A-1WI PI6C2308A-4WI PI6C2308A-1HW PI6C2308A-2L PI6C2308A4L PI6C2308A-6 PI6C2308A3L
OCR Text	...e-device skew less than 500ps - two banks of four outputs, hi-z by two select inputs low jitter, less than 200ps 3.3v operation available...clock signals in applications including pc, workstation, datacom, telecom, and high-performance syst...
Description	BUZZER MAGNETIC 5.0V 13MM SMD 3.3零延时缓冲器 3.3V Zero-Delay Buffer 3.3零延时缓冲器
File Size	386.73K / 10 Page	View it Online	Download Datasheet

				Atmel Corp. ATMEL Corporation Atmel, Corp.
Part No.	PC7457VGU1200N PC7457VGU1000L PC7457VGU1000N PC7457VGU1200L PC7447 PC7447MG1000L PC7447VG933L MG1200N PC7447VGH1200L PC7447VG1000L PC7447VG1000N PC7457VGU933N
OCR Text	...branch history table (bht) with two bits per entry for four levels of prediction ? not-taken, strongly not-taken, taken, and strongly taken ...clock cycle ? space must be available in the cq for an instruction to dispatch (this includes instru...
Description	(PC7447 / PC7457) PowerPC 7457 RISC Microprocessor PowerPC 7457 RISC Microprocessor 7457的PowerPC RISC微处理器
File Size	530.00K / 66 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1423BV18 CY7C1423BV18-167BZC CY7C1422BV18 CY7C1422BV18-167BZC CY7C1422BV18-167BZXC CY7C1422BV18-167BZXI CY7C1422BV18-200BZC CY7C1422BV18-200BZI CY7C1422BV18-200BZXC CY7C1422BV18-200BZXI CY7C1422BV18-250BZC
OCR Text	...sferred at 600 MHz) @ 300 MHz * Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only * Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches * Echo clocks (CQ and CQ) simpli...
Description	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
File Size	1,163.76K / 28 Page	View it Online	Download Datasheet

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