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Xilinx
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| Part No. |
XCR5032C DS046
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| OCR Text |
...ic power of less than 75 A 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Up to six clocks available Programmable clock polarity at every macrocell ... |
| Description |
with Enhanced Clocking
From old datasheet system
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| File Size |
194.58K /
17 Page |
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QuickLogic Corp.
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| Part No. |
QL2005 QL2005-1PQ208I QL2005-1PQ208C
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| OCR Text |
...ocess for small die sizes -100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragme... |
| Description |
3.3V and 5.0V pASIC 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
3.3V and 5.0V pASICò 2 FPGA
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(楂??锛?????瀵?害锛????????????у己??.3V??.0V pASIC 2绯诲??哄?缂???昏??ㄤ欢)
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| File Size |
299.72K /
10 Page |
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it Online |
Download Datasheet |
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Atmel
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| Part No. |
UA1
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| OCR Text |
...416 468 516 576 676 776 876 952 routable Gates 3729 11760 19734 29760 42211 52222 63298 79866 107538 13124 160020 204552 292288 369164 451269 565431 658314 826353 1025460 1407636 1691906 2151765 2360609 Equivalent FPGA Gates 14916 47044 789... |
| Description |
0.35 um ULC Series. Up to 1,000,000 gates
From old datasheet system
Rail-to-rail high output current dual operational amplifier
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| File Size |
48.92K /
8 Page |
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it Online |
Download Datasheet |
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Price and Availability
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