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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1513JV18-250BZXC
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| Description |
72-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR sram, 0.45 ns, PBGA165
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| File Size |
908.32K /
24 Page |
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it Online |
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| Part No. |
4559 M34559G6-XXXFP
|
| Description |
18-Mbit (512K x 36/1M x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 单芯位微机的CMOS
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| File Size |
1,769.11K /
148 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1020BN-12VXCT CY7C1020BN-15ZXC CY7C1020BN-12ZC
|
| Description |
32K x 16 Static RAM; Density: 512 Kb; organization: 32Kb x 16; Vcc (V): 4.5 to 5.5 V; 32K X 16 STANDARD sram, 12 ns, PDSO44
32K x 16 Static RAM 32K X 16 STANDARD sram, 15 ns, PDSO44
32K x 16 Static RAM; Density: 512 Kb; organization: 32Kb x 16; Vcc (V): 4.5 to 5.5 V;
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| File Size |
400.10K /
8 Page |
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it Online |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
CY7C1415BV18-250BZI CY7C1415BV18-167BZI
|
| Description |
36-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 1M X 36 QDR sram, 0.45 ns, PBGA165
36-Mbit QDR™-II sram 4-word Burst Architecture
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| File Size |
956.33K /
30 Page |
View
it Online |
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Cypress Semiconductor, Corp.
|
| Part No. |
CY14E104M-ZS20XI CY14E104K-ZS25XCT CY14E104M-ZS25XCT CY14E104K-ZS15XCT CY14E104K-ZS15XI CY14E104K-ZS15XIT CY14E104K-ZS20XCT CY14E104K-ZS20XI CY14E104K-ZS20XIT CY14E104K-ZS25XI CY14E104K-ZS25XIT CY14E104M-ZS20XCT CY14E104M-ZS15XI CY14E104M-ZS15XCT CY14E104K CY14E104K-ZS45XCT CY14E104K-ZS45XI CY14E104K-ZS45XIT CY14E104K-ZSP15XCT CY14E104K-ZSP15XI CY14E104K-ZSP15XIT CY14E104K-ZSP20XCT CY14E104K-ZSP20XI CY14E104K-ZSP20XIT CY14E104K-ZSP25XCT CY14E104K-ZSP25XI CY14E104K-ZSP25XIT CY14E104K-ZSP45XCT CY14E104K-ZSP45XI CY14E104K-ZSP45XIT CY14E104M-ZSP15XCT CY14E104M-ZS20XIT CY14E104M-ZSP15XIT CY14E104M-ZSP20XCT CY14E104M-ZSP25XI CY14E104M-ZS15XIT CY14E104M-ZS25XIT CY14E104M-ZS45XCT CY14E104M-ZS45XIT CY14E104M-ZSP25XCT CY14E104M-ZSP20XI CY14E104M-ZSP20XIT CY14E104M-ZSP25XIT
|
| Description |
Non-Volatile Static RAM (nvsram); organization: 256x16; Density: 4MB; Speed: 25ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 54-TSOP-II; Features: Real-Time Clock 256K X 16 NON-VOLATILE sram, 25 ns, PDSO54
Non-Volatile Static RAM (nvsram); organization: 256x16; Density: 4MB; Speed: 15ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 44-TSOP-II ; Features: Real-Time Clock 256K X 16 NON-VOLATILE sram, 15 ns, PDSO44
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 45ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 44-TSOP-II ; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 45 ns, PDSO44
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 15ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 44-TSOP-II; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 15 ns, PDSO44
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 25ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 54-TSOP-II ; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 25 ns, PDSO54
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 15ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 44-TSOP-II ; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 15 ns, PDSO44
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 25ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 54-TSOP-II; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 25 ns, PDSO54
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 15ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 54-TSOP-II ; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 15 ns, PDSO54
Non-Volatile Static RAM (nvsram); organization: 512x8; Density: 4MB; Speed: 15ns; Supply Voltage: 5V; Temperature Range: -40° to 85°C; Package: 54-TSOP-II; Features: Real-Time Clock 512K X 8 NON-VOLATILE sram, 15 ns, PDSO54
4 Mbit (512K x 8 / 256K x 16) nvsram with Real-Time-Clock
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| File Size |
538.87K /
28 Page |
View
it Online |
Download Datasheet |
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| Part No. |
M38030F2L-XXXHP M38030F2L-XXXKP M38030F2L-XXXSP M38030F2L-XXXWG M38030MAL-XXXWG M38030MAL-XXXKP M38030FAL-XXXSP M38031FAL-XXXHP M38030FAL-XXXWG M38030MAL-XXXHP M38030FAL-XXXKP M38031FAL-XXXKP M38030FAL-XXXHP M38031FAL-XXXSP M38031FAL-XXXWG M38030MAL-XXXSP M38030F3L-XXXHP M38030F3L-XXXWG M38030M3L-XXXKP M38030F3L-XXXSP M38030F3L-XXXKP M38030M3L-XXXHP M38030FBL-XXXWG M38030MBL-XXXHP M38030FBL-XXXHP M38030FBL-XXXSP M38030MBL-XXXKP M38030M2L-XXXHP M38030M2L-XXXKP M38030M2L-XXXSP M38030M2L-XXXWG M38031F2L-XXXHP M38031F2L-XXXKP M38031F2L-XXXSP M38031F2L-XXXWG M38030FB-XXXHP M38031FBL-XXXSP M38035MBL-XXXSP M38038FBL-XXXSP M38039FBL-XXXSP M38030MBL-XXXSP M38036MBL-XXXSP M38037FBL-XXXSP M38037MBL-XXXSP M38036FBL-XXXSP M38038MBL-XXXSP M38031FC-XXXHP M38031FC-XXXKP M38031FC-XXXWG M38031FCL-XXXHP M38031FCL-XXXKP M38031FCL-XXXSP M38031FCL-XXXWG M38031F5-XXXKP M38031F5-XXXSP M38031F5-XXXWG M38031F5L-XXXHP M38031F5L-XXXKP M38031F5L-XXXSP M38031F5L-XXXWG M38030F1-XXXHP M38030F1-XXXKP M38030F1-XXXSP M38030F1-XXXWG M38030F1L-XXXHP M38030F1L-XXXKP M38030F1L-XXXSP M38030F1L-XXXWG M38031F1-XXXKP M38031F1-XXXWG M38031F1L-XXXHP M38031F1L-XXXKP M38031F6-XXXHP M38031F6-XXXKP M38031F6-XXXSP M38031F6-XXXWG M
|
| Description |
256 Kbit (32K x 8) nvsram; organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C
256K (32K x 8) Static RAM; Density: 256 Kb; organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V;
Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to 200 MHz; Outputs: 6
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 12
8-Mbit (512K x 16) Static RAM; Density: 8 Mb; organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V;
9-Mbit (256K x 36/512K x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 9 Mb; organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
18-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C
18-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
9-Mbit (256K x 36/512K x 18) Flow-Through sram with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 512Kb x 18; Vcc (V): 2.4 to 2.6 V
4-Mbit (512K x 8) Static RAM; Density: 4 Mb; organization: 512Kb x 8; Vcc (V): 4.50 to 5.50 V;
4-Mbit (256K x 16) Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 2.20 to 3.60 V;
64K x 16 Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
1-Mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
1-Mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;
4 Mbit (512K x 8/256K x 16) nvsram; organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
4 Mbit (512K x 8/256K x 16) nvsram; organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP
16-Mbit (1M x 16 / 2M x 8) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 4.50 to 5.50 V;
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY; Density: 128 Kb; organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns
9-Mbit (256K x 36/512K x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Flow-Through sram with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
9-Mbit (256K x 36/512K x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 V
9-Mbit (256K x 36/512K x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
8-Mbit (512K x 16) Static RAM; Density: 8 Mb; organization: 512Kb x 16; Vcc (V): 4.50 to 5.50 V;
9-Mbit (256K x 36/512K x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 4.5 to 5.5 V;
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync sram; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
4-Mbit (256K x 16) Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1024K x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
18-Mbit (512K x 36/1M x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
256K x 16 Static RAM; Density: 4 Mb; organization: 256Kb x 16; Vcc (V): 3.0 to 3.6 V;
8-Mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 2.20 to 3.60 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: -40 to 85 C
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C
18-Mbit (512K x 36/1M x 18) Flow-Through sram with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
512K x 8 Static RAM; Density: 4 Mb; organization: 512Kb x 8; Vcc (V): 4.5 to 5.5 V;
18-Mbit (512K x 36/1M x 18) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 2.4 to 2.6 V
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C
2M x 8 Static RAM; Density: 16 Mb; organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;
16 Mbit (512K X 32) Static RAM; Density: 16 Mb; organization: 512Kb x 32; Vcc (V): 3.0 to 3.6 V;
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C
8-Mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V;
16-Mbit (1M x 16) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (256K x 18) Pipelined DCD Sync sram; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V
512K (32K x 16) Static RAM; Density: 512 Kb; organization: 32Kb x 16; Vcc (V): 3.0 to 3.6 V;
4-Mbit (128K x 36) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
1M x 16 Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C
MoBL(R) 2 Mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
Rambus(R) XDR(TM) Clock Generator; VDD: 2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V;
4-Mbit (128K x 36) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: 128Kb x 36; Vcc (V): 3.1 to 3.6 V
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 10; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 7
18-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V
low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 25 MHz to 100 MHz; Output Frequency Range: 25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC
low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 125; tPD (ns): 6 单芯位CMOS微机
Three-PLL General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机
8-Mbit (512K x 16) MoBL(R) Static RAM; Density: 8 Mb; organization: 512Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -40 to 85 C 单芯位CMOS微机
Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机
MoBL(R) 1 Mbit (128K x 8) Static RAM; Density: 1 Mb; organization: 128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
18-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
1-Mbit (128K x 8) Static RAM; Density: 1 Mb; organization: 128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机
4-Mbit (256K x 18) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
2-Mbit (64K x 32) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; organization: 64Kb x 32; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 10 MHz to 200 MHz; Outputs: 12; Operating Range: -40 to 85 C 单芯位CMOS微机
2-Mbit (128K x 16) Static RAM; Density: 2 Mb; organization: 128Kb x 16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
2-Mbit (256K x 8) Static RAM; Density: 2 Mb; organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机
Very low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C 单芯位CMOS微机
Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机
Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input Range: 27 MHz to 27 MHz; Output Range: 4.2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C 单芯位CMOS微机
3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机
High Speed Multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 18; Operating Range: -40 to 85 C 单芯位CMOS微机
-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 12; Operating Range: 0 to 70 C
1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C
Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 32 MHz; Output Frequency Range: 4 MHz to 32 MHz; Operating Range: 0 to 70 C; Package: SOIC
High Speed low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C
5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1423JV18-250BZXC
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| Description |
36-Mbit DDR-II SIO sram 2-word Burst Architecture; Architecture: DDR-II SIO, 2 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 2M X 18 DDR sram, 0.45 ns, PBGA165
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| File Size |
914.73K /
27 Page |
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