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  -50ps Datasheet PDF File

For -50ps Found Datasheets File :: 511    Search Time::1.031ms    
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    Maxim
Part No. MAX9325
OCR Text ...mely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPE...
Description 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver

File Size 316.07K  /  12 Page

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    MAMUSM0008 MAMUSM0008-TB MAMUSM0008TR

M/A-COM Technology Solutions, Inc.
Part No. MAMUSM0008 MAMUSM0008-TB MAMUSM0008TR
OCR Text ...witch in the first delay line. (50ps). The display will not remain on zero, but will have an offset. Under the Scale/Reference menu, select electrical delay, and dial that up until the data reads zero again, across the band of interest. Tha...
Description Digital Switched Delay Line 1.8 - 2.4 GHz

File Size 177.18K  /  6 Page

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    SHM-4860 SHM-4860_883 SHM-4860MC SHM-4860MM SHM-4860/883

Murata Power Solutions Inc.
Part No. SHM-4860 SHM-4860_883 SHM-4860MC SHM-4860MM SHM-4860/883
OCR Text ...me 74dB Feedthrough attenuation 50ps Aperture uncertainty Industry standard PRODUCT OVERVIEW DATEL's SHM-4860 is a high-speed, highly accurate sample hold amplifier designed for precision, high-speed analog signal processing application...
Description Industry-Standard, High-Speed ±0.01% Sample-Hold Amplifiers
Industry-Standard, High-Speed 【0.01% Sample-Hold Amplifiers

File Size 119.28K  /  4 Page

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    Pericom Semiconductor Corp.
Part No. PI6C20800AE
OCR Text 50ps ? low cycle-to-cycle jitter < 50ps ? output enable for all outputs ? outputs tristate control via smbus ? power management control ? programmable pll bandwidth ? pll or fanout operation ? 3.3v operation ? packaging (pb-...
Description 1:8 Clock Driver for Intel PCI Express Chipsets

File Size 259.96K  /  10 Page

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    MAX4889ETO MAX4889 MAX4888 MAX4888ETI

Maxim Integrated Products
Part No. MAX4889ETO MAX4889 MAX4888 MAX4888ETI
OCR Text ... 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 50ps/div *PRBS = PSEUDORANDOM BIT SEQUENCE GEN I; 2.5Gps; UI = 400ps 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) EYE DIAGRAM (V+ = 2.5V, f = 1.25GHz, 600mVP-P PRBS SIGNAL, RS = RL = 5...
Description 2.5Gbps PCI Express Passive Switches

File Size 264.43K  /  16 Page

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    ICS932S421B 932S421BFLFT 932S421BGLFT

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Integrated Device Technology
Part No. ICS932S421B 932S421BFLFT 932S421BGLFT
OCR Text ...cks  cpu cycle-cycle jitter: < 50ps  src cycle-cycle jitter: < 125ps  pci cycle-cycle jitter: < 500ps  cpu output skew: < 50ps  src output skew: < 250ps  100ppm frequency accuracy on all outputs functionality fs_c 1 fs_b 1 fs_a 2 cp...
Description PCIe Gen2 and QPI Clock for Intel-Based Servers

File Size 222.58K  /  23 Page

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    ICS95V857 ICS95V857AG-130LF-T ICS95V857AGLF-T

ICSI[Integrated Circuit Solution Inc]
ICST[Integrated Circuit Systems]
Part No. ICS95V857 ICS95V857AG-130LF-T ICS95V857AGLF-T
OCR Text .......... 0ps - ICS95V857-130 .. +50ps Specifications: * Meets PC3200 Class A+ specification for DDR-I 400 support * Covers all DDRI speed grades Switching Characteristics: * CYCLE - CYCLE jitter: <50ps * OUTPUT - OUTPUT skew: <40ps * Period ...
Description 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)

File Size 113.77K  /  13 Page

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    PI6C20800S PI6C20800SAE PI6C20800SVE

Pericom Semiconductor Corporation
Part No. PI6C20800S PI6C20800SAE PI6C20800SVE
OCR Text ...ifferential Clocks * Low skew < 50ps * Low Cycle-to-cycle jitter < 50ps * Output Enable for all outputs * Outputs Tristate control via SMBus * Power Management Control * Programmable PLL Bandwidth * PLL or Fanout operation * 3.3V Operation ...
Description PCI Express 1:8 HCSL Clock Buffer

File Size 359.76K  /  10 Page

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    SY89809LTCTR SY89809L09

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Micrel Semiconductor
Part No. SY89809LTCTR SY89809L09
OCR Text ...l features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)?performance previously unachievable in a standard product having such a high number of outputs. the sy89809l is available in a single space saving packag...
Description 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver

File Size 300.66K  /  8 Page

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    Integrated Device Technology, Inc.
Part No. ICS95V857YL-130 ICS95V857YG-130
OCR Text ......... 0ps - ics95v857-130 .. +50ps specifications:  meets or exceeds jedec standard #82-1 for registered ddr clock driver.  meets or exceeds proposed ddr1-400 specifications  covers all ddr1 speed grades switching characteristics:  cy...
Description PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 0.173 INCH, TSSOP-48
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 0.240 INCH, TSSOP-48

File Size 188.12K  /  13 Page

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