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divide-by-four Datasheet PDF File

For divide-by-four Found Datasheets File :: 2673 Search Time::1.5ms
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				Cypress Semiconductor
Part No.	CY7B992-2JCT CY7B992-5JCT CY7B992-5JIT CY7B992-5JI27 CY7B992-5JXI CY7B992-5JXIT CY7B992-7JCT CY7B992-7LMB27 CY7B991-2JCT CY7B991-2JXC CY7B991-2JXCT CY7B991-5JCT CY7B991-5JIT CY7B991-5JXC CY7B991-5JXCT CY7B991-5JXI CY7B991-5JXIT CY7B991-7JCT CY7B991-7JXC CY7B991-7JXCT CY7B991-7LMB27 CY7B9917JXC CY7B991.2JC CY7B991.2JCT CY7B991.2JXC CY7B991.5JXIT CY7B992.5JXIT CY7B991.2JXCT CY7B991.5JC CY7B992.2JC CY7B992.2JCT CY7B992.5JC CY7B992.5JCT CY7B992.5JI CY7B992.5JIT CY7B992.5JXI CY7B992.7JC CY7B992.7JCT CY7B992.7JI CY7B991.5JIT CY7B991.5JXI CY7B991.5JXC CY7B991.5JCT CY7B991.5JXCT CY7B991.7JC CY7B991.7JCT CY7B991.7JI CY7B991.7JXCT CY7B991.7LMB CY7B992.7LMB
OCR Text	... delays of up to 12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of...
Description	Programmable Skew Clock Buffer
File Size	385.67K / 19 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp. Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
Part No.	CY7B994V-2AC CY7B994V-2AI CY7B994V-7AC CY7B993V CY7B993V-2AC CY7B993V-2AI CY7B993V-5AC CY7B993V-5AI CY7B993V-7AC CY7B994V CY7B994V-2BBC CY7B994V-2BBI CY7B994V-5AC CY7B994V-5AI CY7B994V-5BBC CY7B994V-5BBI
OCR Text	...steps up to 10.4 ns * Multiply/divide ratios of 1-6, 8, 10, 12 * Individual output bank disable * Output high-impedance option for testing ...by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can b...
Description	High-Speed Multi-Phase PLL Clock Buffer 7B SERIES, PLL BASED CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
File Size	273.07K / 14 Page	View it Online	Download Datasheet

				Mimix Broadband
Part No.	XE1000-BD-EV1 XE1000-BD XE1000-BD-000V
OCR Text	divide-by-four +5.0 dBm Output Power -30 dBc Fundamental Leakage Single-ended or Differential Input & Output 100% On-Wafer, DC and Output Power Testing 100% Visual Inspection to MIL-STD-883 Method 2010 Chip Device Layout XE1000-BD ...
Description	2.0-16.0 GHz GaAs MMIC Frequency Divider
File Size	158.85K / 5 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	ICS9220
OCR Text	...pwd bit 7 post divider pll post divide rw divide by 2 divide by 4 1 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 m div3 rw 0 bit 2 m div2 rw 0 bit 1 m div1 rw 1 bit 0 m div0 rw 0 -...
Description	Programmable RambusTM XDRTM Clock Generator
File Size	211.10K / 17 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY22392ZI-XXXT CY22392ZC-XXX CY22392ZC-XXXT
OCR Text	... phase-locked loops ultra wide divide counters (8-bit q, 11-bit p, and 7-bit post divide) improved linear crystal load capacitors flash ...by using third party programmers from bp microsystems, hilo systems, and others. performance suit...
Description	166 MHz, OTHER CLOCK GENERATOR, PDSO16 4.40 MM, MO-153, TSSOP-16 200 MHz, OTHER CLOCK GENERATOR, PDSO16 4.40 MM, MO-153, TSSOP-16
File Size	298.65K / 9 Page	View it Online	Download Datasheet

				Pericom Semiconductor, Corp. Pericom Semiconductor Corp. PERICOM[Pericom Semiconductor Corporation] Pericom Technology
Part No.	PI6C39911-5J PI6C39911-2J PI6C39911 PI6C399111J
OCR Text	...ut skew of up to 12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of ...
Description	Clock IC \| 500ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz RTS Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 24V; Power: 2W; Assembly; High Power Density; Optional Continuous Short Circuit Protected; Efficiency to 85% 3.3高速LVTTL或平衡输出可编程偏差时钟缓冲 SuperClock 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
File Size	259.69K / 11 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	5V49EE501NLGI 5V49EE501NLGI8
OCR Text	...lated frequencies. each output divide supports 8-bit output-divider (pm and q[7:0]). the following equation governs how the output frequen...by using the pm bit. if the output is disabled, it will be driven high, low or high impedance, dep...
Description	5V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC24 4 X 4 MM, ROHS COMPLIANT, VFQFPN-24
File Size	283.96K / 33 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	5V49EE503NLGI8
OCR Text	...lated frequencies. each output divide supports 8-bit output-divider (pm and q[7:0]). the following equation governs how the output frequen...by using the pm bit. if the output is disabled, it will be driven high, low or high impedance, dep...
Description	5V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC24 4 X 4 MM, ROHS COMPLIANT, VFQFPN-24
File Size	260.77K / 29 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
Part No.	CY7B991-2JXC CY7B991-2JCT CY7B992-2JCT CY7B992-7LMB27 CY7B991-7LMB27 CY7B991-5JIT CY7B991-5JXI CY7B991-2JXCT CY7B991-5JXIT CY7B991-5JXC CY7B992-5JIT CY7B991-7JXCT CY7B991-5JXCT CY7B992-5JXIT
OCR Text	... delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions enable distribution o...
Description	Programmable Skew Clock Buffer 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 Programmable Skew Clock Buffer 可编程偏移时钟缓冲器
File Size	356.44K / 19 Page	View it Online	Download Datasheet

For divide-by-four Found Datasheets File :: 2673 Search Time::1.5ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | <7> | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |