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PROMOS TECHNOLOGIES INC
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Part No. |
V58C2256164SCE5B
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OCR Text |
... command power down mode auto refresh and self refresh refresh interval: 8192 cycles/64 ms available in 66-pin 400 mil tsop or 60 ball fbga sstl-2 compatible i/os double data rate (ddr) bidirectional data strobe (dqs) for input and o... |
Description |
16M X 16 DDR DRAM, 0.65 ns, PDSO66
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File Size |
917.36K /
61 Page |
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it Online |
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Part No. |
MT48LC8M16TG-8ITG MT48V8M16TG-8G
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OCR Text |
... ? temperature compensated self refresh (tcsr) ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operat ion; column address can be changed every clock cycle ? internal banks for hiding row a... |
Description |
8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
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File Size |
6,168.33K /
69 Page |
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it Online |
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INTEGRATED SILICON SOLUTION INC
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Part No. |
IS42SM32400E-75EBLI
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OCR Text |
...quential and interleave ? auto refresh (cbr) ? tcsr (temperature compensated self refresh) ? pasr (partial arrays self refresh): 1/16, 1/8, ? 1/4, 1/2, and full deep power down mode (dpd) ? driver strength control (ds): 1/4, 1/2, an... |
Description |
4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
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File Size |
764.69K /
26 Page |
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it Online |
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Part No. |
K4E151611C-TC50
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OCR Text |
...upply voltage (+5.0v or +3.3v), refresh cycle (1k ref. or 4k ref.), access time (-45, -5 0 or -6 0 ), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have ca... |
Description |
1M X 16 EDO DRAM, 50 ns, PDSO44
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File Size |
558.18K /
35 Page |
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it Online |
Download Datasheet
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Price and Availability
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