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Integrated Device Technology, Inc.
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Part No. |
ICS9DB801CFLFT
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OCR Text |
...re disabled and the vco and the crystal are stopped. 27 src_stop# input active low input to stop src outputs. 28 high_bw# input 3.3v input for selecting pll band width 0 = high, 1= low 29 dif_4# output 0.7v differential complement clock out... |
Description |
Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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File Size |
207.52K /
19 Page |
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it Online |
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Electronic Theatre Controls, Inc.
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Part No. |
ICS813001AGI
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OCR Text |
...femtoclock pll can multiply the crystal frequency of the vcxo to provide an output frequency range of 40.83mhz to 640mhz, with a random rms phase jitter of less than 1ps (12khz ? 20mhz). this phase jitter performance meets the requirements ... |
Description |
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL 双压控W/3.3V.5伏的LVPECL FEMTOCLOCK,商标锁相环
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File Size |
229.40K /
18 Page |
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it Online |
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Cypress Semiconductor, Corp.
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Part No. |
CY24293ZXI CY24293ZXC CYPRESSSEMICONDUCTORCORP-CY24293ZXCT
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OCR Text |
...june 27, 2011 features 25 mhz crystal or clock input two sets of differential pci-express clocks pin selectable output frequencies supp...to ta b l e 2 . 2 s1 input frequency select pin. has internal weak pull-up. refer to ta b l e 2 . ... |
Description |
Two Outputs PCI-Express Clock Generator; VDD: 3.3 V; Input Frequency: 25 MHz; Output Frequency: 25 MHz to 200 MHz; # Out: 2 200 MHz, OTHER CLOCK GENERATOR, PDSO16
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File Size |
220.81K /
13 Page |
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it Online |
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Price and Availability
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