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Integrated Device Technology, Inc.
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| Part No. |
ICSSSTUAF32866CHLFT
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| OCR Text |
...e device monitors both dcs and csr inputs and will gate the qn outputs from changing states when both dcs and csr inputs are high. if either dcs and csr input is low, the qn outputs will fu nction normally. the reset input has pr... |
| Description |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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| File Size |
556.17K /
31 Page |
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it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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| Part No. |
ICSSSTUAF32866B ICSSSTUAF32866BHLFT
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| OCR Text |
...e device monitors both dcs and csr inputs and will gate the qn outputs from changing states when both dcs and csr inputs are high. if either dcs and csr input is low, the qn outputs will fu nction normally. the reset input has pr... |
| Description |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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| File Size |
556.95K /
31 Page |
View
it Online |
Download Datasheet |
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SIEMENS AG
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| Part No. |
SLA24C64
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| OCR Text |
...18 19 figure 13: csw changed to csr. 21 23 the write or erase cycle is finished latest after 10 4ms. 22 24 line supply voltage: text deleted. 23 24 supply current (write) 3 ma 1 ma. 23 24 line added supply current (read). 24 26 the line e... |
| Description |
64 Kbit (8192 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(64K(8192 ×8 串行CMOS-EEPROM(带有IIC同步2线控)
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| File Size |
286.00K /
28 Page |
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it Online |
Download Datasheet |
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SHARP
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| Part No. |
LH28F004SU-Z1 LH28F004SUT-Z1
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| OCR Text |
...d
register output
multiplexer csr esrs data
comparator data
queue
register register i/o
logic cui wsm 16kb block 0 16kb block 1 16kb block 30 16kb block 31 . . . . . . y gating/sensing y-decoder x-decoder oe ce we rp program/
erase
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| Description |
4M (512K x 8) Flash Memory
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| File Size |
206.12K /
32 Page |
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it Online |
Download Datasheet |
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Infineon
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| Part No. |
SLA24C164-D
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| OCR Text |
...e 11: second command byte is a csr and not csw. 18 19 figure 13: csw changed to csr. 18 20 line supply voltage: text deleted. 19 21 capacitive load added. 20 22 some timings changed. 20 22 the line erase/write cycle removed. 20 22 chapte... |
| Description |
CMOS EEPROM I2C/Page Protection Mode
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| File Size |
253.59K /
24 Page |
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it Online |
Download Datasheet |
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Infineon
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| Part No. |
SLA24C164-D/P
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| OCR Text |
...e 11: second command byte is a csr and not csw. 18 19 figure 13: csw changed to csr. 21 23 the write or erase cycle is finished latest after 10 4ms. 23 24 figure 17: ack deleted before stop. 23 25 line supply voltage: text deleted. 19 26... |
| Description |
CMOS EEPROM I2C/Page Protection Mode
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| File Size |
284.00K /
29 Page |
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it Online |
Download Datasheet |
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Intel
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| Part No. |
IXP1240
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| OCR Text |
... sram registers 2 xx 11 nofix csr access using pci memory cycles 3 xx 11 nofix pci_dma instruction 4 xx 12 nofix clock setup time 5 xx 12 nofix hold time issues for all pci signals (both bused and control) 6 xx 12 nofix ix bus contention... |
| Description |
Network Processor
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| File Size |
188.12K /
24 Page |
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it Online |
Download Datasheet |
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Price and Availability
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