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Zarlink Semiconductor
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Part No. |
CLA70000
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OCR Text |
...igned to maximize the number of nets which may be routed through the cell. This enables optimal routing of both data flow and control signal distribution schemes thus giving very high overall utilization factors. This feature is of particul... |
Description |
High Density CMOS Gate Arrays
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File Size |
189.15K /
17 Page |
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it Online |
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XILINX
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Part No. |
XC3190A
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OCR Text |
...al distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier - Easy design iteration - In-system logic changes Extensive Packaging Options - Over 20 different... |
Description |
Logic Cell Array Families
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File Size |
470.92K /
51 Page |
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it Online |
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Xilinx
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Part No. |
XC2S15-6VQ100C
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OCR Text |
...-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 16 high-performance interface... |
Description |
IC,FPGA,432-CELL,CMOS,TQFP,100PIN,PLASTIC
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File Size |
57.66K /
5 Page |
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it Online |
Download Datasheet |
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Price and Availability
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