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  pecl hstl Datasheet PDF File

For pecl hstl Found Datasheets File :: 197    Search Time::1.172ms    
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    PO100HSTL50A PO100HSTL50ASR PO100HSTL50ASU

Potato Semiconductor Corporation
Part No. PO100hstl50A PO100hstl50ASR PO100hstl50ASU
OCR Text ...Test Waveforms FIGURE 1. LVDS/ pecl/ ECL/ hstl /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, a...
Description Dual Differential LVDS/LVpecl/hstl to LVTTL Translator Dual LVTTL/LVCMOS to Differential hstl Translator

File Size 684.99K  /  8 Page

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    PO74HSTL85331A PO74HSTL85331ATR PO74HSTL85331ATU

Potato Semiconductor Corporation
Part No. PO74hstl85331A PO74hstl85331ATR PO74hstl85331ATU
OCR Text ...Test Waveforms FIGURE 1. LVDS/ pecl/ ECL/ hstl /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. hstl/hstl OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pu...
Description 3.3V 1:4 Crystal Oscillator/ Differential Clock or Data Fanout Buffer

File Size 669.38K  /  8 Page

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    SY89536L SY89536LHC SY89533L SY89532L SY89535L SY89534L SY89531L

MICREL[Micrel Semiconductor]
Part No. SY89536L SY89536LHC SY89533L SY89532L SY89535L SY89534L SY89531L
OCR Text ... Within Device Skew Within Bank pecl Within Bank hstl Bank-to-Bank Part-to-Part Skew tLOCK tJITTER Maximum PLL Lock Time Cycle-to-Cycle Jitter Period Jitter tpw (min) Minimum Pulse Width Target PLL Loop Bandwidth Feedback Divider Ratio: 66 ...
Description 3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVpecl AND hstl BUS CLOCK SYNTHESIZER

File Size 151.50K  /  16 Page

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    PO100HSTL23A PO100HSTL23ASR PO100HSTL23ASU PO100HSTL23ATR PO100HSTL23ATU

Potato Semiconductor Corporation
Part No. PO100hstl23A PO100hstl23ASR PO100hstl23ASU PO100hstl23ATR PO100hstl23ATU
OCR Text ...Test Waveforms FIGURE 1. LVDS/ pecl/ ECL/ hstl /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, a...
Description Dual Differential LVDS/LVpecl/hstl to LVTTL Translator

File Size 519.01K  /  6 Page

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    Motorola
Part No. MPC9990
OCR Text ...70C LOW VOLTAGE DIFFERENTIAL pecl-hstl PLL CLOCK DRIVER FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932 The MPC9990 provides output clock frequencies required for high-performance computer system optimization. The device drives up to 10 di...
Description Low Voltage PLL Clock Drlver
From old datasheet system

File Size 199.86K  /  12 Page

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    PO100HSTL179A PO100HSTL179ASR PO100HSTL179ASU

Potato Semiconductor Corporation
Part No. PO100hstl179A PO100hstl179ASR PO100hstl179ASU
OCR Text ...Test Waveforms FIGURE 1. LVDS/ pecl/ ECL/ hstl /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, a...
Description Differential LVDS/LVpecl/hstl to LVTTL Translator LVTTL/LVCMOS to Differential hstl Translator

File Size 688.25K  /  8 Page

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    ICST[Integrated Circuit Systems]
Part No. ICS8702BYT ICS8702 ICS8702BY
OCR Text ... any differential input signal (pecl, hstl, LVDS) to LVCMOS levels without external bias networks Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input Translates any single-ended input signal to inv...
Description LOW SKEW ±1, ±2 CLOCK GENERATOR

File Size 186.44K  /  12 Page

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    PO100HSTL11A PO100HSTL11ASR PO100HSTL11ASU PO100HSTL11ATR PO100HSTL11ATU

Potato Semiconductor Corporation
Part No. PO100hstl11A PO100hstl11ASR PO100hstl11ASU PO100hstl11ATR PO100hstl11ATU
OCR Text ...Test Waveforms FIGURE 1. LVDS/ pecl/ ECL/ hstl /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. hstl/hstl OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pu...
Description 1 to 2 Differential Clock/Data Fanout Buffer

File Size 549.06K  /  6 Page

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    ICST[Integrated Circuit Systems]
Part No. ICS8501BYT ICS8501 ICS8501BY
OCR Text ...s any differential input signal(pecl, hstl, LVDS, DCM) to DCM levels without external bias networks * Translates single ended input levels to DCM levels with a resistor bias network on the nCLK input * Translates single ended input levels t...
Description Low Skew 1-to-16 Differential Current Mode Fanout Buffer

File Size 159.69K  /  8 Page

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    MC100EP35DR2 MC100EP33D NB100LVEP17MN

ON Semiconductor
Part No. MC100EP35DR2 MC100EP33D NB100LVEP17MN
OCR Text ...onductor's high performance ecl/pecl family of products. schematic information the kit contains representative input and output schematics, ...hstl output positive supply v cs internal reference voltage ( vee + 1.1 v 50 mv) v hstl hstl in...
Description 3.3V / 5V ECL JK Flip Flop
3.3V / 5V ECL ÷4 Divider
2.5 V / 3.3 V ECL Quad Differential Driver/Receiver

File Size 199.81K  /  68 Page

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For pecl hstl Found Datasheets File :: 197    Search Time::1.172ms    
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