| PART |
Description |
Maker |
| HD74LS107A HD74LS107AFP HD74LS107AP HD74LS107ARP |
Dual J-K Flip-Flops with Clear
Dual J-K Negative-edge-triggered Flip-Flops(with Clear)
FLIP-FLOP|DUAL|J/K TYPE|LS-TTL|SOP|14PIN|PLASTIC
FLIP-FLOP|DUAL|J/K TYPE|LS-TTL|DIP|14PIN|PLASTIC
|
HITACHI[Hitachi Semiconductor]
|
| HD74HC76 HD74HC76P |
FLIP-FLOP|DUAL|J/K TYPE|HC-CMOS|DIP|16PIN|PLASTIC
Dual J-K Flip-Flops (with Preset and Clear)
|
HITACHI[Hitachi Semiconductor]
|
| HD74HC113P HD74HC113FPEL |
Dual J-K Flip-Flops (with Preset)
|
Renesas Electronics Corporation
|
| HD74ALVCH16820 |
3.3-V 10-bit Flip Flops with Dual Outputs
|
HITACHI[Hitachi Semiconductor]
|
| HD74HC76 HD74HC76FPEL HD74HC76P |
Dual J-K Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| HD74HC109 HD74HC109RPEL HD74HC109FPEL HD74HC109P |
Dual J-K Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| HD74LS76A HD74LS76AP HD74LS76ARPEL |
Dual J-K Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| HCF4518 HCF4518B HCF4518BC1 HCF4518BEY HCF4518BF H |
Dual Up-Counters(???璁℃???
DUAL UP-COUNTERS 双向上计数器
Replaced by SN54S74 : Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CDIP -55 to 125
Dual Up-Counters(双加计数
|
STMicroelectronics N.V.
意法半导
ST Microelectronics
SGS Thomson Microelectronics
|
| HD74LVC74 |
Dual D-type Flip Flops with Preset and Clear
|
Hitachi Semiconductor
|
| HD74LVC74 HD74LVC74FPEL HD74LVC74TELL |
Dual D-type Flip Flops with Preset and Clear
|
Renesas Electronics Corporation
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| UT54ACS74 UT54ACTS74 |
Radiation-Hardened Dual D Flip-Flops with Clear & Preset
|
ETC
|
