| PART |
Description |
Maker |
| K4D623238B-GQC |
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM wi Extended Data Out Data Sheet
|
Samsung Electronic
|
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13S128324A-2M |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| HI-8783 |
(HI-8783 - HI-8785) 8 bit parallel data converted to 429 & 561 serial data out
|
Holt Integrated Circuits
|
| HI-8785PSTF HI-8783 HI-8783_06 HI-8783PDI HI-8783P |
ARINC INTERFACE DEVICE 8 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
| HI-8788PQTF HI-8787 HI-8787_06 HI-8787PQI HI-8787P |
ARINC INTERFACE DEVICES 16 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
| NT5DS4M32EG-5 NT5DS4M32EG-5G NT5DS4M32EG-6 |
1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
|
NanoAmp Solutions, Inc.
|
| SH713609 SH7137 |
SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer
|
Renesas Electronics Corporation
|
| SDA006 SDA006-7 |
Data Line Protection
DATA BUS TRANSIENT SUPPRESSOR/3-PHASE FULL WAVE BRIDGE RECTIFIER
|
Dionics Inc.
DIODES[Diodes Incorporated]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
