| PART |
Description |
Maker |
| MCP602-IOT MCP604-ISL MCP604-ISN MCP604-IST MCP601 |
300000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
300000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
300,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
2.7V to 5.5V Single Supply CMOS Op Amps 2.7V5.5V单电源CMOS运算放大
2.7V to 5.5V Single Supply CMOS Op Amps 2.7V.5V单电源CMOS运算放大
|
Microchip Technology Inc.
Microchip Technology, Inc.
|
| ICS9148-32 ICS9148F-32 9148F-32 |
BX Main Clock, 2 Chip Clock, Supports 66.6 - 100MHz
Pentium/ProTM System Clock Chip
100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
|
ICST[Integrated Circuit Systems]
INTEGRATED DEVICE TECHNOLOGY INC
|
| CPLL-018 CPLL-018-200.00 CPLL-018-25-200.00 CPLL-0 |
Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
|
Crystek Corporation
|
| IDT77950 77950_DS_39296 IDT77955 |
SwitchStar ATM 1.24Gbps Switch Reference Design **NOT RECOMMENDED FOR NEW DESIGNS**
155Mbps Optical Line Card for IDT77950 Switch **NOT RECOMMENDED FOR NEW DESIGNS**
SwitchStarTM Reference Design Using the IDT77V400 Switching Memory and IDT77V500 Switch Controller
From old datasheet system
|
Integrated Device Technology
IDT
ETC[ETC]
List of Unclassifed Manufacturers
|
| AEC-6913-A1M-1010 AEC-6913-A2M-1010 |
Design for Industrial Automation, Reliable Design: RS-422/485 10x. DIO
|
AAEON Technology
|
| TND301 MC100LVEP34 MC100EP016 MC100EP139 MC100EP16 |
Clock Management Design Using Low Skew and Low Jitter Devices
|
ONSEMI[ON Semiconductor]
|
| STU11NC60 7170 |
OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN
From old datasheet system
|
STMicroelectronics
|
| DS33Z11DK |
Ethernet Transport Design Kit
From old datasheet system
|
Maxim
|
| AN55 |
Design Notes for a 2-Pole Filter
From old datasheet system
|
Cirrus Logic
|
| AN12 |
AT&T 62411 Design Considerations Jitter and Synchronization
From old datasheet system
|
Cirrus Logic
|
| CY3610J CY3610 3610 |
Warp2ISR Verilog ISR?Design Kit for CPLDs
From old datasheet system
|
Cypress
|
