| PART |
Description |
Maker |
| HYS72D256520GR-7-A HYS72D256520GR |
184 Pin Registered Double Data Rate SDRAM Modules
|
INFINEON[Infineon Technologies AG]
|
| HYS64D128320HU-5-B HYS72D128320HU-5-B HYS64D64300H |
42184-Pin Unbuffered Double-Data-Rate Memory Modules
|
Qimonda AG
|
| 3TB41-15 |
TB Series Basic Switch, Double Pole Double Throw Double Break Circuitry, 10 A at 250 Vac, Pin Plunger Actuator, Silver Contacts, Screw Termination
|
Honeywell
|
| HYS72T512341HKP HYS72T512341HJP HYS72T512341HHP HY |
240-Pin Registered DDR2 SDRAM Modules 512M X 72 DDR DRAM MODULE, DMA240
240-Pin Registered DDR2 SDRAM Modules 240针DDR2 SDRAM的注册模
|
Qimonda AG
|
| HYS72D32000GU-7-B HYS72D32000GU-7F-B HYS72D64320GU |
184-Pin Unbuffered Dual-In-Line Memory Modules
|
INFINEON[Infineon Technologies AG]
|
| GS8170DD36C-333 GS8170DD36C-250 GS8170DD36C-300 GS |
18Mb x2Lp CMOS I/O Double Data Rate SigmaRAM 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
18Mb 1x2Lp CMOS I/O Double Data Rate SigmaRAM 35.71x2Lp的CMOS的I / O双数据速率SigmaRAM
|
GSI Technology, Inc.
|
| MT8VDDT3264AG-40BC4 |
256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
|
Micron Technology
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
