PART |
Description |
Maker |
LHF16KA9 LH28F160S5T-L70 LH28F160S5T-L70A |
Flash Memory 16M (2MB × 8/1MB × 16)
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Sharp Electrionic Components
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LHF16KA7 LH28F160S3HT-L10A |
Flash Memory 16M (2MB 8/1MB 16) Flash Memory 16M (2MB × 8/1MB × 16)
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Sharp Corporation Sharp Electrionic Components
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LH28F160S3HT-L10A LHF16KA7 |
Flash Memory 16M (2MB x 8/1MB x 16) Flash Memory 16M (2MB bb 8/1MB bb 16)
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SHARP
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M29W160DB M29W160DB70M1T M29W160DB70M6T M29W160DB7 |
16 Mbit 2Mb x8 or 1Mb x16, Boot Block 3V Supply Flash Memory 16 Mbit (2Mb x8 or 1Mb x16, Boot Block) 3V Supply Flash Memory
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ST Microelectronics STMICROELECTRONICS[STMicroelectronics]
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M295V160BB70N1T M29F160 M295V160BB55N1T M295V160BT |
16 Mbit 2Mb x8 or 1Mb x16, Boot Block Single Supply Flash Memory 16 Mbit 2Mb x8 or 1Mb x16 / Boot Block Single Supply Flash Memory 8-Bit, 0.1 us Dual MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro I/F 20-PLCC -25 to 85 16-Bit Bus Transceiver with 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 16兆位Mb x81兆x16插槽,启动座单电源闪 16 Mbit 2Mb x8 or 1Mb x16, Boot Block Single Supply Flash Memory 16兆位Mb x81兆x16插槽,启动座单电源闪 8-Bit, 0.1 us Dual MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro I/F 20-PDIP -40 to 85 16兆位Mb x81兆x16插槽,启动座单电源闪 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TVSOP -40 to 85 16兆位Mb x8兆x16插槽,启动座单电源闪 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TVSOP -40 to 85 16兆位Mb x8兆x16插槽,启动座单电源闪
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ST Microelectronics 意法半导 STMicroelectronics N.V.
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M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation. Renesas Electronics, Corp.
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GS8322Z18B-166I GS8322Z18B-225 GS8322Z18B-225I GS8 |
166MHz 8.5ns 2M x 18 36Mb NBT pipelined/flow through SRAM 225MHz 6.5ns 2M x 18 36Mb NBT pipelined/flow through SRAM 133MHz 11ns 2M x 18 36Mb NBT pipelined/flow through SRAM 150MHz 10ns 2M x 18 36Mb NBT pipelined/flow through SRAM 200MHz 7.5ns 2M x 18 36Mb NBT pipelined/flow through SRAM
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GSI Technology
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MT54W4MH9B MT54W4MH8B MT54W1MH36B-5 MT54W1MH36B-7. |
36Mb QDRII SRAM 2-WORD BURST 36Mb QDR⑩II SRAM 2-WORD BURST ⑩分6MB四年防务审查II SRAM字爆 36Mb QDR?┥I SRAM 2-WORD BURST
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Micron Technology, Inc.
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IS61NVP102436A IS61NVP102436A-166B3 IS61NVP102436A |
1Mb x 36 and 2Mb x 18 STATE BUS SRAM 1M X 36 STANDARD SRAM, PBGA165 PLASTIC, BGA-165 1M X 36 STANDARD SRAM, PDSO100 TQFP-100 2M X 18 STANDARD SRAM, PBGA165
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Integrated Silicon Solution, Inc. INTEGRATED SILICON SOLUTION INC Integrated Silicon Solu...
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KMM5322104CKU |
2MB X 32 DRAM Simm Using 2MB X 8
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Samsung Semiconductor
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GS8321ZV36E-250I GS8321ZV36E-225I GS8321ZV36E-133 |
Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/C Max Reference; Package: 20-TSSOP; Temperature Range: 0°C to 70°C 36Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 36 ZBT SRAM, 8.5 ns, PBGA165 36Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 36 ZBT SRAM, 8 ns, PBGA165 36Mb Pipelined and Flow Through Synchronous NBT SRAM 2M X 18 ZBT SRAM, 8.5 ns, PBGA165 36Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 32 ZBT SRAM, 6.5 ns, PBGA165
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GSI Technology, Inc.
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