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R1QNA4436RBG-15 -    144-Mbit QDR?II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

R1QNA4436RBG-15_8819653.PDF Datasheet
 Full text search :    144-Mbit QDR?II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)
 Product Description search :    144-Mbit QDR?II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

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72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
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36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
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36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
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