| PART |
Description |
Maker |
| MC10EL31-D |
5V ECL D Flip-Flop With Set and Reset
|
ON Semiconductor
|
| MC100LVEL31D MC100LVEL31DG MC100LVEL31DR2 MC100LVE |
3.3V ECL D Flip-Flop with Set and Reset
|
ONSEMI[ON Semiconductor]
|
| MC100EP131FAR2G |
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock; Package: 32 LEAD LQFP 7x7, 0.8P; No of Pins: 32; Container: Tape and Reel; Qty per Container: 2000 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32
|
ON Semiconductor
|
| MC100LVEL29-D |
3.3V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
|
ON Semiconductor
|
| MC100LVEL29DW MC100LVEL2906 MC100LVEL29DWR2G MC100 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
|
ONSEMI[ON Semiconductor]
|
| MC100EP29DT MC100EP29DTR2 MC10EP29 MC10EP29DT MC10 |
From old datasheet system
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
|
ON Semiconductor
|
| ECLSOIC8EVB NB6L16D MC100EL01D MC100EL04D MC100EL0 |
3.3V / 5V ECL JK Flip Flop
5V ECL 2-Input XOR/XNOR
5V ECL Divide by 2 Divider
Evaluation Board Manual for High Frequency SOIC 8
|
ONSEMI[ON Semiconductor]
|
| 74AUP1G74GT-G 74AUP1G74GF |
Low-power D-type flip-flop with set and reset; positive-edge trigger AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| 74AUP1G74GD 74AUP1G74GM125 |
Low-power D-type flip-flop with set and reset; positive-edge trigger
Low-power D-type flip-flop with set and reset; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors
|
| MC10EP35-D |
3.3V / 5V ECL JK Flip-Flop
|
ON Semiconductor
|
