| PART |
Description |
Maker |
| 715C20KTD10 |
CAP HGH VOLTAGE 715C 20KVDC 1000PF ?20% N4700 E4 - Bulk
|
Vishay Cera-Mite
|
| ISPLSI2064VE ISPLSI2064VE-100LB100 ISPLSI2064VE-10 |
3.3V In-System Programmable High Density SuperFAST?PLD
3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 7 ns, PQFP44
CRYSTAL 16.0 MHZ 20PF SMD EE PLD, 13 ns, PQFP100
CRYSTAL 20.0 MHZ 20PF SMD
RES 180K-OHM 1% 0.063W 200PPM THK-FILM SMD-0402 TR-7-PA2MM
3.3V In-System Programmable High Density SuperFAST PLD
3.3V In-System Programmable High Density SuperFAST⑩ PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
280 MHz 3.3V in-system prommable superFAST high density PLD
|
Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| ISPLSI2192VE-135LT128 ISPLSI2192VE-180-L-T128 ISPL |
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
3.3VIn-SystemProgrammableSuperFASTHighDensityPLD
RELAY SSR 110A 240VAC AC INPUT
3.3V In-System Programmable SuperFASTHigh Density PLD
|
LATTICE[Lattice Semiconductor]
LatticeSemiconductor
Lattice Semiconductor Corporation
|
| ISPLSI2192VL-100LB144 ISPLSI2192VL-100LT128 ISPLSI |
2.5V In-System Programmable SuperFAST High Density PLD
TRIAC STANDARD 12A 400V TO-220AB
2.5V In-System Programmable SuperFASTHigh Density PLD
|
Lattice Semiconductor Corporation
|
| 1032-60LG_883 1032-60LJ 1032-60LJI 1032-60LT 1032- |
High-Density Programmable Logic
In-System Programmable High Density PLD
|
LATTICE[Lattice Semiconductor]
|
| MACH211SP-12 MACH211SP-7JC MACH211SP-7VC MACH211SP |
RES 35.7K-OHM 1% 0.1W 100PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA
SCREW MACHINE SLOTTED 6-32X3/4
High-Density EE CMOS Programmable Logic EE PLD, 16 ns, PQCC44
High-Density EE CMOS Programmable Logic 高密度电子工程CMOS可编程逻辑
|
Advanced Micro Devices, Inc.
ADVANCED MICRO DEVICES INC
|
| ISPLSI2192VE100LB144 ISPLSI2192VE100LB144I ISPLSI2 |
3.3V In-System Programmable SuperFAST?High Density PLD
3.3V In-System Programmable SuperFAST?/a> High Density PLD
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST垄芒 High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
EE PLD, 13 ns, PQFP128
|
LATTICE SEMICONDUCTOR CORP
|
| STP80N03L-06 4881 |
N-Channel Enhancement Mode "Ultra High Density" Power MOS Transistor(Ｎ沟道增强模式高密度功率ＭＯＳ晶体管) N沟道增强模式“超高密度”功率MOS晶体管（不适用沟道增强模式高密度功率马鞍山晶体管）
N - CHANNEL ENHANCEMENT MODE ULTRA HIGH DENSITY POWER MOS TRANSISTOR
N - CHANNEL ENHANCEMENT MODE ULTRA HIGH DENSITY POWER MOS TRANSISTOR
From old datasheet system
N - CHANNEL ENHANCEMENT MODE "ULTRA HIGH DENSITY" POWER MOS TRANSISTOR
|
STMicroelectronics N.V.
ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
SGS Thomson Microelectronics
|
| SET111411 SET111403 SET111412 SET111419 SET111404 |
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?400V,娓╁害55???骞冲??存??垫?45A,楂??搴?澶х?娴?涓???ㄦ尝妗ユ?娴??)
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?1000V,娓╁害55???骞冲??存??垫?30A,楂??搴?澶х?娴?涓???ㄦ尝妗ユ?娴??)
3 PHASE, 30 A, SILICON, BRIDGE RECTIFIER DIODE
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?150V,娓╁害55???骞冲??存??垫?45A,楂??搴?澶х?娴??涓???ㄦ尝妗ユ?娴??)
High Density,High Current,3-Phase Full Wave Bridge Rectifier(反向电压1000V,温度55℃时平均整流电流45A,高密大电三相全波桥整流器) 高密度，大电3 -相全波桥式整流器（反向电000V的温5℃时平均整流电流45A条，高密度，大电流，三相全波桥整流器
HIGH CURRENT, 3-PHASE FULL WAVE BRIDGE ASSEMBLY
|
Semtech, Corp.
Semtech Corporation
|
| LTV8192M LTV-819-1S-TA LTV829S-V LTV-829S-TA LTV82 |
High Density Mounting Type Photocoupler 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER
High Density Mounting Type Photocoupler 2 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER
High Density Mounting Type Photocoupler(762.22 k) 高密度安装类型光电耦合62.22十一
|
Lite-On Technology, Corp.
|
| QL2005 QL2005-1PQ208I QL2005-1PQ208C |
3.3V and 5.0V pASIC 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
3.3V and 5.0V pASICò 2 FPGA
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(楂??锛?????瀵?害锛????????????у己??.3V??.0V pASIC 2绯诲??哄?缂???昏??ㄤ欢)
|
QuickLogic Corp.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
