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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
March 1999
NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPITM) Synchronous Bus)
General Description
The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral Interface) CMOS EEPROM which is designed for high-reliability non-volatile data storage applications. The SPI interface features a byte-wide format (all data is transferred in 8-bit words) to interface with the Motorola 68HC11 microprocessor, or equivalent, at a 2.1MHz clock transfer rate. (This interface is considered the fastest serial communication method.) This 4-wire SPI interface allows the end user full EEPROM functionality while keeping pin count and space requirements low for maximum PC board space utilization. The SPI interface requires four I/O pins on each EEPROM device: Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data Out (SO), as well as 2 other control pins: Write Protect (WP) and HOLD (HOLD). The Write Protect pin can be used to disable the Write operation and the HOLD pin is used to interrupt the SI datastream and place the device in a Hold state during microprocessor instruction generation. Please refer to the following diagrams and description for more details. All programming cycles are completely self-timed and do not require an ERASE, or similar setup, before programming any cells. Programming can be performed in 3 modes, address (byte) write, page (4 addresses/bytes) write or partial page write. Furthermore, the EEPROM is provided with 4 levels of write protection wherein the data, once programmed, cannot be altered. This is controlled by the Status Register and is described in greater detail within this datasheet. In order to prevent spurious programming, the EEPROM has both a Write Enable command, which is immediately disabled after each programming operation, and a Write Protect (WP) pin, which must be pulled HIGH to program.
Features
s 2.1 MHz clock rate @ 2.7V to 5.5V s 4096 bits organized as 512 x 8 s Multiple chips on the same 3 wire bus with separate chip select lines s Self-timed programming cycle s Simultaneous programming of 1 to 4 bytes at a time s Status register can be polled during programming to monitor RDY/BUSY s Both the Write Protect (WP) pin and 'auto-write disable after programming' provides hardware and software write protection s Block write protect feature to protect against accidental writes s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP and 8-pin SO
Block Diagram
CS HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS WP
Address Counter/ Register
Program Enable VPP EEPROM Array 4096 Bits (512 x 8)
High Voltage Generator and Program Timer
Decoder 1 of 512
Read/Write Amps
Data In/Out Register 8 Bits
Data Out Buffer
SO
Non-Volatile Status Register
SPITM is a trademark of Motorola Corporation. DS800002-1
(c) 1999 Fairchild Semiconductor Corporation NM25C041 Rev. D.1
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N) and SO Package (M8) CS SO WP VSS 1 2 3 4 Top View 8 7 6 5 VCC HOLD SCK SI
DS800002-2
Pin Names
CS SO WP VSS SI SCK HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply
Ordering Information NM 25 C XX LZ E XX
Package Temp. Range
Letter
N M8 None V E Blank L LZ 041 C Interface 25 NM
Description
8-pin DIP 8-pin SO 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V and <1A Standby Current 4K, mode 1 CMOS SPI Fairchild Non-Volatile Memory
Voltage Operating Range
Density/Mode
2
NM25C041 Rev. D.1
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V
Operating Conditions
Ambient Operating Temperature NM25C041 NM25C041E NM25C041V Power Supply (VCC) NM25C041 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V VCC 5.5V
Symbol
ICC ICCSB IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD to Output Low Z Output Disable Time HOLD to Output High Z Write Cycle Time
Conditions
CS = VIL CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min
Max
3 50
Units
mA A A A V V V V
-1 -1 -0.3 0.7 * VCC
1 1 VCC * 0.3 VCC + 0.3 0.4
IOL = 1.6 mA IOH = -0.8 mA VCC - 0.8
2.1 2.0 2.0 (Note 2) (Note 2) (Note 3) 190 190 240 240 100 90 240 100 90 CL = 200 pF 0 100 CL = 200 pF 240 100 1-4 Bytes 10 240
MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Capacitance (Note 4) TA = 25C, f = 2.1/1 MHz
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ
3 2
Max
8 6
Units
pF pF
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns. Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested.
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Low Voltage 2.7V VCC 4.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V Ambient Operating Temperature NM25C041L/LZ NM25C041LE/LZE NM25C041LV Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 2.7V - 4.5V
DC and AC Electrical Characteristics 2.7V VCC 4.5V
25C041L/LE 25C041LZ/LZE Min. Max.
3 A 10 1 VIN = 0 to VCC VOUT = GND to VCC -1 -1 -0.3 0.7 * VCC IOL = 0.8 mA IOH = -0.8 mA VCC - 0.8 1.0 2.0 2.0 (Note 6) (Note 6) (Note 7) 410 410 500 500 100 240 500 100 240 500 0 240 500 240 1-4 Bytes 15 0 240 500 240 15 410 410 500 500 100 240 500 100 240 500 1 1 VCC * 0.3 VCC + 0.3 0.4 VCC - 0.8 1.0 2.0 2.0 -1 -1 -0.3 0.7 * VCC 10 N/A 1 1 VCC * 0.3 VCC + 0.3 0.4 A A V V V V MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
25C041LV Min Max
3
Symbol
ICC ICCSB
Parameter
Operating Current Standby Current L LZ Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min. CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD Output Low Z Output Disable Time HOLD to Output Hi Z Write Cycle Time
Conditions
CS = VIL CS = VCC
Units
mA
IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Capacitance TA = 25C, f = 2.1/1 MHz (Note 8)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 5: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 6 : The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns. Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 8: This parameter is periodically sampled and not 100% tested.
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
AC Test Conditions (Continued)
VIH CS VIL
FIGURE 1. Synchronous Data Timing
VIH SCK VIL
VIH SI VIL
VOH SO VOL
, ,,
tCSH tCSS tCSN tCLH tCLL tDIS tDIN tPD tPD tDF HI-Z HI-Z
DS800002-4
FIGURE 2. HOLD Timing
SCK
tHDS
HOLD
tHDN
tHDS
tHDN
tHZ
SO
tLZ
DS800002-6
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NM25C041 Rev. D.1
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Functional Description
TABLE 1. Op Codes Table Instruction Instruction Name Opcode
WREN WRDI RDSR WRSR READ WRITE 0000 0110 0000 0100 0000 0101 0000 0001 0000 A011 0000 A010
Operation
Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
Note: As the NM25C040 requires 9 address bits (4,096 / 8 = 512 bytes = 29), the 9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This convention only applies to 4K SPI protocol.
,,,,,
FIGURE 4. Invalid Op-Code
CS SI INVALID OP-CODE SO
As an additional protection against data corruption, the device is designed so that, if an invalid opcode is received, the device will not shift any further data into the SI latches and SO will remain tristated. In this case, CS must again be brought HIGH to re-initialize the device and a new opcode re-entered. See Figure 4.
DS800002-7
SCK
,, ,, ,, ,, ,,,,,,
FIGURE 3. SPI Protocol
CS
The NM25C041 SPI device uses a CS functionality, so the device is selected when CS is LOW (CS is to be held HIGH during 'standby' periods and between instruction sets). As stated above, the SPI protocol defines this as a MODE 1 part, with a CLOCK PHASE 1 and CLOCK POLARITY 0. This means that the part is active with CS = 0 (VIL), all INPUT data is latched into the device on the RISING edge of SCK and all OUTPUT data is clocked out on the FALLING edge of SCK.
READ STATUS REGISTER (RDSR): The Read Status Register (RDSR) instruction provides access to the status register which is used to interrogate the READY/BUSY and WRITE ENABLE status of the chip. Two non-volatile status register bits are used to select one of four levels of BLOCK WRITE PROTECTION. The status register format is shown in Table 2.
...
SI
Bit 7
Bit 6
...
Bit 1
Bit 0
READ SEQUENCE: Reading the memory via the SPI link requires the following sequence. The CS line is pulled low to select the device. The READ op-code (which includes A8) is transmitted on the SI line followed by the byte address (A7-A0) to be read. After this is done, data on the SI line becomes don't care. The data (D7-D0) at the address specified is then shifted out on the SO line. If only one byte is to be read, the CS line can be pulled back to the high level. It is possible to continue the READ sequence as the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached (1FF), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous READ cycle. See Figure 5.
SO
Bit 7
Bit 6
...
Bit 1
Bit 0
FIGURE 5. Read Sequence
CS
DS800002-5
The HOLD pin operation is used when the device is selected (CS LOW) and the application requires that the SI datastream be stopped and then restarted. The HOLD pin allows a fully 'static' operation, wherin the device may be put on HOLD by bringing the HOLD pin LOW (VIL). During the HOLD state, SCK must be HIGH and CS must remain LOW (device selected). In order to resume EEPROM serial communication, HOLD must be again brought HIGH and the SCK/SI signals resumed. During the HOLD state, SO is tri-stated (high impedance).
SI
READ OP-CODE
BYTE ADDR (n)
SO
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+3)
DS800002-8
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Functional Description (Continued)
TABLE 2. Status Register Format Bit 7
X
X = Don't Care
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Status register Bit 0 = 0 (RDY) indicates that the device is READY; Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0 (WEN) indicates that the device is not WRITE ENABLED; Bit 1 = 1 indicates that the device is WRITE ENABLED. Non-volatile status register Bits 2 and 3 (BP0 and BP1) indicate the level of BLOCK WRITE PROTECTION selected. The block write protection levels and corresponding status register control bits are shown in Table 3. Note that if a RDSR instruction is executed during a programming cycle only the RDY bit is valid. All other bits are 1s. See Figure 6.
,,,,,
FIGURE 8. Write Disable
CS SI WRDI OP-CODE SO
WRITE DISABLE (WRDI): To protect against accidental data disturbance the WRITE DISABLE (WRDI) instruction disables all programming modes. The WRITE DISABLE instruction is independent of the status of the WP pin. See Figure 8.
DS800002-11
TABLE 3. Block Write Protection Levels Level Status Register Bits BP1
0 1 2 3 0 0 1 1
BP0
0 1 0 1
Array Address Protected
None 180-1FF 100-1FF 000-1FF
WRITE SEQUENCE: To program the device the WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a WRITE instruction must be executed. Moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the Block Write Protection Level. See Table 3. A WRITE command requires the following sequence. The CS line is pulled low to select the device, then the WRITE op-code (which includes A8) is transmitted on the SI line followed by the byte address (A7-A0) and the corresponding pro-data (D7-D0) to be programmed. Programming will start after the CS pin is forced back to a high level. Note that the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 data bit. The READY/BUSY status of the device can be determined by executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 = 1 indicates that the WRITE cycle is still in progress and Bit 0 = 0 indicates that the WRITE cycle has ended. During the WRITE programming cycle (Bit 0 = 1) only the READ STATUS REGISTER instruction is enabled.
,, ,,,,,,,,,,,
FIGURE 6. Read Status
CS SI RDSR OP-CODE
FIGURE 9. Start WRITE Condition
CS
SO
SR_DATA MSB...LSB
SCK
DS800002-9
,,,,,
FIGURE 7. Write Enable
CS SI WREN OP-CODE SO
WRITE ENABLE (WREN): When VCC is applied to the chip, it "powers up" in the write disable state. Therefore, all modes must be preceded by a WRITE ENABLE (WREN) instruction. Additionally the WP pin must be held high during a WRITE ENABLE instruction. At the completion of a WRITE or WRSR cycle the device is automatically turned to the write disable state. Note that a WRITE DISABLE (WRDI) instruction or forcing the WP pin low will also return the device to the write disable state. See Figure 7.
SI
SO
,,,,,,
D2 D1 D0
DS800002-12
DS800002-10
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Functional Description (Continued)
The NM25C041 is capable of a four byte PAGE WRITE operation. After receipt of each byte of data the two low order address bits are internally incremented by one. The seven high order bits of the address will remain constant. If the master should transmit more than four bytes of data, the address counter will "roll over", and the previously loaded data will be reloaded. See Figure 10. Note that the first four bits are don't care bits followed by BP1 and BP0 then two additional don't care bits. Programming will start after the CS pin is forced back to a high level. As in the WRITE instruction the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the last don't care bit. See Figure 12.
FIGURE 10. 4 Page Byte Write
CS
SI
SO
At the completion of a WRITE cycle the device is automatically returned to the write disable state. If the WP pin is forced low or the device is not WRITE enabled, the device will ignore the WRITE instruction and return to the standby state when CS is forced high. A new CS falling edge is required to re-initialize the serial communication. WRITE STATUS REGISTER (WRSR): The WRITE STATUS REGISTER (WRSR) instruction is used to program the nonvolatile status register Bits 2 and 3 (BP0 and BP1). As in the WRITE mode the WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a WRSR instruction must be executed. The WRSR command requires the following sequence. The CS line is pulled low to select the device and then the WRSR op-code is transmitted on the SI line followed by the data to be programmed (see Figure 11).
,,,,,,,,,,,,, ,,
FIGURE 12. Start WRSR Condition
CS
WRITE OP-CODE BYTE ADDR(n) DATA (n) DATA (n+1) DATA (n+2) DATA (n+3)
SCK
DS800002-13
SI
SO
The READY/BUSY status of the device can be determined by executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 = 1 indicates that the WRSR cycle is still in progress and Bit 0 = 0 indicates that the WRSR cycle has ended. At the completion of a WRSR cycle the device is automatically returned to the write disable state.
,,,,,,
tDIS tDIN
BP0
tCSN
DS800002-15
,,,,,,,
FIGURE 11. Write Status Register
CS SI WRSR OP-CODE SR_DATA XXXXBP1BP0XX SO
DS800002-14
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Order Number NM25C041M8 Package Number M08A
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NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1 0.032 0.005 (0.813 0.127) RAD 0.250 - 0.005 (6.35 0.127) Pin #1 IDENT
8
7
8
+
7
6
5
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524) 0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Order Number NM25C041N Package Number N08E
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Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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