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FEATURES Improved Replacement for: INA117P and INA117KU 270 V Common-Mode Voltage Range Input Protection to: 500 V Common Mode 500 V Differential Wide Power Supply Range ( 2.5 V to 18 V) 10 V Output Swing on 12 V Supply 1 mA Max Power Supply Current HIGH ACCURACY DC PERFORMANCE 3 ppm Max Gain Nonlinearity 20 V/ C Max Offset Drift (AD629A) 10 V/ C Max Offset Drift (AD629B) 10 ppm/ C Max Gain Drift EXCELLENT AC SPECIFICATIONS 77 dB Min CMRR @ 500 Hz (AD629A) 86 dB Min CMRR @ 500 Hz (AD629B) 500 kHz Bandwidth APPLICATIONS High Voltage Current Sensing Battery Cell Voltage Monitor Power Supply Current Monitor Motor Control Isolation
High Common-Mode Voltage Difference Amplifier AD629
FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic Mini-DIP (N) and SOIC (R) Packages
21.1k REF(-) 1 380k -IN 2 +IN 3 -VS 4 380k
6 7
380k
8
NC +VS OUTPUT REF(+)
20k
5
AD629
NC = NO CONNECT
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input common-mode voltage range. It is a precision device that allows the user to accurately measure differential signals in the presence of high common-mode voltages up to 270 V. The AD629 can replace costly isolation amplifiers in applications that do not require galvanic isolation. The device will operate over a 270 V common-mode voltage range and has inputs that are protected from common-mode or differential mode transients up to 500 V. The AD629 has low offset, low offset drift, low gain error drift, as well as low common-mode rejection drift, and excellent CMRR over a wide frequency range. The AD629 is available in low-cost, plastic 8-lead DIP and SOIC packages. For all packages and grades, performance is guaranteed over the entire industrial temperature range from -40C to +85C.
100
COMMON-MODE REJECTION RATIO - dB
95
2mV/DIV
85 80 75 70 65 60 55 50 20 100 1k FREQUENCY - Hz 10k 20k
OUTPUT ERROR - 2mV/DIV
90
60V/DIV -240 -120 0 120 COMMON-MODE VOLTAGE - Volts 240
Figure 1. Common-Mode Rejection Ratio vs. Frequency
Figure 2. Common-Mode Operating Range. Error Voltage vs. Input Common-Mode Voltage
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD629-SPECIFICATIONS (T = 25 C, V =
A S
15 V unless otherwise noted)
AD629A AD629B
Max Min Typ 1 0.01 4 1 3 0.1 3 110 96 Max Unit V/V % ppm ppm ppm/C mV mV V/C dB dB dB dB dB V V k k V V V mA pF kHz V/s kHz s s s V p-p nV/Hz 18 1 V mA mA C Min Typ 1 0.01 4 1 3 0.2
Parameter GAIN Nominal Gain Gain Error Gain Nonlinearity Gain vs. Temperature OFFSET VOLTAGE Offset Voltage vs. Temperature vs. Supply (PSRR) INPUT Common-Mode Rejection Ratio
Condition VOUT = 10 V, RL = 2 k
0.05 10 10 1 20 90 86 82 86 270 13
RL = 10 k TA = TMIN to TMAX
0.03 10 3 10 0.5 1 10
VS = 5 V TA = TMIN to TMAX VS = 5 V to 15 V VCM = 250 V dc TA = TMIN to TMAX VCM = 500 V p-p DC to 500 Hz VCM = 500 V p-p DC to 1 kHz Common-Mode Differential Common-Mode Differential RL = 10 k RL = 2 k VS = 12 V, RL = 2 k Stable Operation
84 77 73 77
6 100 88
88
90 270 13 200 800 13 12.5 10 1000
Operating Voltage Range Input Operating Impedance OUTPUT Operating Voltage Range
200 800 13 12.5 10 1000 500 2.1 28 15 12 5 15 550 2.5 18 1 2.5
Output Short Circuit Current Capacitive Load DYNAMIC RESPONSE Small Signal -3 dB Bandwidth Slew Rate Full Power Bandwidth Settling Time
25
25
1.7 VOUT = 20 V p-p 0.01%, VOUT = 10 V Step 0.1%, VOUT = 10 V Step 0.01%, VCM = 10 V Step, VDIFF = 0 V
1.7
500 2.1 28 15 12 5 15 550
OUTPUT NOISE VOLTAGE 0.01 Hz to 10 Hz Spectral Density, 100 Hz1 POWER SUPPLY Operating Voltage Range Quiescent Current TEMPERATURE RANGE For Specified Performance
NOTES 1 See Figure 19. Specifications subject to change without notice.
VOUT = 0 V TMIN to TMAX TA = TMIN to TMAX -40
0.9 1.2
0.9 1.2 -40
+85
+85
-2-
REV. A
AD629
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves Input Voltage Range, Continuous . . . . . . . . . . . . . . . . 300 V Common-Mode and Differential, 10 sec . . . . . . . . . . . 500 V Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Pin 1, Pin 5 . . . . . . . . . . . . . . . . . . -VS - 0.3 V to +VS + 0.3 V Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP, JA = 100C/W; 8-Lead SOIC Package, JA = 155C/W.
2.0
THEORY OF OPERATION
The AD629 is a unity gain differential-to-single-ended amplifier (Diff Amp) that can reject extremely high common-mode signals (in excess of 270 V with 15 V supplies). It consists of an operational amplifier (Op Amp) and a resistor network. In order to achieve high common-mode voltage range, an internal resistor divider (Pin 3, Pin 5) attenuates the noninverting signal by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the feedback resistor) restores the gain to provide a differential gain of unity. The complete transfer function equals: VOUT = V (+IN ) - V (-IN ) Laser wafer trimming provides resistor matching so that commonmode signals are rejected while differential input signals are amplified. The op amp itself, in order to reduce output drift, uses super beta transistors in its input stage The input offset current and its associated temperature coefficient contribute no appreciable output voltage offset or drift. This has the added benefit of reducing voltage noise because the corner where 1/f noise becomes dominant is below 5 Hz. In order to reduce the dependence of gain accuracy on the op amp, the open-loop voltage gain of the op amp exceeds 20 million, and the PSRR exceeds 140 dB.
21.1k REF(-) 1 380k 380k
8 7
MAXIMUM POWER DISSIPATION - Watts
TJ = 150 C 8-LEAD MINI-DIP PACKAGE 1.5
NC +VS OUTPUT REF(+)
1.0
-IN
2
+IN 3
380k
6
8-LEAD SOIC PACKAGE 0.5
20k -VS 4
5
AD629
NC = NO CONNECT
Figure 4. Functional Block Diagram
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C 70 80 90
Figure 3. Derating Curve of Maximum Power Dissipation vs. Temperature for SOIC and PDIP Packages
ORDERING GUIDE
Model AD629AR AD629AR-REEL1 AD629AR-REEL72 AD629BR AD629BR-REEL1 AD629BR-REEL72 AD629AN AD629BN
NOTES 1 13" Tape and Reel of 2500 each 2 7" Tape and Reel of 1000 each
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic DIP 8-Lead Plastic DIP
Package Option SO-8 SO-8 SO-8 SO-8 SO-8 SO-8 N-8 N-8
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD629 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD629 -Typical Performance Characteristics (@25 C, V =
S
100
15 V unless otherwise noted)
400 360
Volts
COMMON-MODE REJECTION RATIO - dB
90 80 70 60 50 40 30 20 10 0 100 1k 10k 100k FREQUENCY - Hz 1M 10M
TA = +25 C
320 280 240 200 160 120 80 40 0 0 2 4 6 8 10 12 14 16 POWER SUPPLY VOLTAGE - Volts 18 20 TA = +85 C TA = -40 C
Figure 5. Common-Mode Rejection Ratio vs. Frequency
Figure 8. Common-Mode Operating Range vs. Power Supply Voltage
2mV/DIV VS = 18V
COMMON-MODE VOLTAGE -
RL = 10k
RL = 2k VS =
OUTPUT ERROR - 2mV/DIV
18V
OUTPUT ERROR - 2mV/DIV
VS =
15V
VS =
15V
VS =
12V
VS =
12V
VS = -20 -16 -12
10V -8 -4 0 4 VOUT - Volts 8 12
4V/DIV 16 20
VS = -20 -16 -12 -8
10V -4 0 4 VOUT - Volts 8 12
4V/DIV 16 20
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 10 k (Curves Offset for Clarity)
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 2 k (Curves Offset for Clarity)
RL = 1k VS =
OUTPUT ERROR - 2mV/DIV
18V
OUTPUT ERROR - 2mV/DIV
VS =
5V, RL = 10k
VS =
15V
VS =
5V, RL = 2k
VS =
12V
VS =
5V, RL = 1k
VS = -20 -16 -12 -8
10V -4 0 4 VOUT - Volts 8 12
4V/DIV 16 20
-5
VS = -4
2.5V, RL = 1k -3 -2 -1 0 1 VOUT - Volts 2 3
1V/DIV 4 5
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 1 k (Curves Offset for Clarity)
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage (Curves Offset for Clarity)
-4-
REV. A
AD629
ERROR - 0.8ppm/DIV
-10
-5
0 VOUT - Volts
5
10
ERROR - 2ppm/DIV
-10
-8
-6
-4
-2 0 2 VOUT - Volts
4
6
8
10
Figure 11. Gain Nonlinearity; VS = 15 V, RL =10 k
Figure 14. Gain Nonlinearity; VS = 15 V, RL = 2 k
14.0 13.0 12.0 -40 C -40 C
OUTPUT VOLTAGE - Volts
11.0 10.0 9.0
VS =
15V
+85 C
+25 C
ERROR - 1ppm/DIV
-11.5
-12.0 -12.5 -13.0 +85 C -40 C +25 C
-10
-8
-6
-4
-2 0 2 VOUT - Volts
4
6
8
10
-13.5
0
2
4
6 8 10 12 14 OUTPUT CURRENT - mA
16
18
20
Figure 12. Gain Nonlinearity; VS = 12 V, RL =10 k
Figure 15. Output Voltage Operating Range vs. Output Current; VS = 15 V
11.5 10.5 -40 C 9.5
+85 C -40 C
OUTPUT VOLTAGE - Volts
ERROR - 6.67ppm/DIV
8.5
+25 C
VS =
7.5 6.5
12V
+85 C
-9.0
-9.5 -10.0 -10.5 +85 C -40 C +25 C
-3.0 -2.4 -1.8 -1.2
-0.6 0 0.6 VOUT - Volts
1.2
1.8
2.4
3.0
-11.0
0
2
4
6 8 10 12 14 OUTPUT CURRENT - mA
16
18
20
Figure 13. Gain Nonlinearity; VS = 5 V, RL =1 k
Figure 16. Output Voltage Operating Range vs. Output Current; VS = 12 V
REV. A
-5-
AD629
4.5 3.5 -40 C 2.5 +85 C +85 C -40 C
RL = 2k CL = 0pF
OUTPUT VOLTAGE - Volts
1.5 0.5
VS =
5V
+25 C
-2.0
-2.5 -3.0 -3.5 +25 C -4.0 +85 C -40 C
+85 C
+25 C
25mV/DIV
16 18 20
4 s/DIV
0
2
4
6 8 10 12 14 OUTPUT CURRENT - mA
Figure 17. Output Voltage Operating Range vs. Output Current; VS = 5 V
Figure 20. Small Signal Pulse Response; G = 1, RL = 2 k
120
POWER SUPPLY REJECTION RATIO - dB
+VS -VS
RL = 2k CL = 1000pF
110 100 90 80 70 60 50 40 30 0.1 1 10 100 FREQUENCY - Hz 1k 10k
25mV/DIV
4 s/DIV
Figure 18. Power Supply Rejection Ratio vs. Frequency
Figure 21. Small Signal Pulse Response; G = 1, RL = 2 k, CL = 1000 pF
5.0 4.5 4.0 3.5
G = +1 RL = 2k CL = 1000pF
V/ Hz
3.0 2.5 2.0 1.5 1.0 0.5
5V/DIV
0.01 0.1 1 10 100 FREQUENCY - Hz 1k 10k 100k
5 s/DIV
Figure 19. Voltage Noise Spectral Density vs. Frequency
Figure 22. Large Signal Pulse Response; G = 1, RL = 2 k, CL = 1000 pF
-6-
REV. A
AD629
5V/DIV
+10V
5V/DIV
0V
VOUT
0V
VOUT
-10V
OUTPUT ERROR
1mV = 0.01%
OUTPUT ERROR
1mV = 0.01%
1mV/DIV
10 s/DIV
1mV/DIV
10 s/DIV
Figure 23. Settling Time to 0.01%, For 0 V to 10 V Output Step; G = -1, RL = 2 k
Figure 26. Settling Time to 0.01% for 0 V to -10 V Output Step; G = -1, RL = 2 k
350 300 250 200 150 100 50 0 -150 N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
NUMBER OF UNITS
300 N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
250
NUMBER OF UNITS
200
150
100
50
0
-100 -50 0 50 100 COMMON-MODE REJECTION RATIO - ppm
150
-900
-600
-300 0 300 OFFSET VOLTAGE - V
600
900
Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8
Figure 27. Typical Distribution of Offset Voltage; Package Option N-8
400 350 300
NUMBER OF UNITS
NUMBER OF UNITS
400
N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
350 300 250 200 150 100 50 0 -600
N = 2180 n 200 PCS. FROM 10 ASSEMBLY LOTS
250 200 150 100 50 0 -600
-400
-200 0 200 -1 GAIN ERROR - ppm
400
600
-400
-200 0 200 +1 GAIN ERROR - ppm
400
600
Figure 25. Typical Distribution of -1 Gain Error; Package Option N-8
Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8
REV. A
-7-
AD629
APPLICATIONS Basic Connections
REF(-)
1
21.1k 380k
2
AD629
8
+VS NC
Figure 29 shows the basic connections for operating the AD629 with a dual supply. A supply voltage of between 3 V and 18 V is applied between Pins 7 and 4. Both supplies should be decoupled close to the pins using 0.1 F capacitors. 10 F electrolytic capacitors, also located close to the supply pins, may also be required if low frequency noise is present on the power supply. While multiple amplifiers can be decoupled by a single set of 10 F capacitors, each in amp should have its own set of 0.1 F capacitors so that the decoupling point can be located physically close to the power pins.
AD629
8
-IN ISHUNT RSHUNT
380k
7
VX +IN -VS 380k
3 6
+VS
0.1 F
VY
4
20k
5
REF(+) OUTPUT = VOUT -VREF
NC = NO CONNECT VREF
REF(-)
1
21.1k 380k
2
+VS 3V TO 18V NC
Figure 30. Operation with a Single Supply
-IN ISHUNT RSHUNT
380k
7
+VS
0.1 F
(SEE TEXT) RSHUNT
+IN -VS
380k
3 6
VOUT = ISHUNT REF(+)
20k
4 5
(SEE TEXT)
0.1 F NC = NO CONNECT -VS -3V TO -18V
Applying a reference voltage to REF(+) and REF(-) and operating on a single supply will reduce the input common-mode range of the AD629. The new input common-mode range depends upon the voltage at the inverting and noninverting inputs of the internal operational amplifier, labeled VX and VY in Figure 30. These nodes can swing to within 1 V of either rail. So for a (single) supply voltage of 10 V, VX and VY can range between 1 V and 9 V. If VREF is set to 5 V, the permissible common-mode range is +85 V to -75 V. The common-mode voltage ranges can be calculated using the following equation.
VCM = 20 VX / Y - 19 VREF
Figure 29. Basic Connections
()
()
The differential input signal, which will typically result from a load current flowing through a small shunt resistor, is applied to Pins 2 and 3 with the polarity shown in order to obtain a positive gain. The common-mode range on the differential input signal can range from -270 V to +270 V and the maximum differential range is 13 V. When configured as shown, the device operates as a simple gain-of-one differential-to-single-ended amplifier, the output voltage being the shunt resistance times the shunt current. The output is measured with respect to Pins 1 and 5. Pins 1 and 5 (REF(-) and REF(+)) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. Failure to do this will result in degraded common-mode rejection. Pin 8 is a no connect pin and should be left open.
Single Supply Operation
System-Level Decoupling and Grounding
Figure 30 shows the connections for operating the AD629 with a single supply. Because the output can swing to within only about 2 V of either rail, it is necessary to apply an offset to the output. This can be conveniently done by connecting REF(+) and REF(-) to a low impedance reference voltage (some analogto-digital converters provide this voltage as an output), which is capable of sinking current. Thus, for a single supply of 10 V, VREF might be set to 5 V for a bipolar input signal. This would allow the output to swing 3 V around the central 5 V reference voltage. Alternatively, for unipolar input signals, VREF could be set to about 2 V, allowing the output to swing from +2 V (for a 0 V input) to within 2 V of the positive rail.
The use of ground planes is recommended to minimize the impedance of ground returns (and hence the size of dc errors). Figure 31 shows how to work with grounding in a mixed-signal environment, that is, with digital and analog signals present. In order to isolate low-level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground returns. All ground pins from mixedsignal components such as analog-to-digital converters should be returned through the "high quality" analog ground plane. This includes the digital ground lines of mixed-signal converters that should also be connected to the analog ground plane. This may seem to break the rule of keeping analog and digital grounds separate, but in general, there is also a requirement to keep the voltage difference between digital and analog grounds on a converter as small as possible (typically <0.3 V). The increased noise, caused by the converter's digital return currents flowing through the analog ground plane, will typically be negligible. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. Note that Figure 31, as drawn, suggests a "star" ground system for the analog circuitry, with all ground lines being connected, in this case, to the ADC's analog ground. However, when ground planes are used, it is sufficient to connect ground pins to the nearest point on the low impedance ground plane.
-8-
REV. A
AD629
ANALOG POWER SUPPLY -5V +5V GND 0.1 F 0.1 F 0.1 F VDD AGND DGND VIN1 VIN2 0.1 F DIGITAL POWER SUPPLY GND +5V
shows some sample error voltages generated by a common-mode voltage of 200 V dc with shunt resistors from 20 to 2000 . Assuming that the shunt resistor has been selected to utilize the full 10 V output swing of the AD629, the error voltage becomes quite significant as RSHUNT increases.
Table I. Error Resulting from Large Values of R SHUNT (Uncompensated Circuit)
+IN -IN
-VS
+VS VOUT
12
GND
VDD
AD629
AD7892-2
PROCESSOR
RS ( ) 20 1000 2000
Error VOUT (V) 0.01 0.498 1
Error Indicated (mA) 0.5 0.498 0.5
REF(-) REF(+)
Figure 31. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY GND +5V
If it is desired to measure low current or current near zero in a high common-mode environment, an external resistor equal to the shunt resistor value may be added to the low impedance side of the shunt resistor as shown in Figure 33.
21.1k
1
0.1 F 0.1 F 0.1 F VDD VIN VREF AGND DGND VDD GND
REF(-) RCOMP ISHUNT RSHUNT
AD629
8 NC
+VS
+IN -IN
+VS
-VS VOUT
-IN
380k
2
380k
7
AD629
ADC
+VS
0.1 F VOUT
PROCESSOR
REF(-) REF(+)
+IN -VS
380k
3 6
20k
4 5
REF(+)
Figure 32. Optimal Ground Practice in a Single Supply Environment
-VS
0.1 F NC = NO CONNECT
If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure 32 shows how to minimize interference between the digital and analog circuitry. In this example, the ADC's reference is used to drive the AD629's REF(+) and REF(-) pins. This means that the reference must be capable of sourcing and sinking a current equal to VCM/ 200 k. As in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). These ground planes should be connected at the power supply's ground pin. Separate traces (or power planes) should be run from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but these can be shared by a number of devices as long as a single trace is not used to route current to both digital and analog circuitry.
Using a Large Sense Resistor
Figure 33. Compensating for Large Sense Resistors
Output Filtering
A simple 2-pole low-pass Butterworth filter can be implemented using the OP177 at the output of the AD629 to limit noise at the output, as shown in Figure 34. Table II gives recommended component values for various corner frequencies, along with the peak-to-peak output noise for each case.
REF(-)
1
21.1k 380k
AD629
8
+VS NC 0.1 F
7
+VS C1 0.1 F
380k +VS
-IN
2
380k +IN -VS
3 6
R1 20k
R2 C2
OP177 0.1 F -VS
VOUT
-VS
4
5
REF(+)
Insertion of a large shunt resistance across the input Pins 2 and 3 will imbalance the input resistor network, introducing a commonmode error. The magnitude of the error will depend on the common-mode voltage and the magnitude of RSHUNT. Table I
0.1 F NC = NO CONNECT
Figure 34. Filtering of Output Noise Using a 2-Pole Butterworth Filter
Table II. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency No Filter 50 kHz 5 kHz 500 Hz 50 Hz
R1 2.94 k 1% 2.94 k 1% 2.94 k 1% 2.7 k 10%
R2 1.58 k 1% 1.58 k 1% 1.58 k 1% 1.5 k 10%
C1 2.2 nF 10% 22 nF 10% 220 nF 10% 2.2 F 20%
C2 1 nF 10% 10 nF 10% 0.1 F 10% 1 F 20%
Output Noise (p-p) 3.2 mV 1 mV 0.32 mV 100 V 32 V
REV. A
-9-
AD629
Output Current and Buffering
The AD629 is designed to drive loads of 2 k to within 2 V of the rails, but can deliver higher output currents at lower output voltages (see Figure 15). If higher output current is required, the AD629's output should be buffered with a precision op amp such as the OP113 as shown in Figure 35. This op amp can swing to within 1 V of either rail while driving a load as small as 600 .
REF(-)
1
REF(-)
1
21.1k 380k
2
AD629
8
+VS NC 0.1 F
7
THERMOCOUPLE
-IN
380k
+IN VREF
380k
3 6
VOUT REF(+)
20k
4 5
21.1k 380k
AD629
8
+VS NC 0.1 F
7
NC = NO CONNECT
380k
-IN
2
Figure 36. A Gain of 19 Thermocouple Amplifier
0.1 F
380k +IN
3 6
Error Budget Analysis Example 1
VOUT
OP113 20k -VS 0.1 F NC = NO CONNECT
4 5
REF(+)
0.1 F -VS
Figure 35. Output Buffering Application
A Gain of 19 Differential Amplifier
While low level signals can be connected directly to the -IN and +IN inputs of the AD629, differential input signals can also be connected as shown in Figure 36 to give a precise gain of 19. However, large common-mode voltages are no longer permissible. Cold junction compensation can be implemented using a temperature sensor such as the AD590.
In the dc application below, the 10 A output current from a device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a 1 shunt resistor (Figure 37). The common-mode voltage is 200 V, and the resistor terminals are connected through a long pair of lead wires located in a high-noise environment, for example, 50 Hz/ 60 Hz 440 V ac power lines. The calculations in Table III assume an induced noise level of 1 V at 60 Hz on the leads, in addition to a full-scale dc differential voltage of 10 V. The error budget table quantifies the contribution of each error source. Note that the dominant error source in this example is due to the dc common-mode voltage.
Table III. AD629 vs. INA117 Error Budget Analysis Example 1 (V CM = 200 V dc)
Error Source ACCURACY, TA = 25C Initial Gain Error Offset Voltage DC CMR (Over Temperature)
AD629
INA117
Error, ppm of FS AD629 INA117 500 100 4,480 500 200 10,000 10,700 600 240 840 3 50 10 63 11,603
(0.0005 x 10) / 10 V x 106 (0.0005 x 10) / 10 V x 106 6 (0.001 V / 10 V) x 10 (0.002 V / 10 V) x 106 -6 6 (224 x 10 x 200 V) / 10 V x 10 (500 x 10-6 x 200 V) / 10 V x 106
Total Accuracy Error: 5,080 TEMPERATURE DRIFT (85C) Gain Offset Voltage 10 ppm/C x 60C (20 V/C x 60C) x 106/10 V 10 ppm/C x 60C (40 V/C x 60C) x 106/10 V Total Drift Error: RESOLUTION Noise, Typ, 0.01-10 Hz, V p-p CMR, 60 Hz Nonlinearity 15 V / 10 V x 106 (141 x 10-6 x 1 V) / 10 V x 106 (10-5 x 10 V) / 10 V x 106 25 V / 10 V x 106 (500 x 10-6 x 1 V) / 10 V x 106 (10-5 x 10 V) / 10 V x 106 Total Resolution Error: Total Error: 600 120 720 2 14 10 26 5,826
-10-
REV. A
AD629
OUTPUT CURRENT 10 AMPS 200VCM DC TO GROUND 1 SHUNT REF(-)
1
21.1k
8
NC +VS 0.1 F VOUT REF(+)
-IN
380k
2
380k
7
before. Note that the same kind of power line interference can happen as detailed in Example 1. However, the ac commonmode component of 200 V p-p coming from the shunt is much larger than the interference of 1 V p-p, so that this interference component can be neglected.
OUTPUT CURRENT 10 AMPS 100V AC CM TO GROUND 1 SHUNT REF(-)
1
+IN
380k
3 6
20k 60Hz POWER LINE -VS
4 5
21.1k
8
NC +VS 0.1 F VOUT REF(+)
0.1 F
AD629
NC = NO CONNECT
-IN
380k
2
380k
7
Figure 37. Error Budget Analysis Example 1. VIN = 10 V Full-Scale, VCM = 200 V DC. RSHUNT = 1 , 1 V p-p 60 Hz Power-Line Interference
Error Budget Analysis Example 2
+IN
380k
3 6
20k 60Hz POWER LINE -VS
4 5
0.1 F
AD629
NC = NO CONNECT
This application is similar to the previous example except that the sensed load current is from an amplifier with an ac commonmode component of 100 V (frequency = 500 Hz) present on the shunt (Figure 38). All other conditions are the same as
Figure 38. Error Budget Analysis Example 2. VIN = 10 V Full-Scale, VCM = 100 V at 500 Hz, RSHUNT = 1
Table IV. AD629 vs. INA117 AC Error Budget Example 2 (V CM =
100 V @ 500 Hz)
Error Source ACCURACY, TA = 25C Initial Gain Error Offset Voltage
AD629 (0.0005 x 10) / 10 V x 106 (0.001 V / 10 V) x 106
INA117 (0.0005 x 10) / 10 V x 106 (0.002 V / 10 V) x 106 Total Accuracy Error:
Error, ppm of FS AD629 INA117 500 100 600 600 120 720 2 14 10 2,820 2,846 4,166 500 200 700 600 240 840 3 50 10 10,000 10,063 11,603
TEMPERATURE DRIFT (85C) Gain 10 ppm/C x 60C Offset Voltage (20 V/C x 60C) x 106/10 V RESOLUTION Noise, Typ, 0.01-10 Hz, V p-p CMR @ 60 Hz Nonlinearity AC CMR @ 500 Hz
10 ppm/C x 60C (40 V/C x 60C) x 106/10 V Total Drift Error:
15 V / 10 V x 106 (141 x 10-6 x 1 V) / 10 V x 106 (10-5 x 10 V) / 10 V x 106 (141 x 10-6 x 200 V) / 10 V x 106
25 V / 10 V x 106 (500 x 10-6 x 1 V) / 10 V x 106 (10-5 x 10 V) / 10 V x 106 (500 x 10-6 x 200 V) / 10 V x 106 Total Resolution Error: Total Error:
REV. A
-11-
AD629
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.280 (7.11) 0.240 (6.10)
1 4
0.1574 (4.00) 0.1497 (3.80)
1
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25) 45
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
-12-
REV. A
PRINTED IN U.S.A.
C3717a-6-3/00 (rev. A)

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